kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

basic alu & simple fixes

Browse Source
This commit is contained in:
k0rrluna
2024-12-15 03:51:29 +03:00
parent cbf97501ea
commit 0f57860554
10 changed files with 3366 additions and 92 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
project/addition.v
View File

@ -1,13 +1,20 @@
module addition (
input [3:0] A, B,
output [4:0] Y
input CarryIN,
output [3:0] Y,
output CarryOUT,
output overflow
);
wire [3:0] Carry4;
halfadder h1(.A(A[0]), .B(B[0]), .Sum(Y[0]), .Carry(Carry4[0]));
fulladder f0(.A(A[0]), .B(B[0]), .Carry(CarryIN), .Sum(Y[0]), .CarryO(Carry4[0]));
fulladder f1(.A(A[1]), .B(B[1]), .Carry(Carry4[0]), .Sum(Y[1]), .CarryO(Carry4[1]));
fulladder f2(.A(A[2]), .B(B[2]), .Carry(Carry4[1]), .Sum(Y[2]), .CarryO(Carry4[2]));
fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(Y[4]));
fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(CarryOUT));
overflowDetect od1 (.opCode(2'b01), .A(A), .B(B), .Y(Y), .CarryOUT(CarryOUT), .overflowDetect(overflow));
endmodule