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basic alu & simple fixes

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k0rrluna
2024-12-15 03:51:29 +03:00
parent cbf97501ea
commit 0f57860554
10 changed files with 3366 additions and 92 deletions
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project/ALUTB.v Normal file
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module ALUTB ();
reg [3:0] A, B;
reg CarryIN;
reg opCodeA, opCodeB, opCodeC;
wire [3:0] Y;
wire CarryOUT, overflow;
ALU uut(
.A(A),
.B(B),
.CarryIN(CarryIN),
.opCodeA(opCodeA),
.opCodeB(opCodeB),
.opCodeC(opCodeC),
.Y(Y),
.CarryOUT(CarryOUT),
.overflow(overflow)
);
initial begin
$dumpfile("ALU.vcd"); // GTKWAVE SIMULTAIN DATA WAVEFORM
$dumpvars; // ICARUS VERILOG ADD ALL VARIABLES
A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b0; #5;
A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b0; #5;
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b0; #5;
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b0; #5;
A = 4'b0111; B = 4'b0111; CarryIN = 1'b1; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b0; #5;
A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b1; #5;
A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b1; #5;
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b1; #5;
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b1; #5;
A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b1; #5;
$finish; //NOT CONTAIN CLK, BUT STILL STOPS CODE
end
endmodule