f# fix
This commit is contained in:
@@ -1,32 +0,0 @@
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module PU (
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input A, // Dividend bit
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input B, // Divisor bit
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input Cin, // Carry input
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input S, // Select input for the mux
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output Y, // Output of the PU
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output COut // Carry output from the full adder
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);
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wire Sum, notB;
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// Invert B for subtraction
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not n1 (notB, B);
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// Full adder performs A - B + Cin
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fulladder f1 (
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.A(A),
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.B(notB),
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.Carry(Cin),
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.Sum(Sum),
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.CarryO(COut)
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);
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// 2:1 multiplexer to select between A and Sum
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mux2 m1 (
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.A0(A), // Input 0 of mux
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.A1(Sum), // Input 1 of mux
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.S(S), // Select line
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.Y(Y) // Output of the mux
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);
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endmodule
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@@ -1,9 +0,0 @@
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module aluboard (
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input [3:0] select,
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input [7:0] Y,
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input [3:0] A, B,
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input [2:0] opCodeA,
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output [7:0] sO
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);
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ALU alu0 ()
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@@ -1,391 +0,0 @@
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#! /usr/bin/vvp
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:ivl_version "11.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
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S_0x55ec337fbbf0 .scope module, "divider4TB" "divider4TB" 2 1;
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.timescale 0 0;
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v0x55ec33821ff0_0 .var "Dividend", 3 0;
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v0x55ec338220d0_0 .var "Divisor", 1 0;
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v0x55ec33822170_0 .net "Quotient", 3 0, L_0x55ec338251a0; 1 drivers
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v0x55ec33822240_0 .net "Remainder", 2 0, L_0x55ec33825510; 1 drivers
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S_0x55ec337fa3a0 .scope module, "uut" "divider4" 2 12, 3 1 0, S_0x55ec337fbbf0;
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.timescale 0 0;
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.port_info 0 /INPUT 4 "Dividend";
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.port_info 1 /INPUT 2 "Divisor";
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.port_info 2 /OUTPUT 4 "Quotient";
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.port_info 3 /OUTPUT 3 "Remainder";
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L_0x55ec338251a0 .functor BUFZ 4, L_0x55ec338252b0, C4<0000>, C4<0000>, C4<0000>;
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v0x55ec338218a0_0 .net "Carry", 3 0, L_0x55ec338253d0; 1 drivers
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v0x55ec338219a0_0 .net "Dividend", 3 0, v0x55ec33821ff0_0; 1 drivers
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v0x55ec33821a80_0 .net "Divisor", 1 0, v0x55ec338220d0_0; 1 drivers
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v0x55ec33821b40_0 .net "Quotient", 3 0, L_0x55ec338251a0; alias, 1 drivers
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v0x55ec33821c20_0 .net "Remainder", 2 0, L_0x55ec33825510; alias, 1 drivers
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v0x55ec33821d50_0 .net "S0", 0 0, L_0x55ec33822310; 1 drivers
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v0x55ec33821df0_0 .net "S1", 0 0, L_0x55ec338223e0; 1 drivers
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v0x55ec33821e90_0 .net "Y", 3 0, L_0x55ec338252b0; 1 drivers
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L_0x55ec33822310 .part L_0x55ec338253d0, 3, 1;
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L_0x55ec338223e0 .part L_0x55ec338253d0, 2, 1;
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L_0x55ec33822d50 .part v0x55ec33821ff0_0, 3, 1;
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L_0x55ec33822e40 .part v0x55ec338220d0_0, 1, 1;
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L_0x55ec338238c0 .part v0x55ec33821ff0_0, 2, 1;
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L_0x55ec33823960 .part v0x55ec338220d0_0, 1, 1;
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L_0x55ec33823a90 .part L_0x55ec338253d0, 3, 1;
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L_0x55ec338243b0 .part v0x55ec33821ff0_0, 1, 1;
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L_0x55ec33824530 .part v0x55ec338220d0_0, 0, 1;
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L_0x55ec33824660 .part L_0x55ec338253d0, 2, 1;
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L_0x55ec33825060 .part v0x55ec33821ff0_0, 0, 1;
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L_0x55ec33825100 .part v0x55ec338220d0_0, 0, 1;
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L_0x55ec33825210 .part L_0x55ec338253d0, 1, 1;
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L_0x55ec338252b0 .concat8 [ 1 1 1 1], L_0x55ec33824ff0, L_0x55ec338242f0, L_0x55ec33823800, L_0x55ec33822c60;
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L_0x55ec338253d0 .concat8 [ 1 1 1 1], L_0x55ec33824db0, L_0x55ec338240b0, L_0x55ec338235c0, L_0x55ec33822a20;
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L_0x55ec33825510 .part L_0x55ec338253d0, 0, 3;
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S_0x55ec337f9f60 .scope module, "PU1" "PU" 3 17, 4 1 0, S_0x55ec337fa3a0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /INPUT 1 "Cin";
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.port_info 3 /INPUT 1 "S";
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.port_info 4 /OUTPUT 1 "Y";
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.port_info 5 /OUTPUT 1 "COut";
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L_0x55ec33822480 .functor NOT 1, L_0x55ec33822e40, C4<0>, C4<0>, C4<0>;
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v0x55ec33819cb0_0 .net "A", 0 0, L_0x55ec33822d50; 1 drivers
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v0x55ec33819d70_0 .net "B", 0 0, L_0x55ec33822e40; 1 drivers
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v0x55ec33819e30_0 .net "COut", 0 0, L_0x55ec33822a20; 1 drivers
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L_0x7f82dfd33018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
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v0x55ec33819ed0_0 .net "Cin", 0 0, L_0x7f82dfd33018; 1 drivers
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v0x55ec33819fc0_0 .net "S", 0 0, L_0x55ec33822310; alias, 1 drivers
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v0x55ec3381a0b0_0 .net "Sum", 0 0, L_0x55ec33822870; 1 drivers
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v0x55ec3381a150_0 .net "Y", 0 0, L_0x55ec33822c60; 1 drivers
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v0x55ec3381a1f0_0 .net "notB", 0 0, L_0x55ec33822480; 1 drivers
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S_0x55ec337f9a30 .scope module, "f1" "fulladder" 4 16, 5 1 0, S_0x55ec337f9f60;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /INPUT 1 "Carry";
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.port_info 3 /OUTPUT 1 "Sum";
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.port_info 4 /OUTPUT 1 "CarryO";
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L_0x55ec33822a20 .functor OR 1, L_0x55ec338224f0, L_0x55ec33822730, C4<0>, C4<0>;
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v0x55ec33818dd0_0 .net "A", 0 0, L_0x55ec33822d50; alias, 1 drivers
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v0x55ec33818e90_0 .net "B", 0 0, L_0x55ec33822480; alias, 1 drivers
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v0x55ec33818f60_0 .net "Carry", 0 0, L_0x7f82dfd33018; alias, 1 drivers
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v0x55ec33819060_0 .net "CarryO", 0 0, L_0x55ec33822a20; alias, 1 drivers
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v0x55ec33819100_0 .net "Sum", 0 0, L_0x55ec33822870; alias, 1 drivers
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v0x55ec338191f0_0 .net "and1", 0 0, L_0x55ec338224f0; 1 drivers
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v0x55ec338192c0_0 .net "and2", 0 0, L_0x55ec33822730; 1 drivers
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v0x55ec33819390_0 .net "xor1", 0 0, L_0x55ec338226a0; 1 drivers
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S_0x55ec337f7800 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55ec337f9a30;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "Sum";
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.port_info 3 /OUTPUT 1 "Carry";
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L_0x55ec338224f0 .functor AND 1, L_0x55ec33822d50, L_0x55ec33822480, C4<1>, C4<1>;
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L_0x55ec338226a0 .functor XOR 1, L_0x55ec33822d50, L_0x55ec33822480, C4<0>, C4<0>;
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v0x55ec337f5bd0_0 .net "A", 0 0, L_0x55ec33822d50; alias, 1 drivers
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v0x55ec337f7e00_0 .net "B", 0 0, L_0x55ec33822480; alias, 1 drivers
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v0x55ec337f36f0_0 .net "Carry", 0 0, L_0x55ec338224f0; alias, 1 drivers
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v0x55ec337f5980_0 .net "Sum", 0 0, L_0x55ec338226a0; alias, 1 drivers
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S_0x55ec33818960 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55ec337f9a30;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "Sum";
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.port_info 3 /OUTPUT 1 "Carry";
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L_0x55ec33822730 .functor AND 1, L_0x55ec338226a0, L_0x7f82dfd33018, C4<1>, C4<1>;
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L_0x55ec33822870 .functor XOR 1, L_0x55ec338226a0, L_0x7f82dfd33018, C4<0>, C4<0>;
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v0x55ec337f7bb0_0 .net "A", 0 0, L_0x55ec338226a0; alias, 1 drivers
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v0x55ec337f9de0_0 .net "B", 0 0, L_0x7f82dfd33018; alias, 1 drivers
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v0x55ec33818b90_0 .net "Carry", 0 0, L_0x55ec33822730; alias, 1 drivers
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v0x55ec33818c60_0 .net "Sum", 0 0, L_0x55ec33822870; alias, 1 drivers
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S_0x55ec33819480 .scope module, "m1" "mux2" 4 25, 7 1 0, S_0x55ec337f9f60;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A0";
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.port_info 1 /INPUT 1 "A1";
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.port_info 2 /INPUT 1 "S";
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.port_info 3 /OUTPUT 1 "Y";
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L_0x55ec33822ad0 .functor NOT 1, L_0x55ec33822310, C4<0>, C4<0>, C4<0>;
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L_0x55ec33822b60 .functor AND 1, L_0x55ec33822870, L_0x55ec33822310, C4<1>, C4<1>;
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L_0x55ec33822bf0 .functor AND 1, L_0x55ec33822ad0, L_0x55ec33822d50, C4<1>, C4<1>;
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L_0x55ec33822c60 .functor OR 1, L_0x55ec33822b60, L_0x55ec33822bf0, C4<0>, C4<0>;
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v0x55ec33819660_0 .net "A0", 0 0, L_0x55ec33822d50; alias, 1 drivers
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v0x55ec33819750_0 .net "A1", 0 0, L_0x55ec33822870; alias, 1 drivers
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v0x55ec33819860_0 .net "S", 0 0, L_0x55ec33822310; alias, 1 drivers
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v0x55ec33819900_0 .net "Y", 0 0, L_0x55ec33822c60; alias, 1 drivers
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v0x55ec338199a0_0 .net "and1", 0 0, L_0x55ec33822b60; 1 drivers
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v0x55ec33819ab0_0 .net "and2", 0 0, L_0x55ec33822bf0; 1 drivers
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v0x55ec33819b70_0 .net "notS", 0 0, L_0x55ec33822ad0; 1 drivers
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S_0x55ec3381a320 .scope module, "PU2" "PU" 3 26, 4 1 0, S_0x55ec337fa3a0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /INPUT 1 "Cin";
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.port_info 3 /INPUT 1 "S";
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.port_info 4 /OUTPUT 1 "Y";
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.port_info 5 /OUTPUT 1 "COut";
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L_0x55ec33822fb0 .functor NOT 1, L_0x55ec33823960, C4<0>, C4<0>, C4<0>;
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v0x55ec3381c350_0 .net "A", 0 0, L_0x55ec338238c0; 1 drivers
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v0x55ec3381c410_0 .net "B", 0 0, L_0x55ec33823960; 1 drivers
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v0x55ec3381c4d0_0 .net "COut", 0 0, L_0x55ec338235c0; 1 drivers
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v0x55ec3381c570_0 .net "Cin", 0 0, L_0x55ec33823a90; 1 drivers
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v0x55ec3381c660_0 .net "S", 0 0, L_0x55ec33822310; alias, 1 drivers
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v0x55ec3381c750_0 .net "Sum", 0 0, L_0x55ec33823410; 1 drivers
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v0x55ec3381c7f0_0 .net "Y", 0 0, L_0x55ec33823800; 1 drivers
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v0x55ec3381c890_0 .net "notB", 0 0, L_0x55ec33822fb0; 1 drivers
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S_0x55ec3381a5c0 .scope module, "f1" "fulladder" 4 16, 5 1 0, S_0x55ec3381a320;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /INPUT 1 "Carry";
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.port_info 3 /OUTPUT 1 "Sum";
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.port_info 4 /OUTPUT 1 "CarryO";
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L_0x55ec338235c0 .functor OR 1, L_0x55ec33823020, L_0x55ec338232d0, C4<0>, C4<0>;
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v0x55ec3381b3d0_0 .net "A", 0 0, L_0x55ec338238c0; alias, 1 drivers
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v0x55ec3381b490_0 .net "B", 0 0, L_0x55ec33822fb0; alias, 1 drivers
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v0x55ec3381b560_0 .net "Carry", 0 0, L_0x55ec33823a90; alias, 1 drivers
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v0x55ec3381b660_0 .net "CarryO", 0 0, L_0x55ec338235c0; alias, 1 drivers
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v0x55ec3381b700_0 .net "Sum", 0 0, L_0x55ec33823410; alias, 1 drivers
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v0x55ec3381b7f0_0 .net "and1", 0 0, L_0x55ec33823020; 1 drivers
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v0x55ec3381b8c0_0 .net "and2", 0 0, L_0x55ec338232d0; 1 drivers
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v0x55ec3381b990_0 .net "xor1", 0 0, L_0x55ec33823240; 1 drivers
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S_0x55ec3381a7a0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55ec3381a5c0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "Sum";
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.port_info 3 /OUTPUT 1 "Carry";
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L_0x55ec33823020 .functor AND 1, L_0x55ec338238c0, L_0x55ec33822fb0, C4<1>, C4<1>;
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L_0x55ec33823240 .functor XOR 1, L_0x55ec338238c0, L_0x55ec33822fb0, C4<0>, C4<0>;
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v0x55ec3381a9d0_0 .net "A", 0 0, L_0x55ec338238c0; alias, 1 drivers
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v0x55ec3381aab0_0 .net "B", 0 0, L_0x55ec33822fb0; alias, 1 drivers
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v0x55ec3381ab70_0 .net "Carry", 0 0, L_0x55ec33823020; alias, 1 drivers
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v0x55ec3381ac40_0 .net "Sum", 0 0, L_0x55ec33823240; alias, 1 drivers
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S_0x55ec3381adb0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55ec3381a5c0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "Sum";
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.port_info 3 /OUTPUT 1 "Carry";
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L_0x55ec338232d0 .functor AND 1, L_0x55ec33823240, L_0x55ec33823a90, C4<1>, C4<1>;
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L_0x55ec33823410 .functor XOR 1, L_0x55ec33823240, L_0x55ec33823a90, C4<0>, C4<0>;
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v0x55ec3381b020_0 .net "A", 0 0, L_0x55ec33823240; alias, 1 drivers
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v0x55ec3381b0f0_0 .net "B", 0 0, L_0x55ec33823a90; alias, 1 drivers
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v0x55ec3381b190_0 .net "Carry", 0 0, L_0x55ec338232d0; alias, 1 drivers
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v0x55ec3381b260_0 .net "Sum", 0 0, L_0x55ec33823410; alias, 1 drivers
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S_0x55ec3381ba80 .scope module, "m1" "mux2" 4 25, 7 1 0, S_0x55ec3381a320;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A0";
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.port_info 1 /INPUT 1 "A1";
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.port_info 2 /INPUT 1 "S";
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.port_info 3 /OUTPUT 1 "Y";
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L_0x55ec33823670 .functor NOT 1, L_0x55ec33822310, C4<0>, C4<0>, C4<0>;
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L_0x55ec33823700 .functor AND 1, L_0x55ec33823410, L_0x55ec33822310, C4<1>, C4<1>;
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L_0x55ec33823790 .functor AND 1, L_0x55ec33823670, L_0x55ec338238c0, C4<1>, C4<1>;
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L_0x55ec33823800 .functor OR 1, L_0x55ec33823700, L_0x55ec33823790, C4<0>, C4<0>;
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v0x55ec3381bcd0_0 .net "A0", 0 0, L_0x55ec338238c0; alias, 1 drivers
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v0x55ec3381bdc0_0 .net "A1", 0 0, L_0x55ec33823410; alias, 1 drivers
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v0x55ec3381bed0_0 .net "S", 0 0, L_0x55ec33822310; alias, 1 drivers
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v0x55ec3381bfc0_0 .net "Y", 0 0, L_0x55ec33823800; alias, 1 drivers
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v0x55ec3381c060_0 .net "and1", 0 0, L_0x55ec33823700; 1 drivers
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v0x55ec3381c150_0 .net "and2", 0 0, L_0x55ec33823790; 1 drivers
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v0x55ec3381c210_0 .net "notS", 0 0, L_0x55ec33823670; 1 drivers
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S_0x55ec3381c9e0 .scope module, "PU3" "PU" 3 36, 4 1 0, S_0x55ec337fa3a0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /INPUT 1 "Cin";
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.port_info 3 /INPUT 1 "S";
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.port_info 4 /OUTPUT 1 "Y";
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.port_info 5 /OUTPUT 1 "COut";
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L_0x55ec33823b30 .functor NOT 1, L_0x55ec33824530, C4<0>, C4<0>, C4<0>;
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v0x55ec3381ea80_0 .net "A", 0 0, L_0x55ec338243b0; 1 drivers
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v0x55ec3381eb40_0 .net "B", 0 0, L_0x55ec33824530; 1 drivers
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v0x55ec3381ec00_0 .net "COut", 0 0, L_0x55ec338240b0; 1 drivers
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v0x55ec3381eca0_0 .net "Cin", 0 0, L_0x55ec33824660; 1 drivers
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v0x55ec3381ed90_0 .net "S", 0 0, L_0x55ec338223e0; alias, 1 drivers
|
||||
v0x55ec3381ee80_0 .net "Sum", 0 0, L_0x55ec33823f00; 1 drivers
|
||||
v0x55ec3381ef20_0 .net "Y", 0 0, L_0x55ec338242f0; 1 drivers
|
||||
v0x55ec3381efc0_0 .net "notB", 0 0, L_0x55ec33823b30; 1 drivers
|
||||
S_0x55ec3381cc60 .scope module, "f1" "fulladder" 4 16, 5 1 0, S_0x55ec3381c9e0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x55ec338240b0 .functor OR 1, L_0x55ec33823ba0, L_0x55ec33823dc0, C4<0>, C4<0>;
|
||||
v0x55ec3381db30_0 .net "A", 0 0, L_0x55ec338243b0; alias, 1 drivers
|
||||
v0x55ec3381dbf0_0 .net "B", 0 0, L_0x55ec33823b30; alias, 1 drivers
|
||||
v0x55ec3381dcc0_0 .net "Carry", 0 0, L_0x55ec33824660; alias, 1 drivers
|
||||
v0x55ec3381ddc0_0 .net "CarryO", 0 0, L_0x55ec338240b0; alias, 1 drivers
|
||||
v0x55ec3381de60_0 .net "Sum", 0 0, L_0x55ec33823f00; alias, 1 drivers
|
||||
v0x55ec3381df50_0 .net "and1", 0 0, L_0x55ec33823ba0; 1 drivers
|
||||
v0x55ec3381e020_0 .net "and2", 0 0, L_0x55ec33823dc0; 1 drivers
|
||||
v0x55ec3381e0f0_0 .net "xor1", 0 0, L_0x55ec33823d30; 1 drivers
|
||||
S_0x55ec3381cec0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55ec3381cc60;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55ec33823ba0 .functor AND 1, L_0x55ec338243b0, L_0x55ec33823b30, C4<1>, C4<1>;
|
||||
L_0x55ec33823d30 .functor XOR 1, L_0x55ec338243b0, L_0x55ec33823b30, C4<0>, C4<0>;
|
||||
v0x55ec3381d130_0 .net "A", 0 0, L_0x55ec338243b0; alias, 1 drivers
|
||||
v0x55ec3381d210_0 .net "B", 0 0, L_0x55ec33823b30; alias, 1 drivers
|
||||
v0x55ec3381d2d0_0 .net "Carry", 0 0, L_0x55ec33823ba0; alias, 1 drivers
|
||||
v0x55ec3381d3a0_0 .net "Sum", 0 0, L_0x55ec33823d30; alias, 1 drivers
|
||||
S_0x55ec3381d510 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55ec3381cc60;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55ec33823dc0 .functor AND 1, L_0x55ec33823d30, L_0x55ec33824660, C4<1>, C4<1>;
|
||||
L_0x55ec33823f00 .functor XOR 1, L_0x55ec33823d30, L_0x55ec33824660, C4<0>, C4<0>;
|
||||
v0x55ec3381d780_0 .net "A", 0 0, L_0x55ec33823d30; alias, 1 drivers
|
||||
v0x55ec3381d850_0 .net "B", 0 0, L_0x55ec33824660; alias, 1 drivers
|
||||
v0x55ec3381d8f0_0 .net "Carry", 0 0, L_0x55ec33823dc0; alias, 1 drivers
|
||||
v0x55ec3381d9c0_0 .net "Sum", 0 0, L_0x55ec33823f00; alias, 1 drivers
|
||||
S_0x55ec3381e1e0 .scope module, "m1" "mux2" 4 25, 7 1 0, S_0x55ec3381c9e0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A0";
|
||||
.port_info 1 /INPUT 1 "A1";
|
||||
.port_info 2 /INPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "Y";
|
||||
L_0x55ec33824160 .functor NOT 1, L_0x55ec338223e0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55ec338241f0 .functor AND 1, L_0x55ec33823f00, L_0x55ec338223e0, C4<1>, C4<1>;
|
||||
L_0x55ec33824280 .functor AND 1, L_0x55ec33824160, L_0x55ec338243b0, C4<1>, C4<1>;
|
||||
L_0x55ec338242f0 .functor OR 1, L_0x55ec338241f0, L_0x55ec33824280, C4<0>, C4<0>;
|
||||
v0x55ec3381e430_0 .net "A0", 0 0, L_0x55ec338243b0; alias, 1 drivers
|
||||
v0x55ec3381e520_0 .net "A1", 0 0, L_0x55ec33823f00; alias, 1 drivers
|
||||
v0x55ec3381e630_0 .net "S", 0 0, L_0x55ec338223e0; alias, 1 drivers
|
||||
v0x55ec3381e6d0_0 .net "Y", 0 0, L_0x55ec338242f0; alias, 1 drivers
|
||||
v0x55ec3381e770_0 .net "and1", 0 0, L_0x55ec338241f0; 1 drivers
|
||||
v0x55ec3381e880_0 .net "and2", 0 0, L_0x55ec33824280; 1 drivers
|
||||
v0x55ec3381e940_0 .net "notS", 0 0, L_0x55ec33824160; 1 drivers
|
||||
S_0x55ec3381f0f0 .scope module, "PU4" "PU" 3 45, 4 1 0, S_0x55ec337fa3a0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Cin";
|
||||
.port_info 3 /INPUT 1 "S";
|
||||
.port_info 4 /OUTPUT 1 "Y";
|
||||
.port_info 5 /OUTPUT 1 "COut";
|
||||
L_0x55ec338247f0 .functor NOT 1, L_0x55ec33825100, C4<0>, C4<0>, C4<0>;
|
||||
v0x55ec33821210_0 .net "A", 0 0, L_0x55ec33825060; 1 drivers
|
||||
v0x55ec338212d0_0 .net "B", 0 0, L_0x55ec33825100; 1 drivers
|
||||
v0x55ec33821390_0 .net "COut", 0 0, L_0x55ec33824db0; 1 drivers
|
||||
v0x55ec33821430_0 .net "Cin", 0 0, L_0x55ec33825210; 1 drivers
|
||||
v0x55ec33821520_0 .net "S", 0 0, L_0x55ec338223e0; alias, 1 drivers
|
||||
v0x55ec33821610_0 .net "Sum", 0 0, L_0x55ec33824c00; 1 drivers
|
||||
v0x55ec338216b0_0 .net "Y", 0 0, L_0x55ec33824ff0; 1 drivers
|
||||
v0x55ec33821750_0 .net "notB", 0 0, L_0x55ec338247f0; 1 drivers
|
||||
S_0x55ec3381f370 .scope module, "f1" "fulladder" 4 16, 5 1 0, S_0x55ec3381f0f0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x55ec33824db0 .functor OR 1, L_0x55ec33824860, L_0x55ec33824ac0, C4<0>, C4<0>;
|
||||
v0x55ec33820290_0 .net "A", 0 0, L_0x55ec33825060; alias, 1 drivers
|
||||
v0x55ec33820350_0 .net "B", 0 0, L_0x55ec338247f0; alias, 1 drivers
|
||||
v0x55ec33820420_0 .net "Carry", 0 0, L_0x55ec33825210; alias, 1 drivers
|
||||
v0x55ec33820520_0 .net "CarryO", 0 0, L_0x55ec33824db0; alias, 1 drivers
|
||||
v0x55ec338205c0_0 .net "Sum", 0 0, L_0x55ec33824c00; alias, 1 drivers
|
||||
v0x55ec338206b0_0 .net "and1", 0 0, L_0x55ec33824860; 1 drivers
|
||||
v0x55ec33820780_0 .net "and2", 0 0, L_0x55ec33824ac0; 1 drivers
|
||||
v0x55ec33820850_0 .net "xor1", 0 0, L_0x55ec33824a30; 1 drivers
|
||||
S_0x55ec3381f5f0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55ec3381f370;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55ec33824860 .functor AND 1, L_0x55ec33825060, L_0x55ec338247f0, C4<1>, C4<1>;
|
||||
L_0x55ec33824a30 .functor XOR 1, L_0x55ec33825060, L_0x55ec338247f0, C4<0>, C4<0>;
|
||||
v0x55ec3381f890_0 .net "A", 0 0, L_0x55ec33825060; alias, 1 drivers
|
||||
v0x55ec3381f970_0 .net "B", 0 0, L_0x55ec338247f0; alias, 1 drivers
|
||||
v0x55ec3381fa30_0 .net "Carry", 0 0, L_0x55ec33824860; alias, 1 drivers
|
||||
v0x55ec3381fb00_0 .net "Sum", 0 0, L_0x55ec33824a30; alias, 1 drivers
|
||||
S_0x55ec3381fc70 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55ec3381f370;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55ec33824ac0 .functor AND 1, L_0x55ec33824a30, L_0x55ec33825210, C4<1>, C4<1>;
|
||||
L_0x55ec33824c00 .functor XOR 1, L_0x55ec33824a30, L_0x55ec33825210, C4<0>, C4<0>;
|
||||
v0x55ec3381fee0_0 .net "A", 0 0, L_0x55ec33824a30; alias, 1 drivers
|
||||
v0x55ec3381ffb0_0 .net "B", 0 0, L_0x55ec33825210; alias, 1 drivers
|
||||
v0x55ec33820050_0 .net "Carry", 0 0, L_0x55ec33824ac0; alias, 1 drivers
|
||||
v0x55ec33820120_0 .net "Sum", 0 0, L_0x55ec33824c00; alias, 1 drivers
|
||||
S_0x55ec33820940 .scope module, "m1" "mux2" 4 25, 7 1 0, S_0x55ec3381f0f0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A0";
|
||||
.port_info 1 /INPUT 1 "A1";
|
||||
.port_info 2 /INPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "Y";
|
||||
L_0x55ec33824e60 .functor NOT 1, L_0x55ec338223e0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55ec33824ef0 .functor AND 1, L_0x55ec33824c00, L_0x55ec338223e0, C4<1>, C4<1>;
|
||||
L_0x55ec33824f80 .functor AND 1, L_0x55ec33824e60, L_0x55ec33825060, C4<1>, C4<1>;
|
||||
L_0x55ec33824ff0 .functor OR 1, L_0x55ec33824ef0, L_0x55ec33824f80, C4<0>, C4<0>;
|
||||
v0x55ec33820b90_0 .net "A0", 0 0, L_0x55ec33825060; alias, 1 drivers
|
||||
v0x55ec33820c80_0 .net "A1", 0 0, L_0x55ec33824c00; alias, 1 drivers
|
||||
v0x55ec33820d90_0 .net "S", 0 0, L_0x55ec338223e0; alias, 1 drivers
|
||||
v0x55ec33820e80_0 .net "Y", 0 0, L_0x55ec33824ff0; alias, 1 drivers
|
||||
v0x55ec33820f20_0 .net "and1", 0 0, L_0x55ec33824ef0; 1 drivers
|
||||
v0x55ec33821010_0 .net "and2", 0 0, L_0x55ec33824f80; 1 drivers
|
||||
v0x55ec338210d0_0 .net "notS", 0 0, L_0x55ec33824e60; 1 drivers
|
||||
.scope S_0x55ec337fbbf0;
|
||||
T_0 ;
|
||||
%vpi_call 2 21 "$monitor", "Time=%0t | Dividend=%b | Divisor=%b | Quotient=%b | Remainder=%b", $time, v0x55ec33821ff0_0, v0x55ec338220d0_0, v0x55ec33822170_0, v0x55ec33822240_0 {0 0 0};
|
||||
%vpi_call 2 23 "$dumpfile", "divider4.vcd" {0 0 0};
|
||||
%vpi_call 2 24 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 8, 0, 4;
|
||||
%store/vec4 v0x55ec33821ff0_0, 0, 4;
|
||||
%pushi/vec4 2, 0, 2;
|
||||
%store/vec4 v0x55ec338220d0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 15, 0, 4;
|
||||
%store/vec4 v0x55ec33821ff0_0, 0, 4;
|
||||
%pushi/vec4 3, 0, 2;
|
||||
%store/vec4 v0x55ec338220d0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 7, 0, 4;
|
||||
%store/vec4 v0x55ec33821ff0_0, 0, 4;
|
||||
%pushi/vec4 2, 0, 2;
|
||||
%store/vec4 v0x55ec338220d0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 9, 0, 4;
|
||||
%store/vec4 v0x55ec33821ff0_0, 0, 4;
|
||||
%pushi/vec4 3, 0, 2;
|
||||
%store/vec4 v0x55ec338220d0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 6, 0, 4;
|
||||
%store/vec4 v0x55ec33821ff0_0, 0, 4;
|
||||
%pushi/vec4 1, 0, 2;
|
||||
%store/vec4 v0x55ec338220d0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 10, 0, 4;
|
||||
%store/vec4 v0x55ec33821ff0_0, 0, 4;
|
||||
%pushi/vec4 0, 0, 2;
|
||||
%store/vec4 v0x55ec338220d0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 57 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 8;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"divider4TB.v";
|
||||
"divider4.v";
|
||||
"PU.v";
|
||||
"fulladder.v";
|
||||
"halfadder.v";
|
||||
"mux2.v";
|
||||
@@ -1,58 +0,0 @@
|
||||
module divider4 (
|
||||
input [3:0] Dividend, // 4-bit dividend
|
||||
input [1:0] Divisor, // 2-bit divisor
|
||||
output [3:0] Quotient, // 4-bit quotient
|
||||
output [2:0] Remainder // 3-bit remainder
|
||||
);
|
||||
|
||||
wire [3:0] Carry; // Carry wires between PUs
|
||||
wire [3:0] Y; // Intermediate PU outputs
|
||||
wire S0, S1; // Select signals based on division logic
|
||||
|
||||
// Calculate select signals based on carry outputs
|
||||
assign S0 = Carry[3]; // First select signal
|
||||
assign S1 = Carry[2]; // Second select signal
|
||||
|
||||
// Row 1
|
||||
PU PU1 (
|
||||
.A(Dividend[3]),
|
||||
.B(Divisor[1]),
|
||||
.Cin(1'b0), // Initial carry input is 0
|
||||
.S(S0),
|
||||
.Y(Y[3]),
|
||||
.COut(Carry[3])
|
||||
);
|
||||
|
||||
PU PU2 (
|
||||
.A(Dividend[2]),
|
||||
.B(Divisor[1]),
|
||||
.Cin(Carry[3]),
|
||||
.S(S0),
|
||||
.Y(Y[2]),
|
||||
.COut(Carry[2])
|
||||
);
|
||||
|
||||
// Row 2
|
||||
PU PU3 (
|
||||
.A(Dividend[1]),
|
||||
.B(Divisor[0]),
|
||||
.Cin(Carry[2]),
|
||||
.S(S1),
|
||||
.Y(Y[1]),
|
||||
.COut(Carry[1])
|
||||
);
|
||||
|
||||
PU PU4 (
|
||||
.A(Dividend[0]),
|
||||
.B(Divisor[0]),
|
||||
.Cin(Carry[1]),
|
||||
.S(S1),
|
||||
.Y(Y[0]),
|
||||
.COut(Carry[0])
|
||||
);
|
||||
|
||||
// Assign outputs
|
||||
assign Quotient = Y; // Output of the PUs is the quotient
|
||||
assign Remainder = Carry; // Final carry values are the remainder
|
||||
|
||||
endmodule
|
||||
@@ -1,457 +0,0 @@
|
||||
$date
|
||||
Fri Dec 27 21:47:45 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module divider4TB $end
|
||||
$var wire 3 ! Remainder [2:0] $end
|
||||
$var wire 4 " Quotient [3:0] $end
|
||||
$var reg 4 # Dividend [3:0] $end
|
||||
$var reg 2 $ Divisor [1:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 4 % Dividend [3:0] $end
|
||||
$var wire 2 & Divisor [1:0] $end
|
||||
$var wire 4 ' Quotient [3:0] $end
|
||||
$var wire 4 ( Y [3:0] $end
|
||||
$var wire 1 ) S1 $end
|
||||
$var wire 1 * S0 $end
|
||||
$var wire 3 + Remainder [2:0] $end
|
||||
$var wire 4 , Carry [3:0] $end
|
||||
$scope module PU1 $end
|
||||
$var wire 1 - A $end
|
||||
$var wire 1 . B $end
|
||||
$var wire 1 / Cin $end
|
||||
$var wire 1 * S $end
|
||||
$var wire 1 0 notB $end
|
||||
$var wire 1 1 Y $end
|
||||
$var wire 1 2 Sum $end
|
||||
$var wire 1 3 COut $end
|
||||
$scope module f1 $end
|
||||
$var wire 1 - A $end
|
||||
$var wire 1 0 B $end
|
||||
$var wire 1 / Carry $end
|
||||
$var wire 1 3 CarryO $end
|
||||
$var wire 1 4 xor1 $end
|
||||
$var wire 1 5 and2 $end
|
||||
$var wire 1 6 and1 $end
|
||||
$var wire 1 2 Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 - A $end
|
||||
$var wire 1 0 B $end
|
||||
$var wire 1 6 Carry $end
|
||||
$var wire 1 4 Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 4 A $end
|
||||
$var wire 1 / B $end
|
||||
$var wire 1 5 Carry $end
|
||||
$var wire 1 2 Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module m1 $end
|
||||
$var wire 1 - A0 $end
|
||||
$var wire 1 2 A1 $end
|
||||
$var wire 1 * S $end
|
||||
$var wire 1 1 Y $end
|
||||
$var wire 1 7 and1 $end
|
||||
$var wire 1 8 and2 $end
|
||||
$var wire 1 9 notS $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module PU2 $end
|
||||
$var wire 1 : A $end
|
||||
$var wire 1 ; B $end
|
||||
$var wire 1 < Cin $end
|
||||
$var wire 1 * S $end
|
||||
$var wire 1 = notB $end
|
||||
$var wire 1 > Y $end
|
||||
$var wire 1 ? Sum $end
|
||||
$var wire 1 @ COut $end
|
||||
$scope module f1 $end
|
||||
$var wire 1 : A $end
|
||||
$var wire 1 = B $end
|
||||
$var wire 1 < Carry $end
|
||||
$var wire 1 @ CarryO $end
|
||||
$var wire 1 A xor1 $end
|
||||
$var wire 1 B and2 $end
|
||||
$var wire 1 C and1 $end
|
||||
$var wire 1 ? Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 : A $end
|
||||
$var wire 1 = B $end
|
||||
$var wire 1 C Carry $end
|
||||
$var wire 1 A Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 A A $end
|
||||
$var wire 1 < B $end
|
||||
$var wire 1 B Carry $end
|
||||
$var wire 1 ? Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module m1 $end
|
||||
$var wire 1 : A0 $end
|
||||
$var wire 1 ? A1 $end
|
||||
$var wire 1 * S $end
|
||||
$var wire 1 > Y $end
|
||||
$var wire 1 D and1 $end
|
||||
$var wire 1 E and2 $end
|
||||
$var wire 1 F notS $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module PU3 $end
|
||||
$var wire 1 G A $end
|
||||
$var wire 1 H B $end
|
||||
$var wire 1 I Cin $end
|
||||
$var wire 1 ) S $end
|
||||
$var wire 1 J notB $end
|
||||
$var wire 1 K Y $end
|
||||
$var wire 1 L Sum $end
|
||||
$var wire 1 M COut $end
|
||||
$scope module f1 $end
|
||||
$var wire 1 G A $end
|
||||
$var wire 1 J B $end
|
||||
$var wire 1 I Carry $end
|
||||
$var wire 1 M CarryO $end
|
||||
$var wire 1 N xor1 $end
|
||||
$var wire 1 O and2 $end
|
||||
$var wire 1 P and1 $end
|
||||
$var wire 1 L Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 G A $end
|
||||
$var wire 1 J B $end
|
||||
$var wire 1 P Carry $end
|
||||
$var wire 1 N Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 N A $end
|
||||
$var wire 1 I B $end
|
||||
$var wire 1 O Carry $end
|
||||
$var wire 1 L Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module m1 $end
|
||||
$var wire 1 G A0 $end
|
||||
$var wire 1 L A1 $end
|
||||
$var wire 1 ) S $end
|
||||
$var wire 1 K Y $end
|
||||
$var wire 1 Q and1 $end
|
||||
$var wire 1 R and2 $end
|
||||
$var wire 1 S notS $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module PU4 $end
|
||||
$var wire 1 T A $end
|
||||
$var wire 1 U B $end
|
||||
$var wire 1 V Cin $end
|
||||
$var wire 1 ) S $end
|
||||
$var wire 1 W notB $end
|
||||
$var wire 1 X Y $end
|
||||
$var wire 1 Y Sum $end
|
||||
$var wire 1 Z COut $end
|
||||
$scope module f1 $end
|
||||
$var wire 1 T A $end
|
||||
$var wire 1 W B $end
|
||||
$var wire 1 V Carry $end
|
||||
$var wire 1 Z CarryO $end
|
||||
$var wire 1 [ xor1 $end
|
||||
$var wire 1 \ and2 $end
|
||||
$var wire 1 ] and1 $end
|
||||
$var wire 1 Y Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 T A $end
|
||||
$var wire 1 W B $end
|
||||
$var wire 1 ] Carry $end
|
||||
$var wire 1 [ Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 [ A $end
|
||||
$var wire 1 V B $end
|
||||
$var wire 1 \ Carry $end
|
||||
$var wire 1 Y Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module m1 $end
|
||||
$var wire 1 T A0 $end
|
||||
$var wire 1 Y A1 $end
|
||||
$var wire 1 ) S $end
|
||||
$var wire 1 X Y $end
|
||||
$var wire 1 ^ and1 $end
|
||||
$var wire 1 _ and2 $end
|
||||
$var wire 1 ` notS $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
1`
|
||||
0_
|
||||
0^
|
||||
0]
|
||||
0\
|
||||
1[
|
||||
0Z
|
||||
1Y
|
||||
0X
|
||||
1W
|
||||
0V
|
||||
0U
|
||||
0T
|
||||
1S
|
||||
0R
|
||||
0Q
|
||||
0P
|
||||
0O
|
||||
1N
|
||||
0M
|
||||
1L
|
||||
0K
|
||||
1J
|
||||
0I
|
||||
0H
|
||||
0G
|
||||
1F
|
||||
0E
|
||||
0D
|
||||
0C
|
||||
0B
|
||||
0A
|
||||
0@
|
||||
0?
|
||||
0>
|
||||
0=
|
||||
0<
|
||||
1;
|
||||
0:
|
||||
19
|
||||
18
|
||||
07
|
||||
06
|
||||
05
|
||||
14
|
||||
03
|
||||
12
|
||||
11
|
||||
00
|
||||
0/
|
||||
1.
|
||||
1-
|
||||
b0 ,
|
||||
b0 +
|
||||
0*
|
||||
0)
|
||||
b1000 (
|
||||
b1000 '
|
||||
b10 &
|
||||
b1000 %
|
||||
b10 $
|
||||
b1000 #
|
||||
b1000 "
|
||||
b0 !
|
||||
$end
|
||||
#10
|
||||
0\
|
||||
0V
|
||||
b0 !
|
||||
b0 +
|
||||
1?
|
||||
1>
|
||||
0M
|
||||
1L
|
||||
1K
|
||||
b0 ,
|
||||
0Z
|
||||
1Y
|
||||
b1111 "
|
||||
b1111 '
|
||||
b1111 (
|
||||
1X
|
||||
0J
|
||||
0W
|
||||
1A
|
||||
1E
|
||||
0P
|
||||
1N
|
||||
1R
|
||||
0]
|
||||
1[
|
||||
1_
|
||||
1H
|
||||
1U
|
||||
1:
|
||||
1G
|
||||
1T
|
||||
b11 $
|
||||
b11 &
|
||||
b1111 #
|
||||
b1111 %
|
||||
#20
|
||||
1V
|
||||
b11 !
|
||||
b11 +
|
||||
1M
|
||||
0L
|
||||
b11 ,
|
||||
1Z
|
||||
1Y
|
||||
1P
|
||||
0N
|
||||
1]
|
||||
0[
|
||||
02
|
||||
b111 "
|
||||
b111 '
|
||||
b111 (
|
||||
01
|
||||
1J
|
||||
1W
|
||||
04
|
||||
08
|
||||
0H
|
||||
0U
|
||||
0-
|
||||
b10 $
|
||||
b10 &
|
||||
b111 #
|
||||
b111 %
|
||||
#30
|
||||
0Z
|
||||
b0 !
|
||||
b0 +
|
||||
0V
|
||||
0]
|
||||
1[
|
||||
12
|
||||
11
|
||||
0?
|
||||
0>
|
||||
b0 ,
|
||||
0M
|
||||
0L
|
||||
b1001 "
|
||||
b1001 '
|
||||
b1001 (
|
||||
0K
|
||||
0J
|
||||
0W
|
||||
14
|
||||
18
|
||||
0A
|
||||
0E
|
||||
0P
|
||||
0N
|
||||
0R
|
||||
1H
|
||||
1U
|
||||
1-
|
||||
0:
|
||||
0G
|
||||
b11 $
|
||||
b11 &
|
||||
b1001 #
|
||||
b1001 %
|
||||
#40
|
||||
1^
|
||||
1V
|
||||
1M
|
||||
1O
|
||||
0S
|
||||
0Q
|
||||
0`
|
||||
b110 !
|
||||
b110 +
|
||||
1I
|
||||
1)
|
||||
b110 ,
|
||||
1@
|
||||
1C
|
||||
12
|
||||
01
|
||||
0?
|
||||
1>
|
||||
0L
|
||||
0K
|
||||
1Y
|
||||
b101 "
|
||||
b101 '
|
||||
b101 (
|
||||
1X
|
||||
10
|
||||
1=
|
||||
14
|
||||
08
|
||||
0A
|
||||
1E
|
||||
1N
|
||||
0R
|
||||
0[
|
||||
0_
|
||||
0.
|
||||
0;
|
||||
0-
|
||||
1:
|
||||
1G
|
||||
0T
|
||||
b1 $
|
||||
b1 &
|
||||
b110 #
|
||||
b110 %
|
||||
#50
|
||||
1Q
|
||||
1L
|
||||
1K
|
||||
0R
|
||||
0X
|
||||
1Z
|
||||
1B
|
||||
09
|
||||
0F
|
||||
0D
|
||||
0S
|
||||
0`
|
||||
0^
|
||||
0O
|
||||
1\
|
||||
0Y
|
||||
1<
|
||||
1*
|
||||
b111 !
|
||||
b111 +
|
||||
1I
|
||||
1)
|
||||
1P
|
||||
0N
|
||||
1[
|
||||
13
|
||||
02
|
||||
01
|
||||
b1111 ,
|
||||
1@
|
||||
0?
|
||||
b10 "
|
||||
b10 '
|
||||
b10 (
|
||||
0>
|
||||
1J
|
||||
1W
|
||||
16
|
||||
04
|
||||
08
|
||||
0C
|
||||
1A
|
||||
0E
|
||||
0H
|
||||
0U
|
||||
1-
|
||||
0:
|
||||
b0 $
|
||||
b0 &
|
||||
b1010 #
|
||||
b1010 %
|
||||
#60
|
||||
@@ -1,60 +0,0 @@
|
||||
module divider4TB;
|
||||
|
||||
// Inputs
|
||||
reg [3:0] Dividend;
|
||||
reg [1:0] Divisor;
|
||||
|
||||
// Outputs
|
||||
wire [3:0] Quotient;
|
||||
wire [2:0] Remainder;
|
||||
|
||||
// Instantiate the Unit Under Test (UUT)
|
||||
divider4 uut (
|
||||
.Dividend(Dividend),
|
||||
.Divisor(Divisor),
|
||||
.Quotient(Quotient),
|
||||
.Remainder(Remainder)
|
||||
);
|
||||
|
||||
initial begin
|
||||
// Monitor output changes
|
||||
$monitor("Time=%0t | Dividend=%b | Divisor=%b | Quotient=%b | Remainder=%b",
|
||||
$time, Dividend, Divisor, Quotient, Remainder);
|
||||
$dumpfile("divider4.vcd");
|
||||
$dumpvars;
|
||||
|
||||
// Test Case 1: 8 / 2
|
||||
Dividend = 4'b1000; // 8 in binary
|
||||
Divisor = 2'b10; // 2 in binary
|
||||
#10;
|
||||
|
||||
// Test Case 2: 15 / 3
|
||||
Dividend = 4'b1111; // 15 in binary
|
||||
Divisor = 2'b11; // 3 in binary
|
||||
#10;
|
||||
|
||||
// Test Case 3: 7 / 2
|
||||
Dividend = 4'b0111; // 7 in binary
|
||||
Divisor = 2'b10; // 2 in binary
|
||||
#10;
|
||||
|
||||
// Test Case 4: 9 / 3
|
||||
Dividend = 4'b1001; // 9 in binary
|
||||
Divisor = 2'b11; // 3 in binary
|
||||
#10;
|
||||
|
||||
// Test Case 5: 6 / 1
|
||||
Dividend = 4'b0110; // 6 in binary
|
||||
Divisor = 2'b01; // 1 in binary
|
||||
#10;
|
||||
|
||||
// Test Case 6: Division by 0 (should be undefined behavior)
|
||||
Dividend = 4'b1010; // 10 in binary
|
||||
Divisor = 2'b00; // Division by zero
|
||||
#10;
|
||||
|
||||
// End simulation
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,16 +0,0 @@
|
||||
module mux2 (
|
||||
input A0, A1,
|
||||
input S,
|
||||
output Y
|
||||
);
|
||||
|
||||
wire notS, and1, and2;
|
||||
|
||||
not n1 (notS, S);
|
||||
|
||||
and an1 (and1, A1, S);
|
||||
and an2 (and2, notS, A0);
|
||||
|
||||
or o1 (Y, and1, and2);
|
||||
|
||||
endmodule
|
||||
@@ -1,300 +0,0 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x55b89815f210 .scope module, "selectorTB" "selectorTB" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x55b898185a70_0 .var "A", 3 0;
|
||||
v0x55b898185b50_0 .var "B", 3 0;
|
||||
v0x55b898185c20_0 .var "Y", 7 0;
|
||||
v0x55b898185cf0_0 .var "opCodeA", 2 0;
|
||||
v0x55b898185de0_0 .net "s0", 7 0, L_0x55b89818e810; 1 drivers
|
||||
v0x55b898185e80_0 .var "select", 3 0;
|
||||
S_0x55b898152b60 .scope module, "uut" "selector" 2 8, 3 1 0, S_0x55b89815f210;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 4 "select";
|
||||
.port_info 1 /INPUT 8 "Y";
|
||||
.port_info 2 /INPUT 4 "A";
|
||||
.port_info 3 /INPUT 4 "B";
|
||||
.port_info 4 /INPUT 3 "opCodeA";
|
||||
.port_info 5 /OUTPUT 8 "s0";
|
||||
L_0x55b898185f50 .functor AND 1, L_0x55b898186050, L_0x55b898186190, C4<1>, C4<1>;
|
||||
L_0x55b8981862d0 .functor AND 1, L_0x55b898186340, L_0x55b898186430, C4<1>, C4<1>;
|
||||
L_0x55b898186550 .functor AND 1, L_0x55b8981865c0, L_0x55b8981866b0, C4<1>, C4<1>;
|
||||
L_0x55b8981868d0 .functor AND 1, L_0x55b8981869c0, L_0x55b898186b00, C4<1>, C4<1>;
|
||||
L_0x55b898186bf0 .functor AND 1, L_0x55b898186c60, L_0x55b898186db0, C4<1>, C4<1>;
|
||||
L_0x55b898186ea0 .functor AND 1, L_0x55b898186f50, L_0x55b8981870b0, C4<1>, C4<1>;
|
||||
L_0x55b8981871a0 .functor AND 1, L_0x55b898187210, L_0x55b898187380, C4<1>, C4<1>;
|
||||
L_0x55b898187040 .functor AND 1, L_0x55b8981876e0, L_0x55b8981877d0, C4<1>, C4<1>;
|
||||
L_0x55b898187960 .functor AND 1, L_0x55b8981879d0, L_0x55b898187ac0, C4<1>, C4<1>;
|
||||
L_0x55b898187c60 .functor AND 1, L_0x55b8981878c0, L_0x55b898187d60, C4<1>, C4<1>;
|
||||
L_0x55b898187f60 .functor AND 1, L_0x55b898187fd0, L_0x55b8981880c0, C4<1>, C4<1>;
|
||||
L_0x55b898188280 .functor AND 1, L_0x55b898188390, L_0x55b898188480, C4<1>, C4<1>;
|
||||
L_0x55b898188650 .functor AND 1, L_0x55b8981886f0, L_0x55b898188790, C4<1>, C4<1>;
|
||||
L_0x55b898188970 .functor AND 1, L_0x55b898188a90, L_0x55b898188b80, C4<1>, C4<1>;
|
||||
L_0x55b898188320 .functor AND 1, L_0x55b898188da0, L_0x55b898188e90, C4<1>, C4<1>;
|
||||
L_0x55b8981893b0 .functor AND 1, L_0x55b898189500, L_0x55b898189710, C4<1>, C4<1>;
|
||||
L_0x55b898189800 .functor AND 1, L_0x55b898189870, L_0x55b898189a90, C4<1>, C4<1>;
|
||||
L_0x55b898189bd0 .functor AND 1, L_0x55b898189ce0, L_0x55b898189f10, C4<1>, C4<1>;
|
||||
L_0x55b89818a290 .functor AND 1, L_0x55b89818a350, L_0x55b89818a440, C4<1>, C4<1>;
|
||||
L_0x55b89818a690 .functor OR 1, L_0x55b898189c40, L_0x55b89818a800, C4<0>, C4<0>;
|
||||
L_0x55b89818aab0 .functor OR 1, L_0x55b89818ab20, L_0x55b89818ac10, C4<0>, C4<0>;
|
||||
L_0x55b89818ae80 .functor OR 1, L_0x55b89818afb0, L_0x55b89818b0a0, C4<0>, C4<0>;
|
||||
L_0x55b89818b4a0 .functor OR 1, L_0x55b89818b560, L_0x55b89818b7f0, C4<0>, C4<0>;
|
||||
L_0x55b89818b8e0 .functor OR 1, L_0x55b89818ba20, L_0x55b89818bd10, C4<0>, C4<0>;
|
||||
L_0x55b89818be50 .functor OR 1, L_0x55b89818bec0, L_0x55b89818c170, C4<0>, C4<0>;
|
||||
L_0x55b89818c260 .functor OR 1, L_0x55b89818c3b0, L_0x55b89818c700, C4<0>, C4<0>;
|
||||
L_0x7f2e051b7018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55b89818cb50 .functor OR 1, L_0x55b89818cc10, L_0x7f2e051b7018, C4<0>, C4<0>;
|
||||
L_0x55b89818cd50 .functor OR 1, L_0x55b89818ceb0, L_0x55b89818d1e0, C4<0>, C4<0>;
|
||||
L_0x55b89818d320 .functor OR 1, L_0x55b89818d390, L_0x55b89818d680, C4<0>, C4<0>;
|
||||
L_0x55b89818d770 .functor OR 1, L_0x55b89818d8e0, L_0x55b89818dc70, C4<0>, C4<0>;
|
||||
L_0x55b89818dda0 .functor OR 1, L_0x55b89818de10, L_0x55b89818e0d0, C4<0>, C4<0>;
|
||||
v0x55b89815cd40_0 .net "A", 3 0, v0x55b898185a70_0; 1 drivers
|
||||
v0x55b89815c0d0_0 .net "B", 3 0, v0x55b898185b50_0; 1 drivers
|
||||
o0x7f2e0544e078 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
|
||||
v0x55b89815b460_0 .net "Y", 7 0, o0x7f2e0544e078; 0 drivers
|
||||
v0x55b898142380_0 .net *"_ivl_0", 0 0, L_0x55b898185f50; 1 drivers
|
||||
v0x55b89817f760_0 .net *"_ivl_102", 0 0, L_0x55b898189870; 1 drivers
|
||||
v0x55b89817f890_0 .net *"_ivl_104", 0 0, L_0x55b898189a90; 1 drivers
|
||||
v0x55b89817f970_0 .net *"_ivl_105", 0 0, L_0x55b898189bd0; 1 drivers
|
||||
v0x55b89817fa50_0 .net *"_ivl_108", 0 0, L_0x55b898189ce0; 1 drivers
|
||||
v0x55b89817fb30_0 .net *"_ivl_11", 0 0, L_0x55b898186430; 1 drivers
|
||||
v0x55b89817fc10_0 .net *"_ivl_110", 0 0, L_0x55b898189f10; 1 drivers
|
||||
v0x55b89817fcf0_0 .net *"_ivl_111", 0 0, L_0x55b89818a290; 1 drivers
|
||||
v0x55b89817fdd0_0 .net *"_ivl_115", 0 0, L_0x55b89818a350; 1 drivers
|
||||
v0x55b89817feb0_0 .net *"_ivl_117", 0 0, L_0x55b89818a440; 1 drivers
|
||||
v0x55b89817ff90_0 .net *"_ivl_118", 0 0, L_0x55b89818a690; 1 drivers
|
||||
v0x55b898180070_0 .net *"_ivl_12", 0 0, L_0x55b898186550; 1 drivers
|
||||
v0x55b898180150_0 .net *"_ivl_121", 0 0, L_0x55b898189c40; 1 drivers
|
||||
v0x55b898180230_0 .net *"_ivl_123", 0 0, L_0x55b89818a800; 1 drivers
|
||||
v0x55b898180310_0 .net *"_ivl_124", 0 0, L_0x55b89818aab0; 1 drivers
|
||||
v0x55b8981803f0_0 .net *"_ivl_127", 0 0, L_0x55b89818ab20; 1 drivers
|
||||
v0x55b8981804d0_0 .net *"_ivl_129", 0 0, L_0x55b89818ac10; 1 drivers
|
||||
v0x55b8981805b0_0 .net *"_ivl_130", 0 0, L_0x55b89818ae80; 1 drivers
|
||||
v0x55b898180690_0 .net *"_ivl_133", 0 0, L_0x55b89818afb0; 1 drivers
|
||||
v0x55b898180770_0 .net *"_ivl_135", 0 0, L_0x55b89818b0a0; 1 drivers
|
||||
v0x55b898180850_0 .net *"_ivl_136", 0 0, L_0x55b89818b4a0; 1 drivers
|
||||
v0x55b898180930_0 .net *"_ivl_140", 0 0, L_0x55b89818b560; 1 drivers
|
||||
v0x55b898180a10_0 .net *"_ivl_142", 0 0, L_0x55b89818b7f0; 1 drivers
|
||||
v0x55b898180af0_0 .net *"_ivl_143", 0 0, L_0x55b89818b8e0; 1 drivers
|
||||
v0x55b898180bd0_0 .net *"_ivl_146", 0 0, L_0x55b89818ba20; 1 drivers
|
||||
v0x55b898180cb0_0 .net *"_ivl_148", 0 0, L_0x55b89818bd10; 1 drivers
|
||||
v0x55b898180d90_0 .net *"_ivl_149", 0 0, L_0x55b89818be50; 1 drivers
|
||||
v0x55b898180e70_0 .net *"_ivl_15", 0 0, L_0x55b8981865c0; 1 drivers
|
||||
v0x55b898180f50_0 .net *"_ivl_152", 0 0, L_0x55b89818bec0; 1 drivers
|
||||
v0x55b898181030_0 .net *"_ivl_154", 0 0, L_0x55b89818c170; 1 drivers
|
||||
v0x55b898181320_0 .net *"_ivl_155", 0 0, L_0x55b89818c260; 1 drivers
|
||||
v0x55b898181400_0 .net *"_ivl_158", 0 0, L_0x55b89818c3b0; 1 drivers
|
||||
v0x55b8981814e0_0 .net *"_ivl_160", 0 0, L_0x55b89818c700; 1 drivers
|
||||
v0x55b8981815c0_0 .net *"_ivl_161", 0 0, L_0x55b89818cb50; 1 drivers
|
||||
v0x55b8981816a0_0 .net *"_ivl_165", 0 0, L_0x55b89818cc10; 1 drivers
|
||||
v0x55b898181780_0 .net/2u *"_ivl_166", 0 0, L_0x7f2e051b7018; 1 drivers
|
||||
v0x55b898181860_0 .net *"_ivl_168", 0 0, L_0x55b89818cd50; 1 drivers
|
||||
v0x55b898181940_0 .net *"_ivl_17", 0 0, L_0x55b8981866b0; 1 drivers
|
||||
v0x55b898181a20_0 .net *"_ivl_171", 0 0, L_0x55b89818ceb0; 1 drivers
|
||||
v0x55b898181b00_0 .net *"_ivl_173", 0 0, L_0x55b89818d1e0; 1 drivers
|
||||
v0x55b898181be0_0 .net *"_ivl_174", 0 0, L_0x55b89818d320; 1 drivers
|
||||
v0x55b898181cc0_0 .net *"_ivl_177", 0 0, L_0x55b89818d390; 1 drivers
|
||||
v0x55b898181da0_0 .net *"_ivl_179", 0 0, L_0x55b89818d680; 1 drivers
|
||||
v0x55b898181e80_0 .net *"_ivl_18", 0 0, L_0x55b8981868d0; 1 drivers
|
||||
v0x55b898181f60_0 .net *"_ivl_180", 0 0, L_0x55b89818d770; 1 drivers
|
||||
v0x55b898182040_0 .net *"_ivl_183", 0 0, L_0x55b89818d8e0; 1 drivers
|
||||
v0x55b898182120_0 .net *"_ivl_185", 0 0, L_0x55b89818dc70; 1 drivers
|
||||
v0x55b898182200_0 .net *"_ivl_186", 0 0, L_0x55b89818dda0; 1 drivers
|
||||
v0x55b8981822e0_0 .net *"_ivl_189", 0 0, L_0x55b89818de10; 1 drivers
|
||||
v0x55b8981823c0_0 .net *"_ivl_191", 0 0, L_0x55b89818e0d0; 1 drivers
|
||||
v0x55b8981824a0_0 .net *"_ivl_195", 0 0, L_0x55b89818e1c0; 1 drivers
|
||||
v0x55b898182580_0 .net *"_ivl_199", 0 0, L_0x55b89818e490; 1 drivers
|
||||
v0x55b898182660_0 .net *"_ivl_203", 0 0, L_0x55b89818e530; 1 drivers
|
||||
v0x55b898182740_0 .net *"_ivl_208", 0 0, L_0x55b89818eb80; 1 drivers
|
||||
v0x55b898182820_0 .net *"_ivl_22", 0 0, L_0x55b8981869c0; 1 drivers
|
||||
v0x55b898182900_0 .net *"_ivl_24", 0 0, L_0x55b898186b00; 1 drivers
|
||||
v0x55b8981829e0_0 .net *"_ivl_25", 0 0, L_0x55b898186bf0; 1 drivers
|
||||
v0x55b898182ac0_0 .net *"_ivl_28", 0 0, L_0x55b898186c60; 1 drivers
|
||||
v0x55b898182ba0_0 .net *"_ivl_3", 0 0, L_0x55b898186050; 1 drivers
|
||||
v0x55b898182c80_0 .net *"_ivl_30", 0 0, L_0x55b898186db0; 1 drivers
|
||||
v0x55b898182d60_0 .net *"_ivl_31", 0 0, L_0x55b898186ea0; 1 drivers
|
||||
v0x55b898182e40_0 .net *"_ivl_34", 0 0, L_0x55b898186f50; 1 drivers
|
||||
v0x55b898183330_0 .net *"_ivl_36", 0 0, L_0x55b8981870b0; 1 drivers
|
||||
v0x55b898183410_0 .net *"_ivl_37", 0 0, L_0x55b8981871a0; 1 drivers
|
||||
v0x55b8981834f0_0 .net *"_ivl_40", 0 0, L_0x55b898187210; 1 drivers
|
||||
v0x55b8981835d0_0 .net *"_ivl_42", 0 0, L_0x55b898187380; 1 drivers
|
||||
v0x55b8981836b0_0 .net *"_ivl_43", 0 0, L_0x55b898187040; 1 drivers
|
||||
v0x55b898183790_0 .net *"_ivl_47", 0 0, L_0x55b8981876e0; 1 drivers
|
||||
v0x55b898183870_0 .net *"_ivl_49", 0 0, L_0x55b8981877d0; 1 drivers
|
||||
v0x55b898183950_0 .net *"_ivl_5", 0 0, L_0x55b898186190; 1 drivers
|
||||
v0x55b898183a30_0 .net *"_ivl_50", 0 0, L_0x55b898187960; 1 drivers
|
||||
v0x55b898183b10_0 .net *"_ivl_53", 0 0, L_0x55b8981879d0; 1 drivers
|
||||
v0x55b898183bf0_0 .net *"_ivl_55", 0 0, L_0x55b898187ac0; 1 drivers
|
||||
v0x55b898183cd0_0 .net *"_ivl_56", 0 0, L_0x55b898187c60; 1 drivers
|
||||
v0x55b898183db0_0 .net *"_ivl_59", 0 0, L_0x55b8981878c0; 1 drivers
|
||||
v0x55b898183e90_0 .net *"_ivl_6", 0 0, L_0x55b8981862d0; 1 drivers
|
||||
v0x55b898183f70_0 .net *"_ivl_61", 0 0, L_0x55b898187d60; 1 drivers
|
||||
v0x55b898184050_0 .net *"_ivl_62", 0 0, L_0x55b898187f60; 1 drivers
|
||||
v0x55b898184130_0 .net *"_ivl_65", 0 0, L_0x55b898187fd0; 1 drivers
|
||||
v0x55b898184210_0 .net *"_ivl_67", 0 0, L_0x55b8981880c0; 1 drivers
|
||||
v0x55b8981842f0_0 .net *"_ivl_68", 0 0, L_0x55b898188280; 1 drivers
|
||||
v0x55b8981843d0_0 .net *"_ivl_71", 0 0, L_0x55b898188390; 1 drivers
|
||||
v0x55b8981844b0_0 .net *"_ivl_73", 0 0, L_0x55b898188480; 1 drivers
|
||||
v0x55b898184590_0 .net *"_ivl_74", 0 0, L_0x55b898188650; 1 drivers
|
||||
v0x55b898184670_0 .net *"_ivl_77", 0 0, L_0x55b8981886f0; 1 drivers
|
||||
v0x55b898184750_0 .net *"_ivl_79", 0 0, L_0x55b898188790; 1 drivers
|
||||
v0x55b898184830_0 .net *"_ivl_80", 0 0, L_0x55b898188970; 1 drivers
|
||||
v0x55b898184910_0 .net *"_ivl_83", 0 0, L_0x55b898188a90; 1 drivers
|
||||
v0x55b8981849f0_0 .net *"_ivl_85", 0 0, L_0x55b898188b80; 1 drivers
|
||||
v0x55b898184ad0_0 .net *"_ivl_86", 0 0, L_0x55b898188320; 1 drivers
|
||||
v0x55b898184bb0_0 .net *"_ivl_89", 0 0, L_0x55b898188da0; 1 drivers
|
||||
v0x55b898184c90_0 .net *"_ivl_9", 0 0, L_0x55b898186340; 1 drivers
|
||||
v0x55b898184d70_0 .net *"_ivl_91", 0 0, L_0x55b898188e90; 1 drivers
|
||||
v0x55b898184e50_0 .net *"_ivl_92", 0 0, L_0x55b8981893b0; 1 drivers
|
||||
v0x55b898184f30_0 .net *"_ivl_96", 0 0, L_0x55b898189500; 1 drivers
|
||||
v0x55b898185010_0 .net *"_ivl_98", 0 0, L_0x55b898189710; 1 drivers
|
||||
v0x55b8981850f0_0 .net *"_ivl_99", 0 0, L_0x55b898189800; 1 drivers
|
||||
v0x55b8981851d0_0 .net "a0", 3 0, L_0x55b898186790; 1 drivers
|
||||
v0x55b8981852b0_0 .net "b0", 3 0, L_0x55b898187470; 1 drivers
|
||||
v0x55b898185390_0 .net "op0", 2 0, L_0x55b89818a000; 1 drivers
|
||||
v0x55b898185470_0 .net "opCodeA", 2 0, v0x55b898185cf0_0; 1 drivers
|
||||
v0x55b898185550_0 .net "s0", 7 0, L_0x55b89818e810; alias, 1 drivers
|
||||
v0x55b898185630_0 .net "select", 3 0, v0x55b898185e80_0; 1 drivers
|
||||
v0x55b898185710_0 .net "tempAB", 3 0, L_0x55b89818b360; 1 drivers
|
||||
v0x55b8981857f0_0 .net "tempYO", 3 0, L_0x55b89818c830; 1 drivers
|
||||
v0x55b8981858d0_0 .net "y0", 7 0, L_0x55b898189090; 1 drivers
|
||||
L_0x55b898186050 .part v0x55b898185e80_0, 0, 1;
|
||||
L_0x55b898186190 .part v0x55b898185a70_0, 0, 1;
|
||||
L_0x55b898186340 .part v0x55b898185e80_0, 0, 1;
|
||||
L_0x55b898186430 .part v0x55b898185a70_0, 1, 1;
|
||||
L_0x55b8981865c0 .part v0x55b898185e80_0, 0, 1;
|
||||
L_0x55b8981866b0 .part v0x55b898185a70_0, 2, 1;
|
||||
L_0x55b898186790 .concat8 [ 1 1 1 1], L_0x55b898185f50, L_0x55b8981862d0, L_0x55b898186550, L_0x55b8981868d0;
|
||||
L_0x55b8981869c0 .part v0x55b898185e80_0, 0, 1;
|
||||
L_0x55b898186b00 .part v0x55b898185a70_0, 3, 1;
|
||||
L_0x55b898186c60 .part v0x55b898185e80_0, 1, 1;
|
||||
L_0x55b898186db0 .part v0x55b898185b50_0, 0, 1;
|
||||
L_0x55b898186f50 .part v0x55b898185e80_0, 1, 1;
|
||||
L_0x55b8981870b0 .part v0x55b898185b50_0, 1, 1;
|
||||
L_0x55b898187210 .part v0x55b898185e80_0, 1, 1;
|
||||
L_0x55b898187380 .part v0x55b898185b50_0, 2, 1;
|
||||
L_0x55b898187470 .concat8 [ 1 1 1 1], L_0x55b898186bf0, L_0x55b898186ea0, L_0x55b8981871a0, L_0x55b898187040;
|
||||
L_0x55b8981876e0 .part v0x55b898185e80_0, 1, 1;
|
||||
L_0x55b8981877d0 .part v0x55b898185b50_0, 3, 1;
|
||||
L_0x55b8981879d0 .part v0x55b898185e80_0, 2, 1;
|
||||
L_0x55b898187ac0 .part o0x7f2e0544e078, 0, 1;
|
||||
L_0x55b8981878c0 .part v0x55b898185e80_0, 2, 1;
|
||||
L_0x55b898187d60 .part o0x7f2e0544e078, 1, 1;
|
||||
L_0x55b898187fd0 .part v0x55b898185e80_0, 2, 1;
|
||||
L_0x55b8981880c0 .part o0x7f2e0544e078, 2, 1;
|
||||
L_0x55b898188390 .part v0x55b898185e80_0, 2, 1;
|
||||
L_0x55b898188480 .part o0x7f2e0544e078, 3, 1;
|
||||
L_0x55b8981886f0 .part v0x55b898185e80_0, 2, 1;
|
||||
L_0x55b898188790 .part o0x7f2e0544e078, 4, 1;
|
||||
L_0x55b898188a90 .part v0x55b898185e80_0, 2, 1;
|
||||
L_0x55b898188b80 .part o0x7f2e0544e078, 5, 1;
|
||||
L_0x55b898188da0 .part v0x55b898185e80_0, 2, 1;
|
||||
L_0x55b898188e90 .part o0x7f2e0544e078, 6, 1;
|
||||
LS_0x55b898189090_0_0 .concat8 [ 1 1 1 1], L_0x55b898187960, L_0x55b898187c60, L_0x55b898187f60, L_0x55b898188280;
|
||||
LS_0x55b898189090_0_4 .concat8 [ 1 1 1 1], L_0x55b898188650, L_0x55b898188970, L_0x55b898188320, L_0x55b8981893b0;
|
||||
L_0x55b898189090 .concat8 [ 4 4 0 0], LS_0x55b898189090_0_0, LS_0x55b898189090_0_4;
|
||||
L_0x55b898189500 .part v0x55b898185e80_0, 2, 1;
|
||||
L_0x55b898189710 .part o0x7f2e0544e078, 7, 1;
|
||||
L_0x55b898189870 .part v0x55b898185e80_0, 3, 1;
|
||||
L_0x55b898189a90 .part v0x55b898185cf0_0, 0, 1;
|
||||
L_0x55b898189ce0 .part v0x55b898185e80_0, 3, 1;
|
||||
L_0x55b898189f10 .part v0x55b898185cf0_0, 1, 1;
|
||||
L_0x55b89818a000 .concat8 [ 1 1 1 0], L_0x55b898189800, L_0x55b898189bd0, L_0x55b89818a290;
|
||||
L_0x55b89818a350 .part v0x55b898185e80_0, 3, 1;
|
||||
L_0x55b89818a440 .part v0x55b898185cf0_0, 2, 1;
|
||||
L_0x55b898189c40 .part L_0x55b898186790, 0, 1;
|
||||
L_0x55b89818a800 .part L_0x55b898187470, 0, 1;
|
||||
L_0x55b89818ab20 .part L_0x55b898186790, 1, 1;
|
||||
L_0x55b89818ac10 .part L_0x55b898187470, 1, 1;
|
||||
L_0x55b89818afb0 .part L_0x55b898186790, 2, 1;
|
||||
L_0x55b89818b0a0 .part L_0x55b898187470, 2, 1;
|
||||
L_0x55b89818b360 .concat8 [ 1 1 1 1], L_0x55b89818a690, L_0x55b89818aab0, L_0x55b89818ae80, L_0x55b89818b4a0;
|
||||
L_0x55b89818b560 .part L_0x55b898186790, 3, 1;
|
||||
L_0x55b89818b7f0 .part L_0x55b898187470, 3, 1;
|
||||
L_0x55b89818ba20 .part L_0x55b898189090, 0, 1;
|
||||
L_0x55b89818bd10 .part L_0x55b89818a000, 0, 1;
|
||||
L_0x55b89818bec0 .part L_0x55b898189090, 1, 1;
|
||||
L_0x55b89818c170 .part L_0x55b89818a000, 1, 1;
|
||||
L_0x55b89818c3b0 .part L_0x55b898189090, 2, 1;
|
||||
L_0x55b89818c700 .part L_0x55b89818a000, 2, 1;
|
||||
L_0x55b89818c830 .concat8 [ 1 1 1 1], L_0x55b89818b8e0, L_0x55b89818be50, L_0x55b89818c260, L_0x55b89818cb50;
|
||||
L_0x55b89818cc10 .part L_0x55b898189090, 3, 1;
|
||||
L_0x55b89818ceb0 .part L_0x55b89818b360, 0, 1;
|
||||
L_0x55b89818d1e0 .part L_0x55b89818c830, 0, 1;
|
||||
L_0x55b89818d390 .part L_0x55b89818b360, 1, 1;
|
||||
L_0x55b89818d680 .part L_0x55b89818c830, 1, 1;
|
||||
L_0x55b89818d8e0 .part L_0x55b89818b360, 2, 1;
|
||||
L_0x55b89818dc70 .part L_0x55b89818c830, 2, 1;
|
||||
L_0x55b89818de10 .part L_0x55b89818b360, 3, 1;
|
||||
L_0x55b89818e0d0 .part L_0x55b89818c830, 3, 1;
|
||||
L_0x55b89818e1c0 .part L_0x55b898189090, 4, 1;
|
||||
L_0x55b89818e490 .part L_0x55b898189090, 5, 1;
|
||||
L_0x55b89818e530 .part L_0x55b898189090, 6, 1;
|
||||
LS_0x55b89818e810_0_0 .concat8 [ 1 1 1 1], L_0x55b89818cd50, L_0x55b89818d320, L_0x55b89818d770, L_0x55b89818dda0;
|
||||
LS_0x55b89818e810_0_4 .concat8 [ 1 1 1 1], L_0x55b89818e1c0, L_0x55b89818e490, L_0x55b89818e530, L_0x55b89818eb80;
|
||||
L_0x55b89818e810 .concat8 [ 4 4 0 0], LS_0x55b89818e810_0_0, LS_0x55b89818e810_0_4;
|
||||
L_0x55b89818eb80 .part L_0x55b898189090, 7, 1;
|
||||
.scope S_0x55b89815f210;
|
||||
T_0 ;
|
||||
%vpi_call 2 17 "$dumpfile", "selector.vcd" {0 0 0};
|
||||
%vpi_call 2 18 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x55b898185a70_0, 0, 4;
|
||||
%pushi/vec4 2, 0, 4;
|
||||
%store/vec4 v0x55b898185b50_0, 0, 4;
|
||||
%pushi/vec4 7, 0, 3;
|
||||
%store/vec4 v0x55b898185cf0_0, 0, 3;
|
||||
%pushi/vec4 240, 0, 8;
|
||||
%store/vec4 v0x55b898185c20_0, 0, 8;
|
||||
%pushi/vec4 2, 0, 4;
|
||||
%store/vec4 v0x55b898185e80_0, 0, 4;
|
||||
%delay 5, 0;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x55b898185a70_0, 0, 4;
|
||||
%pushi/vec4 2, 0, 4;
|
||||
%store/vec4 v0x55b898185b50_0, 0, 4;
|
||||
%pushi/vec4 7, 0, 3;
|
||||
%store/vec4 v0x55b898185cf0_0, 0, 3;
|
||||
%pushi/vec4 240, 0, 8;
|
||||
%store/vec4 v0x55b898185c20_0, 0, 8;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x55b898185e80_0, 0, 4;
|
||||
%delay 5, 0;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x55b898185a70_0, 0, 4;
|
||||
%pushi/vec4 2, 0, 4;
|
||||
%store/vec4 v0x55b898185b50_0, 0, 4;
|
||||
%pushi/vec4 7, 0, 3;
|
||||
%store/vec4 v0x55b898185cf0_0, 0, 3;
|
||||
%pushi/vec4 112, 0, 8;
|
||||
%store/vec4 v0x55b898185c20_0, 0, 8;
|
||||
%pushi/vec4 4, 0, 4;
|
||||
%store/vec4 v0x55b898185e80_0, 0, 4;
|
||||
%delay 5, 0;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x55b898185a70_0, 0, 4;
|
||||
%pushi/vec4 2, 0, 4;
|
||||
%store/vec4 v0x55b898185b50_0, 0, 4;
|
||||
%pushi/vec4 7, 0, 3;
|
||||
%store/vec4 v0x55b898185cf0_0, 0, 3;
|
||||
%pushi/vec4 112, 0, 8;
|
||||
%store/vec4 v0x55b898185c20_0, 0, 8;
|
||||
%pushi/vec4 8, 0, 4;
|
||||
%store/vec4 v0x55b898185e80_0, 0, 4;
|
||||
%delay 5, 0;
|
||||
%vpi_call 2 23 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"selectorTB.v";
|
||||
"selector.v";
|
||||
@@ -1,80 +0,0 @@
|
||||
$date
|
||||
Wed Jan 8 01:16:47 2025
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module selectorTB $end
|
||||
$var wire 8 ! s0 [7:0] $end
|
||||
$var reg 4 " A [3:0] $end
|
||||
$var reg 4 # B [3:0] $end
|
||||
$var reg 8 $ Y [7:0] $end
|
||||
$var reg 3 % opCodeA [2:0] $end
|
||||
$var reg 4 & select [3:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 4 ' A [3:0] $end
|
||||
$var wire 4 ( B [3:0] $end
|
||||
$var wire 8 ) Y [7:0] $end
|
||||
$var wire 3 * opCodeA [2:0] $end
|
||||
$var wire 4 + select [3:0] $end
|
||||
$var wire 8 , y0 [7:0] $end
|
||||
$var wire 4 - tempYO [3:0] $end
|
||||
$var wire 4 . tempAB [3:0] $end
|
||||
$var wire 8 / s0 [7:0] $end
|
||||
$var wire 3 0 op0 [2:0] $end
|
||||
$var wire 4 1 b0 [3:0] $end
|
||||
$var wire 4 2 a0 [3:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
b0 2
|
||||
b10 1
|
||||
b0 0
|
||||
b10 /
|
||||
b10 .
|
||||
b0 -
|
||||
b0 ,
|
||||
b10 +
|
||||
b111 *
|
||||
bz )
|
||||
b10 (
|
||||
b1 '
|
||||
b10 &
|
||||
b111 %
|
||||
b11110000 $
|
||||
b10 #
|
||||
b1 "
|
||||
b10 !
|
||||
$end
|
||||
#5
|
||||
b1 !
|
||||
b1 /
|
||||
b1 .
|
||||
b1 2
|
||||
b0 1
|
||||
b1 &
|
||||
b1 +
|
||||
#10
|
||||
b0 .
|
||||
bx -
|
||||
bx !
|
||||
bx /
|
||||
b0 2
|
||||
bx ,
|
||||
b100 &
|
||||
b100 +
|
||||
b1110000 $
|
||||
#15
|
||||
b111 -
|
||||
b111 !
|
||||
b111 /
|
||||
b0 ,
|
||||
b111 0
|
||||
b1000 &
|
||||
b1000 +
|
||||
#20
|
||||
Reference in New Issue
Block a user