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rearrangement

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k0rrluna 2024-12-01 02:01:08 +03:00
parent 7466f916d3
commit 0237c7bcb2
277 changed files with 56884 additions and 56884 deletions
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bit3-ledTest/bit3
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@ -1,218 +1,218 @@
#! /usr/bin/vvp #! /usr/bin/vvp
:ivl_version "11.0 (stable)"; :ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL"; :ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0; :vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55f4b1a88210 .scope module, "bit3Tb" "bit3Tb" 2 1; S_0x55f4b1a88210 .scope module, "bit3Tb" "bit3Tb" 2 1;
.timescale 0 0; .timescale 0 0;
v0x55f4b1aba170_0 .var "r1", 2 0; v0x55f4b1aba170_0 .var "r1", 2 0;
v0x55f4b1aba230_0 .var "r2", 2 0; v0x55f4b1aba230_0 .var "r2", 2 0;
v0x55f4b1aba300_0 .net "w1", 3 0, L_0x55f4b1abb700; 1 drivers v0x55f4b1aba300_0 .net "w1", 3 0, L_0x55f4b1abb700; 1 drivers
S_0x55f4b1a81ef0 .scope module, "uut" "bit3adder" 2 6, 3 1 0, S_0x55f4b1a88210; S_0x55f4b1a81ef0 .scope module, "uut" "bit3adder" 2 6, 3 1 0, S_0x55f4b1a88210;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 3 "A"; .port_info 0 /INPUT 3 "A";
.port_info 1 /INPUT 3 "B"; .port_info 1 /INPUT 3 "B";
.port_info 2 /OUTPUT 4 "C"; .port_info 2 /OUTPUT 4 "C";
v0x55f4b1ab9cc0_0 .net "A", 2 0, v0x55f4b1aba170_0; 1 drivers v0x55f4b1ab9cc0_0 .net "A", 2 0, v0x55f4b1aba170_0; 1 drivers
v0x55f4b1ab9dc0_0 .net "B", 2 0, v0x55f4b1aba230_0; 1 drivers v0x55f4b1ab9dc0_0 .net "B", 2 0, v0x55f4b1aba230_0; 1 drivers
v0x55f4b1ab9ea0_0 .net "C", 3 0, L_0x55f4b1abb700; alias, 1 drivers v0x55f4b1ab9ea0_0 .net "C", 3 0, L_0x55f4b1abb700; alias, 1 drivers
v0x55f4b1ab9f60_0 .net "c1", 0 0, L_0x55f4b1aba500; 1 drivers v0x55f4b1ab9f60_0 .net "c1", 0 0, L_0x55f4b1aba500; 1 drivers
v0x55f4b1aba000_0 .net "c2", 0 0, L_0x55f4b1ababd0; 1 drivers v0x55f4b1aba000_0 .net "c2", 0 0, L_0x55f4b1ababd0; 1 drivers
L_0x55f4b1aba5c0 .part v0x55f4b1aba170_0, 0, 1; L_0x55f4b1aba5c0 .part v0x55f4b1aba170_0, 0, 1;
L_0x55f4b1aba6b0 .part v0x55f4b1aba230_0, 0, 1; L_0x55f4b1aba6b0 .part v0x55f4b1aba230_0, 0, 1;
L_0x55f4b1abad10 .part v0x55f4b1aba170_0, 1, 1; L_0x55f4b1abad10 .part v0x55f4b1aba170_0, 1, 1;
L_0x55f4b1abae40 .part v0x55f4b1aba230_0, 1, 1; L_0x55f4b1abae40 .part v0x55f4b1aba230_0, 1, 1;
L_0x55f4b1abb340 .part v0x55f4b1aba170_0, 2, 1; L_0x55f4b1abb340 .part v0x55f4b1aba170_0, 2, 1;
L_0x55f4b1abb500 .part v0x55f4b1aba230_0, 2, 1; L_0x55f4b1abb500 .part v0x55f4b1aba230_0, 2, 1;
L_0x55f4b1abb700 .concat8 [ 1 1 1 1], L_0x55f4b1aba400, L_0x55f4b1aba9b0, L_0x55f4b1abb090, L_0x55f4b1abb2b0; L_0x55f4b1abb700 .concat8 [ 1 1 1 1], L_0x55f4b1aba400, L_0x55f4b1aba9b0, L_0x55f4b1abb090, L_0x55f4b1abb2b0;
S_0x55f4b1a81d10 .scope module, "fa0" "fulladder" 3 10, 4 1 0, S_0x55f4b1a81ef0; S_0x55f4b1a81d10 .scope module, "fa0" "fulladder" 3 10, 4 1 0, S_0x55f4b1a81ef0;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C0"; .port_info 2 /INPUT 1 "C0";
.port_info 3 /OUTPUT 1 "S"; .port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C"; .port_info 4 /OUTPUT 1 "C";
L_0x55f4b1ababd0 .functor OR 1, L_0x55f4b1abab40, L_0x55f4b1aba8d0, C4<0>, C4<0>; L_0x55f4b1ababd0 .functor OR 1, L_0x55f4b1abab40, L_0x55f4b1aba8d0, C4<0>, C4<0>;
v0x55f4b1ab7ae0_0 .net "A", 0 0, L_0x55f4b1abad10; 1 drivers v0x55f4b1ab7ae0_0 .net "A", 0 0, L_0x55f4b1abad10; 1 drivers
v0x55f4b1ab7ba0_0 .net "B", 0 0, L_0x55f4b1abae40; 1 drivers v0x55f4b1ab7ba0_0 .net "B", 0 0, L_0x55f4b1abae40; 1 drivers
v0x55f4b1ab7c70_0 .net "C", 0 0, L_0x55f4b1ababd0; alias, 1 drivers v0x55f4b1ab7c70_0 .net "C", 0 0, L_0x55f4b1ababd0; alias, 1 drivers
v0x55f4b1ab7d40_0 .net "C0", 0 0, L_0x55f4b1aba500; alias, 1 drivers v0x55f4b1ab7d40_0 .net "C0", 0 0, L_0x55f4b1aba500; alias, 1 drivers
v0x55f4b1ab7e10_0 .net "C1", 0 0, L_0x55f4b1aba8d0; 1 drivers v0x55f4b1ab7e10_0 .net "C1", 0 0, L_0x55f4b1aba8d0; 1 drivers
v0x55f4b1ab7f00_0 .net "C2", 0 0, L_0x55f4b1abab40; 1 drivers v0x55f4b1ab7f00_0 .net "C2", 0 0, L_0x55f4b1abab40; 1 drivers
v0x55f4b1ab7fd0_0 .net "S", 0 0, L_0x55f4b1aba9b0; 1 drivers v0x55f4b1ab7fd0_0 .net "S", 0 0, L_0x55f4b1aba9b0; 1 drivers
v0x55f4b1ab80a0_0 .net "S1", 0 0, L_0x55f4b1aba7a0; 1 drivers v0x55f4b1ab80a0_0 .net "S1", 0 0, L_0x55f4b1aba7a0; 1 drivers
S_0x55f4b1a98e60 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x55f4b1a81d10; S_0x55f4b1a98e60 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x55f4b1a81d10;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S"; .port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C"; .port_info 3 /OUTPUT 1 "C";
L_0x55f4b1aba7a0 .functor XOR 1, L_0x55f4b1abad10, L_0x55f4b1abae40, C4<0>, C4<0>; L_0x55f4b1aba7a0 .functor XOR 1, L_0x55f4b1abad10, L_0x55f4b1abae40, C4<0>, C4<0>;
L_0x55f4b1aba8d0 .functor AND 1, L_0x55f4b1abad10, L_0x55f4b1abae40, C4<1>, C4<1>; L_0x55f4b1aba8d0 .functor AND 1, L_0x55f4b1abad10, L_0x55f4b1abae40, C4<1>, C4<1>;
v0x55f4b1a89ba0_0 .net "A", 0 0, L_0x55f4b1abad10; alias, 1 drivers v0x55f4b1a89ba0_0 .net "A", 0 0, L_0x55f4b1abad10; alias, 1 drivers
v0x55f4b1a89950_0 .net "B", 0 0, L_0x55f4b1abae40; alias, 1 drivers v0x55f4b1a89950_0 .net "B", 0 0, L_0x55f4b1abae40; alias, 1 drivers
v0x55f4b1a885d0_0 .net "C", 0 0, L_0x55f4b1aba8d0; alias, 1 drivers v0x55f4b1a885d0_0 .net "C", 0 0, L_0x55f4b1aba8d0; alias, 1 drivers
v0x55f4b1a87200_0 .net "S", 0 0, L_0x55f4b1aba7a0; alias, 1 drivers v0x55f4b1a87200_0 .net "S", 0 0, L_0x55f4b1aba7a0; alias, 1 drivers
S_0x55f4b1ab74f0 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x55f4b1a81d10; S_0x55f4b1ab74f0 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x55f4b1a81d10;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S"; .port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C"; .port_info 3 /OUTPUT 1 "C";
L_0x55f4b1aba9b0 .functor XOR 1, L_0x55f4b1aba7a0, L_0x55f4b1aba500, C4<0>, C4<0>; L_0x55f4b1aba9b0 .functor XOR 1, L_0x55f4b1aba7a0, L_0x55f4b1aba500, C4<0>, C4<0>;
L_0x55f4b1abab40 .functor AND 1, L_0x55f4b1aba7a0, L_0x55f4b1aba500, C4<1>, C4<1>; L_0x55f4b1abab40 .functor AND 1, L_0x55f4b1aba7a0, L_0x55f4b1aba500, C4<1>, C4<1>;
v0x55f4b1ab7760_0 .net "A", 0 0, L_0x55f4b1aba7a0; alias, 1 drivers v0x55f4b1ab7760_0 .net "A", 0 0, L_0x55f4b1aba7a0; alias, 1 drivers
v0x55f4b1ab7800_0 .net "B", 0 0, L_0x55f4b1aba500; alias, 1 drivers v0x55f4b1ab7800_0 .net "B", 0 0, L_0x55f4b1aba500; alias, 1 drivers
v0x55f4b1ab78a0_0 .net "C", 0 0, L_0x55f4b1abab40; alias, 1 drivers v0x55f4b1ab78a0_0 .net "C", 0 0, L_0x55f4b1abab40; alias, 1 drivers
v0x55f4b1ab7970_0 .net "S", 0 0, L_0x55f4b1aba9b0; alias, 1 drivers v0x55f4b1ab7970_0 .net "S", 0 0, L_0x55f4b1aba9b0; alias, 1 drivers
S_0x55f4b1ab8190 .scope module, "fa1" "fulladder" 3 11, 4 1 0, S_0x55f4b1a81ef0; S_0x55f4b1ab8190 .scope module, "fa1" "fulladder" 3 11, 4 1 0, S_0x55f4b1a81ef0;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C0"; .port_info 2 /INPUT 1 "C0";
.port_info 3 /OUTPUT 1 "S"; .port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C"; .port_info 4 /OUTPUT 1 "C";
L_0x55f4b1abb2b0 .functor OR 1, L_0x55f4b1abb220, L_0x55f4b1abb000, C4<0>, C4<0>; L_0x55f4b1abb2b0 .functor OR 1, L_0x55f4b1abb220, L_0x55f4b1abb000, C4<0>, C4<0>;
v0x55f4b1ab8fe0_0 .net "A", 0 0, L_0x55f4b1abb340; 1 drivers v0x55f4b1ab8fe0_0 .net "A", 0 0, L_0x55f4b1abb340; 1 drivers
v0x55f4b1ab90a0_0 .net "B", 0 0, L_0x55f4b1abb500; 1 drivers v0x55f4b1ab90a0_0 .net "B", 0 0, L_0x55f4b1abb500; 1 drivers
v0x55f4b1ab9170_0 .net "C", 0 0, L_0x55f4b1abb2b0; 1 drivers v0x55f4b1ab9170_0 .net "C", 0 0, L_0x55f4b1abb2b0; 1 drivers
v0x55f4b1ab9240_0 .net "C0", 0 0, L_0x55f4b1ababd0; alias, 1 drivers v0x55f4b1ab9240_0 .net "C0", 0 0, L_0x55f4b1ababd0; alias, 1 drivers
v0x55f4b1ab9330_0 .net "C1", 0 0, L_0x55f4b1abb000; 1 drivers v0x55f4b1ab9330_0 .net "C1", 0 0, L_0x55f4b1abb000; 1 drivers
v0x55f4b1ab9420_0 .net "C2", 0 0, L_0x55f4b1abb220; 1 drivers v0x55f4b1ab9420_0 .net "C2", 0 0, L_0x55f4b1abb220; 1 drivers
v0x55f4b1ab94c0_0 .net "S", 0 0, L_0x55f4b1abb090; 1 drivers v0x55f4b1ab94c0_0 .net "S", 0 0, L_0x55f4b1abb090; 1 drivers
v0x55f4b1ab9590_0 .net "S1", 0 0, L_0x55f4b1abaf70; 1 drivers v0x55f4b1ab9590_0 .net "S1", 0 0, L_0x55f4b1abaf70; 1 drivers
S_0x55f4b1ab8370 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x55f4b1ab8190; S_0x55f4b1ab8370 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x55f4b1ab8190;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S"; .port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C"; .port_info 3 /OUTPUT 1 "C";
L_0x55f4b1abaf70 .functor XOR 1, L_0x55f4b1abb340, L_0x55f4b1abb500, C4<0>, C4<0>; L_0x55f4b1abaf70 .functor XOR 1, L_0x55f4b1abb340, L_0x55f4b1abb500, C4<0>, C4<0>;
L_0x55f4b1abb000 .functor AND 1, L_0x55f4b1abb340, L_0x55f4b1abb500, C4<1>, C4<1>; L_0x55f4b1abb000 .functor AND 1, L_0x55f4b1abb340, L_0x55f4b1abb500, C4<1>, C4<1>;
v0x55f4b1ab85f0_0 .net "A", 0 0, L_0x55f4b1abb340; alias, 1 drivers v0x55f4b1ab85f0_0 .net "A", 0 0, L_0x55f4b1abb340; alias, 1 drivers
v0x55f4b1ab86d0_0 .net "B", 0 0, L_0x55f4b1abb500; alias, 1 drivers v0x55f4b1ab86d0_0 .net "B", 0 0, L_0x55f4b1abb500; alias, 1 drivers
v0x55f4b1ab8790_0 .net "C", 0 0, L_0x55f4b1abb000; alias, 1 drivers v0x55f4b1ab8790_0 .net "C", 0 0, L_0x55f4b1abb000; alias, 1 drivers
v0x55f4b1ab8860_0 .net "S", 0 0, L_0x55f4b1abaf70; alias, 1 drivers v0x55f4b1ab8860_0 .net "S", 0 0, L_0x55f4b1abaf70; alias, 1 drivers
S_0x55f4b1ab89d0 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x55f4b1ab8190; S_0x55f4b1ab89d0 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x55f4b1ab8190;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S"; .port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C"; .port_info 3 /OUTPUT 1 "C";
L_0x55f4b1abb090 .functor XOR 1, L_0x55f4b1abaf70, L_0x55f4b1ababd0, C4<0>, C4<0>; L_0x55f4b1abb090 .functor XOR 1, L_0x55f4b1abaf70, L_0x55f4b1ababd0, C4<0>, C4<0>;
L_0x55f4b1abb220 .functor AND 1, L_0x55f4b1abaf70, L_0x55f4b1ababd0, C4<1>, C4<1>; L_0x55f4b1abb220 .functor AND 1, L_0x55f4b1abaf70, L_0x55f4b1ababd0, C4<1>, C4<1>;
v0x55f4b1ab8c40_0 .net "A", 0 0, L_0x55f4b1abaf70; alias, 1 drivers v0x55f4b1ab8c40_0 .net "A", 0 0, L_0x55f4b1abaf70; alias, 1 drivers
v0x55f4b1ab8d10_0 .net "B", 0 0, L_0x55f4b1ababd0; alias, 1 drivers v0x55f4b1ab8d10_0 .net "B", 0 0, L_0x55f4b1ababd0; alias, 1 drivers
v0x55f4b1ab8de0_0 .net "C", 0 0, L_0x55f4b1abb220; alias, 1 drivers v0x55f4b1ab8de0_0 .net "C", 0 0, L_0x55f4b1abb220; alias, 1 drivers
v0x55f4b1ab8eb0_0 .net "S", 0 0, L_0x55f4b1abb090; alias, 1 drivers v0x55f4b1ab8eb0_0 .net "S", 0 0, L_0x55f4b1abb090; alias, 1 drivers
S_0x55f4b1ab9680 .scope module, "ha0" "halfadder" 3 9, 5 1 0, S_0x55f4b1a81ef0; S_0x55f4b1ab9680 .scope module, "ha0" "halfadder" 3 9, 5 1 0, S_0x55f4b1a81ef0;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S"; .port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C"; .port_info 3 /OUTPUT 1 "C";
L_0x55f4b1aba400 .functor XOR 1, L_0x55f4b1aba5c0, L_0x55f4b1aba6b0, C4<0>, C4<0>; L_0x55f4b1aba400 .functor XOR 1, L_0x55f4b1aba5c0, L_0x55f4b1aba6b0, C4<0>, C4<0>;
L_0x55f4b1aba500 .functor AND 1, L_0x55f4b1aba5c0, L_0x55f4b1aba6b0, C4<1>, C4<1>; L_0x55f4b1aba500 .functor AND 1, L_0x55f4b1aba5c0, L_0x55f4b1aba6b0, C4<1>, C4<1>;
v0x55f4b1ab9900_0 .net "A", 0 0, L_0x55f4b1aba5c0; 1 drivers v0x55f4b1ab9900_0 .net "A", 0 0, L_0x55f4b1aba5c0; 1 drivers
v0x55f4b1ab99c0_0 .net "B", 0 0, L_0x55f4b1aba6b0; 1 drivers v0x55f4b1ab99c0_0 .net "B", 0 0, L_0x55f4b1aba6b0; 1 drivers
v0x55f4b1ab9a80_0 .net "C", 0 0, L_0x55f4b1aba500; alias, 1 drivers v0x55f4b1ab9a80_0 .net "C", 0 0, L_0x55f4b1aba500; alias, 1 drivers
v0x55f4b1ab9ba0_0 .net "S", 0 0, L_0x55f4b1aba400; 1 drivers v0x55f4b1ab9ba0_0 .net "S", 0 0, L_0x55f4b1aba400; 1 drivers
.scope S_0x55f4b1a88210; .scope S_0x55f4b1a88210;
T_0 ; T_0 ;
%vpi_call 2 13 "$dumpfile", "bit3.vcd" {0 0 0}; %vpi_call 2 13 "$dumpfile", "bit3.vcd" {0 0 0};
%vpi_call 2 14 "$dumpvars" {0 0 0}; %vpi_call 2 14 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3; %store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 7, 0, 3; %pushi/vec4 7, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3; %store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 1, 0, 3; %pushi/vec4 1, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3; %store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 6, 0, 3; %pushi/vec4 6, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3; %store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 2, 0, 3; %pushi/vec4 2, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3; %store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 5, 0, 3; %pushi/vec4 5, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3; %store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 3, 0, 3; %pushi/vec4 3, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3; %store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 4, 0, 3; %pushi/vec4 4, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3; %store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 4, 0, 3; %pushi/vec4 4, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3; %store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 3, 0, 3; %pushi/vec4 3, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3; %store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 5, 0, 3; %pushi/vec4 5, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3; %store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 2, 0, 3; %pushi/vec4 2, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3; %store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 6, 0, 3; %pushi/vec4 6, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3; %store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 1, 0, 3; %pushi/vec4 1, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3; %store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 7, 0, 3; %pushi/vec4 7, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3; %store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3; %store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3; %store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3; %store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 1, 0, 3; %pushi/vec4 1, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3; %store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3; %store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 2, 0, 3; %pushi/vec4 2, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3; %store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3; %store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 3, 0, 3; %pushi/vec4 3, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3; %store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3; %store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 4, 0, 3; %pushi/vec4 4, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3; %store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3; %store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 5, 0, 3; %pushi/vec4 5, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3; %store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3; %store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 6, 0, 3; %pushi/vec4 6, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3; %store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3; %store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 7, 0, 3; %pushi/vec4 7, 0, 3;
%store/vec4 v0x55f4b1aba170_0, 0, 3; %store/vec4 v0x55f4b1aba170_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55f4b1aba230_0, 0, 3; %store/vec4 v0x55f4b1aba230_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%vpi_call 2 33 "$display", "Done" {0 0 0}; %vpi_call 2 33 "$display", "Done" {0 0 0};
%end; %end;
.thread T_0; .thread T_0;
# The file index is used to find the file name in the following table. # The file index is used to find the file name in the following table.
:file_names 6; :file_names 6;
"N/A"; "N/A";
"<interactive>"; "<interactive>";
"bit3Tb.v"; "bit3Tb.v";
"bit3adder.v"; "bit3adder.v";
"fulladder.v"; "fulladder.v";
"halfadder.v"; "halfadder.v";

462
bit3-ledTest/bit3.vcd
View File

@ -1,231 +1,231 @@
$date $date
Fri Jul 5 03:41:58 2024 Fri Jul 5 03:41:58 2024
$end $end
$version $version
Icarus Verilog Icarus Verilog
$end $end
$timescale $timescale
1s 1s
$end $end
$scope module bit3Tb $end $scope module bit3Tb $end
$var wire 4 ! w1 [3:0] $end $var wire 4 ! w1 [3:0] $end
$var reg 3 " r1 [2:0] $end $var reg 3 " r1 [2:0] $end
$var reg 3 # r2 [2:0] $end $var reg 3 # r2 [2:0] $end
$scope module uut $end $scope module uut $end
$var wire 3 $ A [2:0] $end $var wire 3 $ A [2:0] $end
$var wire 3 % B [2:0] $end $var wire 3 % B [2:0] $end
$var wire 1 & c2 $end $var wire 1 & c2 $end
$var wire 1 ' c1 $end $var wire 1 ' c1 $end
$var wire 4 ( C [3:0] $end $var wire 4 ( C [3:0] $end
$scope module fa0 $end $scope module fa0 $end
$var wire 1 ) A $end $var wire 1 ) A $end
$var wire 1 * B $end $var wire 1 * B $end
$var wire 1 & C $end $var wire 1 & C $end
$var wire 1 + S1 $end $var wire 1 + S1 $end
$var wire 1 , S $end $var wire 1 , S $end
$var wire 1 - C2 $end $var wire 1 - C2 $end
$var wire 1 . C1 $end $var wire 1 . C1 $end
$var wire 1 ' C0 $end $var wire 1 ' C0 $end
$scope module ha1 $end $scope module ha1 $end
$var wire 1 ) A $end $var wire 1 ) A $end
$var wire 1 * B $end $var wire 1 * B $end
$var wire 1 . C $end $var wire 1 . C $end
$var wire 1 + S $end $var wire 1 + S $end
$upscope $end $upscope $end
$scope module ha2 $end $scope module ha2 $end
$var wire 1 + A $end $var wire 1 + A $end
$var wire 1 - C $end $var wire 1 - C $end
$var wire 1 , S $end $var wire 1 , S $end
$var wire 1 ' B $end $var wire 1 ' B $end
$upscope $end $upscope $end
$upscope $end $upscope $end
$scope module fa1 $end $scope module fa1 $end
$var wire 1 / A $end $var wire 1 / A $end
$var wire 1 0 B $end $var wire 1 0 B $end
$var wire 1 1 C $end $var wire 1 1 C $end
$var wire 1 & C0 $end $var wire 1 & C0 $end
$var wire 1 2 S1 $end $var wire 1 2 S1 $end
$var wire 1 3 S $end $var wire 1 3 S $end
$var wire 1 4 C2 $end $var wire 1 4 C2 $end
$var wire 1 5 C1 $end $var wire 1 5 C1 $end
$scope module ha1 $end $scope module ha1 $end
$var wire 1 / A $end $var wire 1 / A $end
$var wire 1 0 B $end $var wire 1 0 B $end
$var wire 1 5 C $end $var wire 1 5 C $end
$var wire 1 2 S $end $var wire 1 2 S $end
$upscope $end $upscope $end
$scope module ha2 $end $scope module ha2 $end
$var wire 1 2 A $end $var wire 1 2 A $end
$var wire 1 & B $end $var wire 1 & B $end
$var wire 1 4 C $end $var wire 1 4 C $end
$var wire 1 3 S $end $var wire 1 3 S $end
$upscope $end $upscope $end
$upscope $end $upscope $end
$scope module ha0 $end $scope module ha0 $end
$var wire 1 6 A $end $var wire 1 6 A $end
$var wire 1 7 B $end $var wire 1 7 B $end
$var wire 1 ' C $end $var wire 1 ' C $end
$var wire 1 8 S $end $var wire 1 8 S $end
$upscope $end $upscope $end
$upscope $end $upscope $end
$upscope $end $upscope $end
$enddefinitions $end $enddefinitions $end
#0 #0
$dumpvars $dumpvars
18 18
17 17
06 06
05 05
04 04
13 13
12 12
01 01
10 10
0/ 0/
0. 0.
0- 0-
1, 1,
1+ 1+
1* 1*
0) 0)
b111 ( b111 (
0' 0'
0& 0&
b111 % b111 %
b0 $ b0 $
b111 # b111 #
b0 " b0 "
b111 ! b111 !
$end $end
#10 #10
07 07
16 16
b110 # b110 #
b110 % b110 %
b1 " b1 "
b1 $ b1 $
#20 #20
17 17
0* 0*
06 06
1) 1)
b101 # b101 #
b101 % b101 %
b10 " b10 "
b10 $ b10 $
#30 #30
07 07
16 16
b100 # b100 #
b100 % b100 %
b11 " b11 "
b11 $ b11 $
#40 #40
17 17
1* 1*
00 00
06 06
0) 0)
1/ 1/
b11 # b11 #
b11 % b11 %
b100 " b100 "
b100 $ b100 $
#50 #50
07 07
16 16
b10 # b10 #
b10 % b10 %
b101 " b101 "
b101 $ b101 $
#60 #60
17 17
0* 0*
06 06
1) 1)
b1 # b1 #
b1 % b1 %
b110 " b110 "
b110 $ b110 $
#70 #70
07 07
16 16
b0 # b0 #
b0 % b0 %
b111 " b111 "
b111 $ b111 $
#80 #80
0, 0,
03 03
b0 ! b0 !
b0 ( b0 (
08 08
0+ 0+
02 02
06 06
0) 0)
0/ 0/
b0 " b0 "
b0 $ b0 $
#90 #90
b1 ! b1 !
b1 ( b1 (
18 18
16 16
b1 " b1 "
b1 $ b1 $
#100 #100
1, 1,
b10 ! b10 !
b10 ( b10 (
08 08
1+ 1+
06 06
1) 1)
b10 " b10 "
b10 $ b10 $
#110 #110
b11 ! b11 !
b11 ( b11 (
18 18
16 16
b11 " b11 "
b11 $ b11 $
#120 #120
0, 0,
13 13
b100 ! b100 !
b100 ( b100 (
08 08
0+ 0+
12 12
06 06
0) 0)
1/ 1/
b100 " b100 "
b100 $ b100 $
#130 #130
b101 ! b101 !
b101 ( b101 (
18 18
16 16
b101 " b101 "
b101 $ b101 $
#140 #140
1, 1,
b110 ! b110 !
b110 ( b110 (
08 08
1+ 1+
06 06
1) 1)
b110 " b110 "
b110 $ b110 $
#150 #150
b111 ! b111 !
b111 ( b111 (
18 18
16 16
b111 " b111 "
b111 $ b111 $
#160 #160

70
bit3-ledTest/bit3Tb.v
View File

@ -1,36 +1,36 @@
module bit3Tb(); module bit3Tb();
reg [2:0] r1, r2; reg [2:0] r1, r2;
wire [3:0] w1; wire [3:0] w1;
bit3adder uut( bit3adder uut(
.A(r1), .A(r1),
.B(r2), .B(r2),
.C(w1) .C(w1)
); );
initial begin initial begin
$dumpfile("bit3.vcd"); $dumpfile("bit3.vcd");
$dumpvars; $dumpvars;
r1 = 3'b000; r2 = 3'b111; #10; r1 = 3'b000; r2 = 3'b111; #10;
r1 = 3'b001; r2 = 3'b110; #10; r1 = 3'b001; r2 = 3'b110; #10;
r1 = 3'b010; r2 = 3'b101; #10; r1 = 3'b010; r2 = 3'b101; #10;
r1 = 3'b011; r2 = 3'b100; #10; r1 = 3'b011; r2 = 3'b100; #10;
r1 = 3'b100; r2 = 3'b011; #10; r1 = 3'b100; r2 = 3'b011; #10;
r1 = 3'b101; r2 = 3'b010; #10; r1 = 3'b101; r2 = 3'b010; #10;
r1 = 3'b110; r2 = 3'b001; #10; r1 = 3'b110; r2 = 3'b001; #10;
r1 = 3'b111; r2 = 3'b000; #10; r1 = 3'b111; r2 = 3'b000; #10;
r1 = 3'b000; r2 = 3'b000; #10; r1 = 3'b000; r2 = 3'b000; #10;
r1 = 3'b001; r2 = 3'b000; #10; r1 = 3'b001; r2 = 3'b000; #10;
r1 = 3'b010; r2 = 3'b000; #10; r1 = 3'b010; r2 = 3'b000; #10;
r1 = 3'b011; r2 = 3'b000; #10; r1 = 3'b011; r2 = 3'b000; #10;
r1 = 3'b100; r2 = 3'b000; #10; r1 = 3'b100; r2 = 3'b000; #10;
r1 = 3'b101; r2 = 3'b000; #10; r1 = 3'b101; r2 = 3'b000; #10;
r1 = 3'b110; r2 = 3'b000; #10; r1 = 3'b110; r2 = 3'b000; #10;
r1 = 3'b111; r2 = 3'b000; #10; r1 = 3'b111; r2 = 3'b000; #10;
$display("Done"); $display("Done");
end end
endmodule endmodule

24
bit3-ledTest/fulladder.v
View File

@ -1,13 +1,13 @@
module fulladder( module fulladder(
input A, B, C0, input A, B, C0,
output S, C output S, C
); );
wire S1,C1,C2; wire S1,C1,C2;
halfadder ha1(A, B, S1, C1); halfadder ha1(A, B, S1, C1);
halfadder ha2(S1, C0, S, C2); halfadder ha2(S1, C0, S, C2);
or (C, C2, C1); or (C, C2, C1);
endmodule endmodule

16
bit3-ledTest/halfadder.v
View File

@ -1,9 +1,9 @@
module halfadder( module halfadder(
input A,B, input A,B,
output S,C output S,C
); );
xor (S, A, B); xor (S, A, B);
and (C, A, B); and (C, A, B);
endmodule endmodule

378
bit3-ledTest/led1
View File

@ -1,189 +1,189 @@
#! /usr/bin/vvp #! /usr/bin/vvp
:ivl_version "11.0 (stable)"; :ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL"; :ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0; :vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x5585ad829490 .scope module, "ledTest" "ledTest" 2 1; S_0x5585ad829490 .scope module, "ledTest" "ledTest" 2 1;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 2 "v1"; .port_info 0 /INPUT 2 "v1";
.port_info 1 /INPUT 2 "v2"; .port_info 1 /INPUT 2 "v2";
.port_info 2 /OUTPUT 6 "L14"; .port_info 2 /OUTPUT 6 "L14";
v0x5585ad857530_0 .var "L14", 5 0; v0x5585ad857530_0 .var "L14", 5 0;
L_0x7f76fd14c018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; L_0x7f76fd14c018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x5585ad857610_0 .net/2u *"_ivl_0", 0 0, L_0x7f76fd14c018; 1 drivers v0x5585ad857610_0 .net/2u *"_ivl_0", 0 0, L_0x7f76fd14c018; 1 drivers
L_0x7f76fd14c060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; L_0x7f76fd14c060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x5585ad8576f0_0 .net/2u *"_ivl_4", 0 0, L_0x7f76fd14c060; 1 drivers v0x5585ad8576f0_0 .net/2u *"_ivl_4", 0 0, L_0x7f76fd14c060; 1 drivers
v0x5585ad8577b0_0 .net "sum", 3 0, L_0x5585ad858d60; 1 drivers v0x5585ad8577b0_0 .net "sum", 3 0, L_0x5585ad858d60; 1 drivers
o0x7f76fd195ac8 .functor BUFZ 2, C4<zz>; HiZ drive o0x7f76fd195ac8 .functor BUFZ 2, C4<zz>; HiZ drive
v0x5585ad8578a0_0 .net "v1", 1 0, o0x7f76fd195ac8; 0 drivers v0x5585ad8578a0_0 .net "v1", 1 0, o0x7f76fd195ac8; 0 drivers
o0x7f76fd195af8 .functor BUFZ 2, C4<zz>; HiZ drive o0x7f76fd195af8 .functor BUFZ 2, C4<zz>; HiZ drive
v0x5585ad8579b0_0 .net "v2", 1 0, o0x7f76fd195af8; 0 drivers v0x5585ad8579b0_0 .net "v2", 1 0, o0x7f76fd195af8; 0 drivers
E_0x5585ad83ba80 .event edge, v0x5585ad857260_0; E_0x5585ad83ba80 .event edge, v0x5585ad857260_0;
L_0x5585ad858e50 .concat [ 2 1 0 0], o0x7f76fd195ac8, L_0x7f76fd14c018; L_0x5585ad858e50 .concat [ 2 1 0 0], o0x7f76fd195ac8, L_0x7f76fd14c018;
L_0x5585ad858f80 .concat [ 2 1 0 0], o0x7f76fd195af8, L_0x7f76fd14c060; L_0x5585ad858f80 .concat [ 2 1 0 0], o0x7f76fd195af8, L_0x7f76fd14c060;
S_0x5585ad822f60 .scope module, "adder" "bit3adder" 2 8, 3 1 0, S_0x5585ad829490; S_0x5585ad822f60 .scope module, "adder" "bit3adder" 2 8, 3 1 0, S_0x5585ad829490;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 3 "A"; .port_info 0 /INPUT 3 "A";
.port_info 1 /INPUT 3 "B"; .port_info 1 /INPUT 3 "B";
.port_info 2 /OUTPUT 4 "C"; .port_info 2 /OUTPUT 4 "C";
v0x5585ad857080_0 .net "A", 2 0, L_0x5585ad858e50; 1 drivers v0x5585ad857080_0 .net "A", 2 0, L_0x5585ad858e50; 1 drivers
v0x5585ad857180_0 .net "B", 2 0, L_0x5585ad858f80; 1 drivers v0x5585ad857180_0 .net "B", 2 0, L_0x5585ad858f80; 1 drivers
v0x5585ad857260_0 .net "C", 3 0, L_0x5585ad858d60; alias, 1 drivers v0x5585ad857260_0 .net "C", 3 0, L_0x5585ad858d60; alias, 1 drivers
v0x5585ad857320_0 .net "c1", 0 0, L_0x5585ad857be0; 1 drivers v0x5585ad857320_0 .net "c1", 0 0, L_0x5585ad857be0; 1 drivers
v0x5585ad8573c0_0 .net "c2", 0 0, L_0x5585ad858280; 1 drivers v0x5585ad8573c0_0 .net "c2", 0 0, L_0x5585ad858280; 1 drivers
L_0x5585ad857d30 .part L_0x5585ad858e50, 0, 1; L_0x5585ad857d30 .part L_0x5585ad858e50, 0, 1;
L_0x5585ad857dd0 .part L_0x5585ad858f80, 0, 1; L_0x5585ad857dd0 .part L_0x5585ad858f80, 0, 1;
L_0x5585ad8583c0 .part L_0x5585ad858e50, 1, 1; L_0x5585ad8583c0 .part L_0x5585ad858e50, 1, 1;
L_0x5585ad8584f0 .part L_0x5585ad858f80, 1, 1; L_0x5585ad8584f0 .part L_0x5585ad858f80, 1, 1;
L_0x5585ad858ac0 .part L_0x5585ad858e50, 2, 1; L_0x5585ad858ac0 .part L_0x5585ad858e50, 2, 1;
L_0x5585ad858bf0 .part L_0x5585ad858f80, 2, 1; L_0x5585ad858bf0 .part L_0x5585ad858f80, 2, 1;
L_0x5585ad858d60 .concat8 [ 1 1 1 1], L_0x5585ad857b10, L_0x5585ad858060, L_0x5585ad858810, L_0x5585ad858a30; L_0x5585ad858d60 .concat8 [ 1 1 1 1], L_0x5585ad857b10, L_0x5585ad858060, L_0x5585ad858810, L_0x5585ad858a30;
S_0x5585ad823140 .scope module, "fa0" "fulladder" 3 10, 4 1 0, S_0x5585ad822f60; S_0x5585ad823140 .scope module, "fa0" "fulladder" 3 10, 4 1 0, S_0x5585ad822f60;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C0"; .port_info 2 /INPUT 1 "C0";
.port_info 3 /OUTPUT 1 "S"; .port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C"; .port_info 4 /OUTPUT 1 "C";
L_0x5585ad858280 .functor OR 1, L_0x5585ad8581f0, L_0x5585ad857f80, C4<0>, C4<0>; L_0x5585ad858280 .functor OR 1, L_0x5585ad8581f0, L_0x5585ad857f80, C4<0>, C4<0>;
v0x5585ad854ea0_0 .net "A", 0 0, L_0x5585ad8583c0; 1 drivers v0x5585ad854ea0_0 .net "A", 0 0, L_0x5585ad8583c0; 1 drivers
v0x5585ad854f60_0 .net "B", 0 0, L_0x5585ad8584f0; 1 drivers v0x5585ad854f60_0 .net "B", 0 0, L_0x5585ad8584f0; 1 drivers
v0x5585ad855030_0 .net "C", 0 0, L_0x5585ad858280; alias, 1 drivers v0x5585ad855030_0 .net "C", 0 0, L_0x5585ad858280; alias, 1 drivers
v0x5585ad855100_0 .net "C0", 0 0, L_0x5585ad857be0; alias, 1 drivers v0x5585ad855100_0 .net "C0", 0 0, L_0x5585ad857be0; alias, 1 drivers
v0x5585ad8551d0_0 .net "C1", 0 0, L_0x5585ad857f80; 1 drivers v0x5585ad8551d0_0 .net "C1", 0 0, L_0x5585ad857f80; 1 drivers
v0x5585ad8552c0_0 .net "C2", 0 0, L_0x5585ad8581f0; 1 drivers v0x5585ad8552c0_0 .net "C2", 0 0, L_0x5585ad8581f0; 1 drivers
v0x5585ad855390_0 .net "S", 0 0, L_0x5585ad858060; 1 drivers v0x5585ad855390_0 .net "S", 0 0, L_0x5585ad858060; 1 drivers
v0x5585ad855460_0 .net "S1", 0 0, L_0x5585ad857e70; 1 drivers v0x5585ad855460_0 .net "S1", 0 0, L_0x5585ad857e70; 1 drivers
S_0x5585ad8385a0 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x5585ad823140; S_0x5585ad8385a0 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x5585ad823140;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S"; .port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C"; .port_info 3 /OUTPUT 1 "C";
L_0x5585ad857e70 .functor XOR 1, L_0x5585ad8583c0, L_0x5585ad8584f0, C4<0>, C4<0>; L_0x5585ad857e70 .functor XOR 1, L_0x5585ad8583c0, L_0x5585ad8584f0, C4<0>, C4<0>;
L_0x5585ad857f80 .functor AND 1, L_0x5585ad8583c0, L_0x5585ad8584f0, C4<1>, C4<1>; L_0x5585ad857f80 .functor AND 1, L_0x5585ad8583c0, L_0x5585ad8584f0, C4<1>, C4<1>;
v0x5585ad839660_0 .net "A", 0 0, L_0x5585ad8583c0; alias, 1 drivers v0x5585ad839660_0 .net "A", 0 0, L_0x5585ad8583c0; alias, 1 drivers
v0x5585ad828480_0 .net "B", 0 0, L_0x5585ad8584f0; alias, 1 drivers v0x5585ad828480_0 .net "B", 0 0, L_0x5585ad8584f0; alias, 1 drivers
v0x5585ad8546d0_0 .net "C", 0 0, L_0x5585ad857f80; alias, 1 drivers v0x5585ad8546d0_0 .net "C", 0 0, L_0x5585ad857f80; alias, 1 drivers
v0x5585ad854770_0 .net "S", 0 0, L_0x5585ad857e70; alias, 1 drivers v0x5585ad854770_0 .net "S", 0 0, L_0x5585ad857e70; alias, 1 drivers
S_0x5585ad8548b0 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x5585ad823140; S_0x5585ad8548b0 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x5585ad823140;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S"; .port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C"; .port_info 3 /OUTPUT 1 "C";
L_0x5585ad858060 .functor XOR 1, L_0x5585ad857e70, L_0x5585ad857be0, C4<0>, C4<0>; L_0x5585ad858060 .functor XOR 1, L_0x5585ad857e70, L_0x5585ad857be0, C4<0>, C4<0>;
L_0x5585ad8581f0 .functor AND 1, L_0x5585ad857e70, L_0x5585ad857be0, C4<1>, C4<1>; L_0x5585ad8581f0 .functor AND 1, L_0x5585ad857e70, L_0x5585ad857be0, C4<1>, C4<1>;
v0x5585ad854b20_0 .net "A", 0 0, L_0x5585ad857e70; alias, 1 drivers v0x5585ad854b20_0 .net "A", 0 0, L_0x5585ad857e70; alias, 1 drivers
v0x5585ad854bc0_0 .net "B", 0 0, L_0x5585ad857be0; alias, 1 drivers v0x5585ad854bc0_0 .net "B", 0 0, L_0x5585ad857be0; alias, 1 drivers
v0x5585ad854c60_0 .net "C", 0 0, L_0x5585ad8581f0; alias, 1 drivers v0x5585ad854c60_0 .net "C", 0 0, L_0x5585ad8581f0; alias, 1 drivers
v0x5585ad854d30_0 .net "S", 0 0, L_0x5585ad858060; alias, 1 drivers v0x5585ad854d30_0 .net "S", 0 0, L_0x5585ad858060; alias, 1 drivers
S_0x5585ad855550 .scope module, "fa1" "fulladder" 3 11, 4 1 0, S_0x5585ad822f60; S_0x5585ad855550 .scope module, "fa1" "fulladder" 3 11, 4 1 0, S_0x5585ad822f60;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C0"; .port_info 2 /INPUT 1 "C0";
.port_info 3 /OUTPUT 1 "S"; .port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C"; .port_info 4 /OUTPUT 1 "C";
L_0x5585ad858a30 .functor OR 1, L_0x5585ad8589a0, L_0x5585ad858730, C4<0>, C4<0>; L_0x5585ad858a30 .functor OR 1, L_0x5585ad8589a0, L_0x5585ad858730, C4<0>, C4<0>;
v0x5585ad8563a0_0 .net "A", 0 0, L_0x5585ad858ac0; 1 drivers v0x5585ad8563a0_0 .net "A", 0 0, L_0x5585ad858ac0; 1 drivers
v0x5585ad856460_0 .net "B", 0 0, L_0x5585ad858bf0; 1 drivers v0x5585ad856460_0 .net "B", 0 0, L_0x5585ad858bf0; 1 drivers
v0x5585ad856530_0 .net "C", 0 0, L_0x5585ad858a30; 1 drivers v0x5585ad856530_0 .net "C", 0 0, L_0x5585ad858a30; 1 drivers
v0x5585ad856600_0 .net "C0", 0 0, L_0x5585ad858280; alias, 1 drivers v0x5585ad856600_0 .net "C0", 0 0, L_0x5585ad858280; alias, 1 drivers
v0x5585ad8566f0_0 .net "C1", 0 0, L_0x5585ad858730; 1 drivers v0x5585ad8566f0_0 .net "C1", 0 0, L_0x5585ad858730; 1 drivers
v0x5585ad8567e0_0 .net "C2", 0 0, L_0x5585ad8589a0; 1 drivers v0x5585ad8567e0_0 .net "C2", 0 0, L_0x5585ad8589a0; 1 drivers
v0x5585ad856880_0 .net "S", 0 0, L_0x5585ad858810; 1 drivers v0x5585ad856880_0 .net "S", 0 0, L_0x5585ad858810; 1 drivers
v0x5585ad856950_0 .net "S1", 0 0, L_0x5585ad858650; 1 drivers v0x5585ad856950_0 .net "S1", 0 0, L_0x5585ad858650; 1 drivers
S_0x5585ad855730 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x5585ad855550; S_0x5585ad855730 .scope module, "ha1" "halfadder" 4 8, 5 1 0, S_0x5585ad855550;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S"; .port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C"; .port_info 3 /OUTPUT 1 "C";
L_0x5585ad858650 .functor XOR 1, L_0x5585ad858ac0, L_0x5585ad858bf0, C4<0>, C4<0>; L_0x5585ad858650 .functor XOR 1, L_0x5585ad858ac0, L_0x5585ad858bf0, C4<0>, C4<0>;
L_0x5585ad858730 .functor AND 1, L_0x5585ad858ac0, L_0x5585ad858bf0, C4<1>, C4<1>; L_0x5585ad858730 .functor AND 1, L_0x5585ad858ac0, L_0x5585ad858bf0, C4<1>, C4<1>;
v0x5585ad8559b0_0 .net "A", 0 0, L_0x5585ad858ac0; alias, 1 drivers v0x5585ad8559b0_0 .net "A", 0 0, L_0x5585ad858ac0; alias, 1 drivers
v0x5585ad855a90_0 .net "B", 0 0, L_0x5585ad858bf0; alias, 1 drivers v0x5585ad855a90_0 .net "B", 0 0, L_0x5585ad858bf0; alias, 1 drivers
v0x5585ad855b50_0 .net "C", 0 0, L_0x5585ad858730; alias, 1 drivers v0x5585ad855b50_0 .net "C", 0 0, L_0x5585ad858730; alias, 1 drivers
v0x5585ad855c20_0 .net "S", 0 0, L_0x5585ad858650; alias, 1 drivers v0x5585ad855c20_0 .net "S", 0 0, L_0x5585ad858650; alias, 1 drivers
S_0x5585ad855d90 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x5585ad855550; S_0x5585ad855d90 .scope module, "ha2" "halfadder" 4 9, 5 1 0, S_0x5585ad855550;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S"; .port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C"; .port_info 3 /OUTPUT 1 "C";
L_0x5585ad858810 .functor XOR 1, L_0x5585ad858650, L_0x5585ad858280, C4<0>, C4<0>; L_0x5585ad858810 .functor XOR 1, L_0x5585ad858650, L_0x5585ad858280, C4<0>, C4<0>;
L_0x5585ad8589a0 .functor AND 1, L_0x5585ad858650, L_0x5585ad858280, C4<1>, C4<1>; L_0x5585ad8589a0 .functor AND 1, L_0x5585ad858650, L_0x5585ad858280, C4<1>, C4<1>;
v0x5585ad856000_0 .net "A", 0 0, L_0x5585ad858650; alias, 1 drivers v0x5585ad856000_0 .net "A", 0 0, L_0x5585ad858650; alias, 1 drivers
v0x5585ad8560d0_0 .net "B", 0 0, L_0x5585ad858280; alias, 1 drivers v0x5585ad8560d0_0 .net "B", 0 0, L_0x5585ad858280; alias, 1 drivers
v0x5585ad8561a0_0 .net "C", 0 0, L_0x5585ad8589a0; alias, 1 drivers v0x5585ad8561a0_0 .net "C", 0 0, L_0x5585ad8589a0; alias, 1 drivers
v0x5585ad856270_0 .net "S", 0 0, L_0x5585ad858810; alias, 1 drivers v0x5585ad856270_0 .net "S", 0 0, L_0x5585ad858810; alias, 1 drivers
S_0x5585ad856a40 .scope module, "ha0" "halfadder" 3 9, 5 1 0, S_0x5585ad822f60; S_0x5585ad856a40 .scope module, "ha0" "halfadder" 3 9, 5 1 0, S_0x5585ad822f60;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S"; .port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C"; .port_info 3 /OUTPUT 1 "C";
L_0x5585ad857b10 .functor XOR 1, L_0x5585ad857d30, L_0x5585ad857dd0, C4<0>, C4<0>; L_0x5585ad857b10 .functor XOR 1, L_0x5585ad857d30, L_0x5585ad857dd0, C4<0>, C4<0>;
L_0x5585ad857be0 .functor AND 1, L_0x5585ad857d30, L_0x5585ad857dd0, C4<1>, C4<1>; L_0x5585ad857be0 .functor AND 1, L_0x5585ad857d30, L_0x5585ad857dd0, C4<1>, C4<1>;
v0x5585ad856cc0_0 .net "A", 0 0, L_0x5585ad857d30; 1 drivers v0x5585ad856cc0_0 .net "A", 0 0, L_0x5585ad857d30; 1 drivers
v0x5585ad856d80_0 .net "B", 0 0, L_0x5585ad857dd0; 1 drivers v0x5585ad856d80_0 .net "B", 0 0, L_0x5585ad857dd0; 1 drivers
v0x5585ad856e40_0 .net "C", 0 0, L_0x5585ad857be0; alias, 1 drivers v0x5585ad856e40_0 .net "C", 0 0, L_0x5585ad857be0; alias, 1 drivers
v0x5585ad856f60_0 .net "S", 0 0, L_0x5585ad857b10; 1 drivers v0x5585ad856f60_0 .net "S", 0 0, L_0x5585ad857b10; 1 drivers
.scope S_0x5585ad829490; .scope S_0x5585ad829490;
T_0 ; T_0 ;
%wait E_0x5585ad83ba80; %wait E_0x5585ad83ba80;
%pushi/vec4 0, 0, 6; %pushi/vec4 0, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6; %store/vec4 v0x5585ad857530_0, 0, 6;
%load/vec4 v0x5585ad8577b0_0; %load/vec4 v0x5585ad8577b0_0;
%cmpi/e 0, 0, 4; %cmpi/e 0, 0, 4;
%jmp/0xz T_0.0, 4; %jmp/0xz T_0.0, 4;
%pushi/vec4 0, 0, 6; %pushi/vec4 0, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6; %store/vec4 v0x5585ad857530_0, 0, 6;
%jmp T_0.1; %jmp T_0.1;
T_0.0 ; T_0.0 ;
%load/vec4 v0x5585ad8577b0_0; %load/vec4 v0x5585ad8577b0_0;
%cmpi/e 1, 0, 4; %cmpi/e 1, 0, 4;
%jmp/0xz T_0.2, 4; %jmp/0xz T_0.2, 4;
%pushi/vec4 1, 0, 6; %pushi/vec4 1, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6; %store/vec4 v0x5585ad857530_0, 0, 6;
%jmp T_0.3; %jmp T_0.3;
T_0.2 ; T_0.2 ;
%load/vec4 v0x5585ad8577b0_0; %load/vec4 v0x5585ad8577b0_0;
%cmpi/e 2, 0, 4; %cmpi/e 2, 0, 4;
%jmp/0xz T_0.4, 4; %jmp/0xz T_0.4, 4;
%pushi/vec4 3, 0, 6; %pushi/vec4 3, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6; %store/vec4 v0x5585ad857530_0, 0, 6;
%jmp T_0.5; %jmp T_0.5;
T_0.4 ; T_0.4 ;
%load/vec4 v0x5585ad8577b0_0; %load/vec4 v0x5585ad8577b0_0;
%cmpi/e 3, 0, 4; %cmpi/e 3, 0, 4;
%jmp/0xz T_0.6, 4; %jmp/0xz T_0.6, 4;
%pushi/vec4 7, 0, 6; %pushi/vec4 7, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6; %store/vec4 v0x5585ad857530_0, 0, 6;
%jmp T_0.7; %jmp T_0.7;
T_0.6 ; T_0.6 ;
%load/vec4 v0x5585ad8577b0_0; %load/vec4 v0x5585ad8577b0_0;
%cmpi/e 4, 0, 4; %cmpi/e 4, 0, 4;
%jmp/0xz T_0.8, 4; %jmp/0xz T_0.8, 4;
%pushi/vec4 15, 0, 6; %pushi/vec4 15, 0, 6;
%store/vec4 v0x5585ad857530_0, 0, 6; %store/vec4 v0x5585ad857530_0, 0, 6;
T_0.8 ; T_0.8 ;
T_0.7 ; T_0.7 ;
T_0.5 ; T_0.5 ;
T_0.3 ; T_0.3 ;
T_0.1 ; T_0.1 ;
%jmp T_0; %jmp T_0;
.thread T_0, $push; .thread T_0, $push;
# The file index is used to find the file name in the following table. # The file index is used to find the file name in the following table.
:file_names 6; :file_names 6;
"N/A"; "N/A";
"<interactive>"; "<interactive>";
"ledTest.v"; "ledTest.v";
"bit3adder.v"; "bit3adder.v";
"fulladder.v"; "fulladder.v";
"halfadder.v"; "halfadder.v";

64
bit3-ledTest/ledTest.v
View File

@ -1,33 +1,33 @@
module ledTest ( module ledTest (
input[1:0] v1, v2, input[1:0] v1, v2,
output [5:0] L14 output [5:0] L14
); );
wire[3:0] sum; wire[3:0] sum;
bit3adder adder( bit3adder adder(
.A({1'b0, v1}), .A({1'b0, v1}),
.B({1'b0, v2}), .B({1'b0, v2}),
.C(sum) .C(sum)
); );
always @(*) begin always @(*) begin
L14 = 6'b000_000; L14 = 6'b000_000;
if(sum == 4'd0) begin if(sum == 4'd0) begin
L14 = 6'b000_000; L14 = 6'b000_000;
end end
else if(sum == 4'd1) else if(sum == 4'd1)
L14 = 6'b000_001; L14 = 6'b000_001;
else if(sum == 4'd2) else if(sum == 4'd2)
L14 = 6'b000_011; L14 = 6'b000_011;
else if(sum == 4'd3) else if(sum == 4'd3)
L14 = 6'b000_111; L14 = 6'b000_111;
else if(sum == 4'd4) else if(sum == 4'd4)
L14 = 6'b001_111; L14 = 6'b001_111;
end end
endmodule endmodule

6
bit3-ledTest/ledTest2.v
View File

@ -1,4 +1,4 @@
module ledTest2 ( module ledTest2 (
input input
) )
// Buton verisi eklenecek TO-DO // Buton verisi eklenecek TO-DO

344
bit3-ledTest/sub1
View File

@ -1,172 +1,172 @@
#! /usr/bin/vvp #! /usr/bin/vvp
:ivl_version "11.0 (stable)"; :ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL"; :ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0; :vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55c07506ba60 .scope module, "fulladder" "fulladder" 2 1; S_0x55c07506ba60 .scope module, "fulladder" "fulladder" 2 1;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C0"; .port_info 2 /INPUT 1 "C0";
.port_info 3 /OUTPUT 1 "S"; .port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "C"; .port_info 4 /OUTPUT 1 "C";
L_0x55c0750836c0 .functor OR 1, L_0x55c0750835e0, L_0x55c075083400, C4<0>, C4<0>; L_0x55c0750836c0 .functor OR 1, L_0x55c0750835e0, L_0x55c075083400, C4<0>, C4<0>;
o0x7ffa3a6e3018 .functor BUFZ 1, C4<z>; HiZ drive o0x7ffa3a6e3018 .functor BUFZ 1, C4<z>; HiZ drive
v0x55c0750823d0_0 .net "A", 0 0, o0x7ffa3a6e3018; 0 drivers v0x55c0750823d0_0 .net "A", 0 0, o0x7ffa3a6e3018; 0 drivers
o0x7ffa3a6e3048 .functor BUFZ 1, C4<z>; HiZ drive o0x7ffa3a6e3048 .functor BUFZ 1, C4<z>; HiZ drive
v0x55c075082490_0 .net "B", 0 0, o0x7ffa3a6e3048; 0 drivers v0x55c075082490_0 .net "B", 0 0, o0x7ffa3a6e3048; 0 drivers
v0x55c075082560_0 .net "C", 0 0, L_0x55c0750836c0; 1 drivers v0x55c075082560_0 .net "C", 0 0, L_0x55c0750836c0; 1 drivers
o0x7ffa3a6e3198 .functor BUFZ 1, C4<z>; HiZ drive o0x7ffa3a6e3198 .functor BUFZ 1, C4<z>; HiZ drive
v0x55c075082630_0 .net "C0", 0 0, o0x7ffa3a6e3198; 0 drivers v0x55c075082630_0 .net "C0", 0 0, o0x7ffa3a6e3198; 0 drivers
v0x55c075082700_0 .net "C1", 0 0, L_0x55c075083400; 1 drivers v0x55c075082700_0 .net "C1", 0 0, L_0x55c075083400; 1 drivers
v0x55c0750827f0_0 .net "C2", 0 0, L_0x55c0750835e0; 1 drivers v0x55c0750827f0_0 .net "C2", 0 0, L_0x55c0750835e0; 1 drivers
v0x55c0750828c0_0 .net "S", 0 0, L_0x55c0750834e0; 1 drivers v0x55c0750828c0_0 .net "S", 0 0, L_0x55c0750834e0; 1 drivers
v0x55c075082990_0 .net "S1", 0 0, L_0x55c0750832f0; 1 drivers v0x55c075082990_0 .net "S1", 0 0, L_0x55c0750832f0; 1 drivers
S_0x55c07506dab0 .scope module, "ha1" "halfadder" 2 8, 3 1 0, S_0x55c07506ba60; S_0x55c07506dab0 .scope module, "ha1" "halfadder" 2 8, 3 1 0, S_0x55c07506ba60;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S"; .port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C"; .port_info 3 /OUTPUT 1 "C";
L_0x55c0750832f0 .functor XOR 1, o0x7ffa3a6e3018, o0x7ffa3a6e3048, C4<0>, C4<0>; L_0x55c0750832f0 .functor XOR 1, o0x7ffa3a6e3018, o0x7ffa3a6e3048, C4<0>, C4<0>;
L_0x55c075083400 .functor AND 1, o0x7ffa3a6e3018, o0x7ffa3a6e3048, C4<1>, C4<1>; L_0x55c075083400 .functor AND 1, o0x7ffa3a6e3018, o0x7ffa3a6e3048, C4<1>, C4<1>;
v0x55c07506dd30_0 .net "A", 0 0, o0x7ffa3a6e3018; alias, 0 drivers v0x55c07506dd30_0 .net "A", 0 0, o0x7ffa3a6e3018; alias, 0 drivers
v0x55c075081ab0_0 .net "B", 0 0, o0x7ffa3a6e3048; alias, 0 drivers v0x55c075081ab0_0 .net "B", 0 0, o0x7ffa3a6e3048; alias, 0 drivers
v0x55c075081b70_0 .net "C", 0 0, L_0x55c075083400; alias, 1 drivers v0x55c075081b70_0 .net "C", 0 0, L_0x55c075083400; alias, 1 drivers
v0x55c075081c40_0 .net "S", 0 0, L_0x55c0750832f0; alias, 1 drivers v0x55c075081c40_0 .net "S", 0 0, L_0x55c0750832f0; alias, 1 drivers
S_0x55c075081db0 .scope module, "ha2" "halfadder" 2 9, 3 1 0, S_0x55c07506ba60; S_0x55c075081db0 .scope module, "ha2" "halfadder" 2 9, 3 1 0, S_0x55c07506ba60;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S"; .port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C"; .port_info 3 /OUTPUT 1 "C";
L_0x55c0750834e0 .functor XOR 1, L_0x55c0750832f0, o0x7ffa3a6e3198, C4<0>, C4<0>; L_0x55c0750834e0 .functor XOR 1, L_0x55c0750832f0, o0x7ffa3a6e3198, C4<0>, C4<0>;
L_0x55c0750835e0 .functor AND 1, L_0x55c0750832f0, o0x7ffa3a6e3198, C4<1>, C4<1>; L_0x55c0750835e0 .functor AND 1, L_0x55c0750832f0, o0x7ffa3a6e3198, C4<1>, C4<1>;
v0x55c075082020_0 .net "A", 0 0, L_0x55c0750832f0; alias, 1 drivers v0x55c075082020_0 .net "A", 0 0, L_0x55c0750832f0; alias, 1 drivers
v0x55c0750820f0_0 .net "B", 0 0, o0x7ffa3a6e3198; alias, 0 drivers v0x55c0750820f0_0 .net "B", 0 0, o0x7ffa3a6e3198; alias, 0 drivers
v0x55c075082190_0 .net "C", 0 0, L_0x55c0750835e0; alias, 1 drivers v0x55c075082190_0 .net "C", 0 0, L_0x55c0750835e0; alias, 1 drivers
v0x55c075082260_0 .net "S", 0 0, L_0x55c0750834e0; alias, 1 drivers v0x55c075082260_0 .net "S", 0 0, L_0x55c0750834e0; alias, 1 drivers
S_0x55c07506bbf0 .scope module, "test3bitTest" "test3bitTest" 4 1; S_0x55c07506bbf0 .scope module, "test3bitTest" "test3bitTest" 4 1;
.timescale 0 0; .timescale 0 0;
v0x55c075083030_0 .var "r1", 2 0; v0x55c075083030_0 .var "r1", 2 0;
v0x55c075083120_0 .var "r2", 2 0; v0x55c075083120_0 .var "r2", 2 0;
v0x55c0750831f0_0 .net "w1", 3 0, v0x55c075082ef0_0; 1 drivers v0x55c0750831f0_0 .net "w1", 3 0, v0x55c075082ef0_0; 1 drivers
S_0x55c075082a80 .scope module, "uut" "Adder3Bit_behavioral" 4 6, 5 1 0, S_0x55c07506bbf0; S_0x55c075082a80 .scope module, "uut" "Adder3Bit_behavioral" 4 6, 5 1 0, S_0x55c07506bbf0;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 3 "A"; .port_info 0 /INPUT 3 "A";
.port_info 1 /INPUT 3 "B"; .port_info 1 /INPUT 3 "B";
.port_info 2 /OUTPUT 4 "C"; .port_info 2 /OUTPUT 4 "C";
v0x55c075082d10_0 .net "A", 2 0, v0x55c075083030_0; 1 drivers v0x55c075082d10_0 .net "A", 2 0, v0x55c075083030_0; 1 drivers
v0x55c075082e10_0 .net "B", 2 0, v0x55c075083120_0; 1 drivers v0x55c075082e10_0 .net "B", 2 0, v0x55c075083120_0; 1 drivers
v0x55c075082ef0_0 .var "C", 3 0; v0x55c075082ef0_0 .var "C", 3 0;
E_0x55c075064d90 .event edge, v0x55c075082e10_0, v0x55c075082d10_0; E_0x55c075064d90 .event edge, v0x55c075082e10_0, v0x55c075082d10_0;
.scope S_0x55c075082a80; .scope S_0x55c075082a80;
T_0 ; T_0 ;
%wait E_0x55c075064d90; %wait E_0x55c075064d90;
%load/vec4 v0x55c075082d10_0; %load/vec4 v0x55c075082d10_0;
%pad/u 4; %pad/u 4;
%load/vec4 v0x55c075082e10_0; %load/vec4 v0x55c075082e10_0;
%pad/u 4; %pad/u 4;
%sub; %sub;
%store/vec4 v0x55c075082ef0_0, 0, 4; %store/vec4 v0x55c075082ef0_0, 0, 4;
%jmp T_0; %jmp T_0;
.thread T_0, $push; .thread T_0, $push;
.scope S_0x55c07506bbf0; .scope S_0x55c07506bbf0;
T_1 ; T_1 ;
%vpi_call 4 13 "$dumpfile", "bit3.vcd" {0 0 0}; %vpi_call 4 13 "$dumpfile", "bit3.vcd" {0 0 0};
%vpi_call 4 14 "$dumpvars" {0 0 0}; %vpi_call 4 14 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3; %store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 7, 0, 3; %pushi/vec4 7, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3; %store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 1, 0, 3; %pushi/vec4 1, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3; %store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 6, 0, 3; %pushi/vec4 6, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3; %store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 2, 0, 3; %pushi/vec4 2, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3; %store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 5, 0, 3; %pushi/vec4 5, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3; %store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 3, 0, 3; %pushi/vec4 3, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3; %store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 4, 0, 3; %pushi/vec4 4, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3; %store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 4, 0, 3; %pushi/vec4 4, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3; %store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 3, 0, 3; %pushi/vec4 3, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3; %store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 5, 0, 3; %pushi/vec4 5, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3; %store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 2, 0, 3; %pushi/vec4 2, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3; %store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 6, 0, 3; %pushi/vec4 6, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3; %store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 1, 0, 3; %pushi/vec4 1, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3; %store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 7, 0, 3; %pushi/vec4 7, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3; %store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3; %store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3; %store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3; %store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 1, 0, 3; %pushi/vec4 1, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3; %store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3; %store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 2, 0, 3; %pushi/vec4 2, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3; %store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3; %store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 3, 0, 3; %pushi/vec4 3, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3; %store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3; %store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 4, 0, 3; %pushi/vec4 4, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3; %store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3; %store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 5, 0, 3; %pushi/vec4 5, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3; %store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3; %store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 6, 0, 3; %pushi/vec4 6, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3; %store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3; %store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 7, 0, 3; %pushi/vec4 7, 0, 3;
%store/vec4 v0x55c075083030_0, 0, 3; %store/vec4 v0x55c075083030_0, 0, 3;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x55c075083120_0, 0, 3; %store/vec4 v0x55c075083120_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%vpi_call 4 33 "$display", "Done" {0 0 0}; %vpi_call 4 33 "$display", "Done" {0 0 0};
%end; %end;
.thread T_1; .thread T_1;
# The file index is used to find the file name in the following table. # The file index is used to find the file name in the following table.
:file_names 6; :file_names 6;
"N/A"; "N/A";
"<interactive>"; "<interactive>";
"fulladder.v"; "fulladder.v";
"halfadder.v"; "halfadder.v";
"test3bitTest.v"; "test3bitTest.v";
"adder3bitBehavioral.v"; "adder3bitBehavioral.v";

20
gowin/bibp/bibp.gprj
View File

@ -1,10 +1,10 @@
<?xml version="1" encoding="UTF-8"?> <?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project> <!DOCTYPE gowin-fpga-project>
<Project> <Project>
<Template>FPGA</Template> <Template>FPGA</Template>
<Version>5</Version> <Version>5</Version>
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device> <Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
<FileList> <FileList>
<File path="src/bibp.v" type="file.verilog" enable="1"/> <File path="src/bibp.v" type="file.verilog" enable="1"/>
</FileList> </FileList>
</Project> </Project>

26
gowin/bibp/bibp.gprj.user
View File

@ -1,13 +1,13 @@
<?xml version="1" encoding="UTF-8"?> <?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData> <!DOCTYPE ProjectUserData>
<UserConfig> <UserConfig>
<Version>1.0</Version> <Version>1.0</Version>
<FlowState> <FlowState>
<Process ID="Synthesis" State="3"/> <Process ID="Synthesis" State="3"/>
<Process ID="Pnr" State="0"/> <Process ID="Pnr" State="0"/>
<Process ID="Gao" State="0"/> <Process ID="Gao" State="0"/>
<Process ID="Rtl_Gao" State="2"/> <Process ID="Rtl_Gao" State="2"/>
</FlowState> </FlowState>
<ResultFileList/> <ResultFileList/>
<Ui>000000ff00000001fd00000002000000000000018e000003e5fc0200000001fc00000063000003e50000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff00000000000000000000000300000ab00000027efc0100000001fc0000000000000ab0000000da00fffffffa000000010100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000009e00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000da00ffffff0000091a000003e500000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000bdffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c007301000001a5ffffffff0000000000000000</Ui> <Ui>000000ff00000001fd00000002000000000000018e000003e5fc0200000001fc00000063000003e50000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff00000000000000000000000300000ab00000027efc0100000001fc0000000000000ab0000000da00fffffffa000000010100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000009e00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000da00ffffff0000091a000003e500000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000bdffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c007301000001a5ffffffff0000000000000000</Ui>
</UserConfig> </UserConfig>

174
gowin/bibp/impl/bibp_process_config.json
View File

@ -1,88 +1,88 @@
{ {
"BACKGROUND_PROGRAMMING" : "off", "BACKGROUND_PROGRAMMING" : "off",
"COMPRESS" : false, "COMPRESS" : false,
"CPU" : false, "CPU" : false,
"CRC_CHECK" : true, "CRC_CHECK" : true,
"Clock_Route_Order" : 0, "Clock_Route_Order" : 0,
"Correct_Hold_Violation" : true, "Correct_Hold_Violation" : true,
"DONE" : false, "DONE" : false,
"DOWNLOAD_SPEED" : "default", "DOWNLOAD_SPEED" : "default",
"Disable_Insert_Pad" : false, "Disable_Insert_Pad" : false,
"ENABLE_CTP" : false, "ENABLE_CTP" : false,
"ENABLE_MERGE_MODE" : false, "ENABLE_MERGE_MODE" : false,
"ENCRYPTION_KEY" : false, "ENCRYPTION_KEY" : false,
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000", "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
"ERROR_DECTION_AND_CORRECTION" : false, "ERROR_DECTION_AND_CORRECTION" : false,
"ERROR_DECTION_ONLY" : false, "ERROR_DECTION_ONLY" : false,
"ERROR_INJECTION" : false, "ERROR_INJECTION" : false,
"EXTERNAL_MASTER_CONFIG_CLOCK" : false, "EXTERNAL_MASTER_CONFIG_CLOCK" : false,
"Enable_DSRM" : false, "Enable_DSRM" : false,
"FORMAT" : "binary", "FORMAT" : "binary",
"FREQUENCY_DIVIDER" : "", "FREQUENCY_DIVIDER" : "",
"Generate_Constraint_File_of_Ports" : false, "Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false, "Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false, "Generate_Plain_Text_Timing_Report" : false,
"Generate_Post_PNR_Simulation_Model_File" : false, "Generate_Post_PNR_Simulation_Model_File" : false,
"Generate_Post_Place_File" : false, "Generate_Post_Place_File" : false,
"Generate_SDF_File" : false, "Generate_SDF_File" : false,
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false, "Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
"Global_Freq" : "default", "Global_Freq" : "default",
"GwSyn_Loop_Limit" : 2000, "GwSyn_Loop_Limit" : 2000,
"HOTBOOT" : false, "HOTBOOT" : false,
"I2C" : false, "I2C" : false,
"I2C_SLAVE_ADDR" : "00", "I2C_SLAVE_ADDR" : "00",
"IncludePath" : [ "IncludePath" : [
], ],
"Incremental_Compile" : "", "Incremental_Compile" : "",
"Initialize_Primitives" : false, "Initialize_Primitives" : false,
"JTAG" : false, "JTAG" : false,
"MODE_IO" : false, "MODE_IO" : false,
"MSPI" : false, "MSPI" : false,
"MSPI_JUMP" : false, "MSPI_JUMP" : false,
"MULTIBOOT_ADDRESS_WIDTH" : "24", "MULTIBOOT_ADDRESS_WIDTH" : "24",
"MULTIBOOT_MODE" : "Normal", "MULTIBOOT_MODE" : "Normal",
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000", "MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
"MULTIJUMP_ADDRESS_WIDTH" : "24", "MULTIJUMP_ADDRESS_WIDTH" : "24",
"MULTIJUMP_MODE" : "Normal", "MULTIJUMP_MODE" : "Normal",
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000", "MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
"Multi_Boot" : true, "Multi_Boot" : true,
"OUTPUT_BASE_NAME" : "bibp", "OUTPUT_BASE_NAME" : "bibp",
"POWER_ON_RESET_MONITOR" : true, "POWER_ON_RESET_MONITOR" : true,
"PRINT_BSRAM_VALUE" : true, "PRINT_BSRAM_VALUE" : true,
"PROGRAM_DONE_BYPASS" : false, "PROGRAM_DONE_BYPASS" : false,
"PlaceInRegToIob" : true, "PlaceInRegToIob" : true,
"PlaceIoRegToIob" : true, "PlaceIoRegToIob" : true,
"PlaceOutRegToIob" : true, "PlaceOutRegToIob" : true,
"Place_Option" : "0", "Place_Option" : "0",
"Process_Configuration_Verion" : "1.0", "Process_Configuration_Verion" : "1.0",
"Promote_Physical_Constraint_Warning_to_Error" : true, "Promote_Physical_Constraint_Warning_to_Error" : true,
"READY" : false, "READY" : false,
"RECONFIG_N" : false, "RECONFIG_N" : false,
"Ram_RW_Check" : false, "Ram_RW_Check" : false,
"Replicate_Resources" : false, "Replicate_Resources" : false,
"Report_Auto-Placed_Io_Information" : false, "Report_Auto-Placed_Io_Information" : false,
"Route_Maxfan" : 23, "Route_Maxfan" : 23,
"Route_Option" : "0", "Route_Option" : "0",
"Run_Timing_Driven" : true, "Run_Timing_Driven" : true,
"SECURE_MODE" : false, "SECURE_MODE" : false,
"SECURITY_BIT" : true, "SECURITY_BIT" : true,
"SEU_HANDLER" : false, "SEU_HANDLER" : false,
"SEU_HANDLER_CHECKSUM" : false, "SEU_HANDLER_CHECKSUM" : false,
"SEU_HANDLER_MODE" : "auto", "SEU_HANDLER_MODE" : "auto",
"SSPI" : false, "SSPI" : false,
"STOP_SEU_HANDLER" : false, "STOP_SEU_HANDLER" : false,
"Show_All_Warnings" : false, "Show_All_Warnings" : false,
"Synthesize_tool" : "GowinSyn", "Synthesize_tool" : "GowinSyn",
"TclPre" : "", "TclPre" : "",
"TopModule" : "", "TopModule" : "",
"USERCODE" : "default", "USERCODE" : "default",
"Unused_Pin" : "As_input_tri_stated_with_pull_up", "Unused_Pin" : "As_input_tri_stated_with_pull_up",
"VCCAUX" : 3.3, "VCCAUX" : 3.3,
"VCCX" : "3.3", "VCCX" : "3.3",
"VHDL_Standard" : "VHDL_Std_1993", "VHDL_Standard" : "VHDL_Std_1993",
"Verilog_Standard" : "Vlg_Std_2001", "Verilog_Standard" : "Vlg_Std_2001",
"WAKE_UP" : "0", "WAKE_UP" : "0",
"show_all_warnings" : false, "show_all_warnings" : false,
"turn_off_bg" : false "turn_off_bg" : false
} }

28
gowin/bibp/impl/gwsynthesis/bibp.log
View File

@ -1,14 +1,14 @@
GowinSynthesis start GowinSynthesis start
Running parser ... Running parser ...
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v' Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v'
ERROR (EX3812) : 'buyruk' is not a constant("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":7) ERROR (EX3812) : 'buyruk' is not a constant("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":7)
ERROR (EX3812) : 'buyruk' is not a constant("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":8) ERROR (EX3812) : 'buyruk' is not a constant("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":8)
ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":12) ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":12)
ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":13) ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":13)
ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":14) ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":14)
ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":15) ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":15)
ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":16) ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":16)
ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":17) ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":17)
ERROR (EX3928) : Module 'bibp' is ignored due to previous errors("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":21) ERROR (EX3928) : Module 'bibp' is ignored due to previous errors("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":21)
Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v' ignored due to errors Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v' ignored due to errors
GowinSynthesis finish GowinSynthesis finish

38
gowin/bibp/impl/gwsynthesis/bibp.prj
View File

@ -1,19 +1,19 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project> <!DOCTYPE gowin-synthesis-project>
<Project> <Project>
<Version>beta</Version> <Version>beta</Version>
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/> <Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList> <FileList>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v" type="verilog"/> <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v" type="verilog"/>
</FileList> </FileList>
<OptionList> <OptionList>
<Option type="disable_insert_pad" value="0"/> <Option type="disable_insert_pad" value="0"/>
<Option type="global_freq" value="100.000"/> <Option type="global_freq" value="100.000"/>
<Option type="looplimit" value="2000"/> <Option type="looplimit" value="2000"/>
<Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\impl\gwsynthesis\bibp.vg"/> <Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\impl\gwsynthesis\bibp.vg"/>
<Option type="print_all_synthesis_warning" value="0"/> <Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="0"/> <Option type="ram_rw_check" value="0"/>
<Option type="verilog_language" value="verilog-2001"/> <Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/> <Option type="vhdl_language" value="vhdl-1993"/>
</OptionList> </OptionList>
</Project> </Project>

32
gowin/bibp/impl/temp/rtl_parser_arg.json
View File

@ -1,17 +1,17 @@
{ {
"Device" : "GW2A-18C", "Device" : "GW2A-18C",
"Files" : [ "Files" : [
{ {
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bibp/src/bibp.v", "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bibp/src/bibp.v",
"Type" : "verilog" "Type" : "verilog"
} }
], ],
"IncludePath" : [ "IncludePath" : [
], ],
"LoopLimit" : 2000, "LoopLimit" : 2000,
"ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bibp/impl/temp/rtl_parser.result", "ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bibp/impl/temp/rtl_parser.result",
"Top" : "", "Top" : "",
"VerilogStd" : "verilog_2001", "VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93" "VhdlStd" : "vhdl_93"
} }

40
gowin/bibp/src/bibp.v
View File

@ -1,21 +1,21 @@
module bibp #(parameter UZUNLUK = 8)( module bibp #(parameter UZUNLUK = 8)(
input [UZUNLUK + 2:0] buyruk, input [UZUNLUK + 2:0] buyruk,
output [UZUNLUK:0] sonuc output [UZUNLUK:0] sonuc
); );
localparam halfUZUNLUK = UZUNLUK / 2; localparam halfUZUNLUK = UZUNLUK / 2;
localparam v1 = buyruk[UZUNLUK + 2 - 1 : halfUZUNLUK]; localparam v1 = buyruk[UZUNLUK + 2 - 1 : halfUZUNLUK];
localparam v2 = buyruk[halfUZUNLUK - 1 : 0]; localparam v2 = buyruk[halfUZUNLUK - 1 : 0];
always@(*) begin always@(*) begin
case(buyruk[UZUNLUK + 2: UZUNLUK -1]) case(buyruk[UZUNLUK + 2: UZUNLUK -1])
3'b000: sonuc = v1 + v2; 3'b000: sonuc = v1 + v2;
3'b001: sonuc = v1 - v2; 3'b001: sonuc = v1 - v2;
3'b010: sonuc = v1 & v2; 3'b010: sonuc = v1 & v2;
3'b011: sonuc = v1 | v2; 3'b011: sonuc = v1 | v2;
3'b100: sonuc = v1 ^ v2; 3'b100: sonuc = v1 ^ v2;
default: sonuc = v1 + v2; default: sonuc = v1 + v2;
endcase endcase
end end
endmodule endmodule

28
gowin/fpga_project/fpga_project.gprj
View File

@ -1,14 +1,14 @@
<?xml version="1" encoding="UTF-8"?> <?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project> <!DOCTYPE gowin-fpga-project>
<Project> <Project>
<Template>FPGA</Template> <Template>FPGA</Template>
<Version>5</Version> <Version>5</Version>
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device> <Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
<FileList> <FileList>
<File path="src/bit3adder.v" type="file.verilog" enable="1"/> <File path="src/bit3adder.v" type="file.verilog" enable="1"/>
<File path="src/fulladder.v" type="file.verilog" enable="1"/> <File path="src/fulladder.v" type="file.verilog" enable="1"/>
<File path="src/halfadder.v" type="file.verilog" enable="1"/> <File path="src/halfadder.v" type="file.verilog" enable="1"/>
<File path="src/ledTest.v" type="file.verilog" enable="1"/> <File path="src/ledTest.v" type="file.verilog" enable="1"/>
<File path="src/fpga_project.cst" type="file.cst" enable="1"/> <File path="src/fpga_project.cst" type="file.cst" enable="1"/>
</FileList> </FileList>
</Project> </Project>

48
gowin/fpga_project/fpga_project.gprj.user
View File

@ -1,24 +1,24 @@
<?xml version="1" encoding="UTF-8"?> <?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData> <!DOCTYPE ProjectUserData>
<UserConfig> <UserConfig>
<Version>1.0</Version> <Version>1.0</Version>
<FlowState> <FlowState>
<Process ID="Synthesis" State="2"/> <Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="2"/> <Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/> <Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/> <Process ID="Rtl_Gao" State="2"/>
</FlowState> </FlowState>
<ResultFileList> <ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/fpga_project.vg"/> <ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/fpga_project.vg"/>
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/fpga_project.fs"/> <ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/fpga_project.fs"/>
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/fpga_project.pin.html"/> <ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/fpga_project.pin.html"/>
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/fpga_project.db"/> <ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/fpga_project.db"/>
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/fpga_project.power.html"/> <ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/fpga_project.power.html"/>
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/fpga_project.rpt.html"/> <ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/fpga_project.rpt.html"/>
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/fpga_project.timing_paths"/> <ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/fpga_project.timing_paths"/>
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/fpga_project.tr.html"/> <ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/fpga_project.tr.html"/>
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/fpga_project_syn.rpt.html"/> <ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/fpga_project_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/fpga_project_syn_rsc.xml"/> <ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/fpga_project_syn_rsc.xml"/>
</ResultFileList> </ResultFileList>
<Ui>000000ff00000001fd00000002000000000000018e0000051efc0200000001fc000000630000051e0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff00000000000000000000000300000ab000000145fc0100000001fc0000000000000ab0000000da00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000009e00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000da00ffffff0000091a0000051e00000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000bdffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c007301000001a5ffffffff0000000000000000</Ui> <Ui>000000ff00000001fd00000002000000000000018e0000051efc0200000001fc000000630000051e0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff00000000000000000000000300000ab000000145fc0100000001fc0000000000000ab0000000da00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000009e00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000da00ffffff0000091a0000051e00000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000bdffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c007301000001a5ffffffff0000000000000000</Ui>
</UserConfig> </UserConfig>

174
gowin/fpga_project/impl/fpga_project_process_config.json
View File

@ -1,88 +1,88 @@
{ {
"BACKGROUND_PROGRAMMING" : "off", "BACKGROUND_PROGRAMMING" : "off",
"COMPRESS" : false, "COMPRESS" : false,
"CPU" : false, "CPU" : false,
"CRC_CHECK" : true, "CRC_CHECK" : true,
"Clock_Route_Order" : 0, "Clock_Route_Order" : 0,
"Correct_Hold_Violation" : true, "Correct_Hold_Violation" : true,
"DONE" : false, "DONE" : false,
"DOWNLOAD_SPEED" : "default", "DOWNLOAD_SPEED" : "default",
"Disable_Insert_Pad" : false, "Disable_Insert_Pad" : false,
"ENABLE_CTP" : false, "ENABLE_CTP" : false,
"ENABLE_MERGE_MODE" : false, "ENABLE_MERGE_MODE" : false,
"ENCRYPTION_KEY" : false, "ENCRYPTION_KEY" : false,
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000", "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
"ERROR_DECTION_AND_CORRECTION" : false, "ERROR_DECTION_AND_CORRECTION" : false,
"ERROR_DECTION_ONLY" : false, "ERROR_DECTION_ONLY" : false,
"ERROR_INJECTION" : false, "ERROR_INJECTION" : false,
"EXTERNAL_MASTER_CONFIG_CLOCK" : false, "EXTERNAL_MASTER_CONFIG_CLOCK" : false,
"Enable_DSRM" : false, "Enable_DSRM" : false,
"FORMAT" : "binary", "FORMAT" : "binary",
"FREQUENCY_DIVIDER" : "1", "FREQUENCY_DIVIDER" : "1",
"Generate_Constraint_File_of_Ports" : false, "Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false, "Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false, "Generate_Plain_Text_Timing_Report" : false,
"Generate_Post_PNR_Simulation_Model_File" : false, "Generate_Post_PNR_Simulation_Model_File" : false,
"Generate_Post_Place_File" : false, "Generate_Post_Place_File" : false,
"Generate_SDF_File" : false, "Generate_SDF_File" : false,
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false, "Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
"Global_Freq" : "default", "Global_Freq" : "default",
"GwSyn_Loop_Limit" : 2000, "GwSyn_Loop_Limit" : 2000,
"HOTBOOT" : false, "HOTBOOT" : false,
"I2C" : false, "I2C" : false,
"I2C_SLAVE_ADDR" : "00", "I2C_SLAVE_ADDR" : "00",
"IncludePath" : [ "IncludePath" : [
], ],
"Incremental_Compile" : "", "Incremental_Compile" : "",
"Initialize_Primitives" : false, "Initialize_Primitives" : false,
"JTAG" : false, "JTAG" : false,
"MODE_IO" : false, "MODE_IO" : false,
"MSPI" : false, "MSPI" : false,
"MSPI_JUMP" : false, "MSPI_JUMP" : false,
"MULTIBOOT_ADDRESS_WIDTH" : "24", "MULTIBOOT_ADDRESS_WIDTH" : "24",
"MULTIBOOT_MODE" : "Normal", "MULTIBOOT_MODE" : "Normal",
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000", "MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
"MULTIJUMP_ADDRESS_WIDTH" : "24", "MULTIJUMP_ADDRESS_WIDTH" : "24",
"MULTIJUMP_MODE" : "Normal", "MULTIJUMP_MODE" : "Normal",
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000", "MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
"Multi_Boot" : true, "Multi_Boot" : true,
"OUTPUT_BASE_NAME" : "fpga_project", "OUTPUT_BASE_NAME" : "fpga_project",
"POWER_ON_RESET_MONITOR" : true, "POWER_ON_RESET_MONITOR" : true,
"PRINT_BSRAM_VALUE" : true, "PRINT_BSRAM_VALUE" : true,
"PROGRAM_DONE_BYPASS" : false, "PROGRAM_DONE_BYPASS" : false,
"PlaceInRegToIob" : true, "PlaceInRegToIob" : true,
"PlaceIoRegToIob" : true, "PlaceIoRegToIob" : true,
"PlaceOutRegToIob" : true, "PlaceOutRegToIob" : true,
"Place_Option" : "0", "Place_Option" : "0",
"Process_Configuration_Verion" : "1.0", "Process_Configuration_Verion" : "1.0",
"Promote_Physical_Constraint_Warning_to_Error" : true, "Promote_Physical_Constraint_Warning_to_Error" : true,
"READY" : false, "READY" : false,
"RECONFIG_N" : false, "RECONFIG_N" : false,
"Ram_RW_Check" : false, "Ram_RW_Check" : false,
"Replicate_Resources" : false, "Replicate_Resources" : false,
"Report_Auto-Placed_Io_Information" : false, "Report_Auto-Placed_Io_Information" : false,
"Route_Maxfan" : 23, "Route_Maxfan" : 23,
"Route_Option" : "0", "Route_Option" : "0",
"Run_Timing_Driven" : true, "Run_Timing_Driven" : true,
"SECURE_MODE" : false, "SECURE_MODE" : false,
"SECURITY_BIT" : true, "SECURITY_BIT" : true,
"SEU_HANDLER" : false, "SEU_HANDLER" : false,
"SEU_HANDLER_CHECKSUM" : false, "SEU_HANDLER_CHECKSUM" : false,
"SEU_HANDLER_MODE" : "auto", "SEU_HANDLER_MODE" : "auto",
"SSPI" : false, "SSPI" : false,
"STOP_SEU_HANDLER" : false, "STOP_SEU_HANDLER" : false,
"Show_All_Warnings" : false, "Show_All_Warnings" : false,
"Synthesize_tool" : "GowinSyn", "Synthesize_tool" : "GowinSyn",
"TclPre" : "", "TclPre" : "",
"TopModule" : "", "TopModule" : "",
"USERCODE" : "default", "USERCODE" : "default",
"Unused_Pin" : "As_input_tri_stated_with_pull_up", "Unused_Pin" : "As_input_tri_stated_with_pull_up",
"VCCAUX" : 3.3, "VCCAUX" : 3.3,
"VCCX" : "3.3", "VCCX" : "3.3",
"VHDL_Standard" : "VHDL_Std_1993", "VHDL_Standard" : "VHDL_Std_1993",
"Verilog_Standard" : "Vlg_Std_2001", "Verilog_Standard" : "Vlg_Std_2001",
"WAKE_UP" : "0", "WAKE_UP" : "0",
"show_all_warnings" : false, "show_all_warnings" : false,
"turn_off_bg" : false "turn_off_bg" : false
} }

76
gowin/fpga_project/impl/gwsynthesis/fpga_project.log
View File

@ -1,38 +1,38 @@
GowinSynthesis start GowinSynthesis start
Running parser ... Running parser ...
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v' Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v' Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v' Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v'
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v' Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v'
Compiling module 'ledTest'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v":1) Compiling module 'ledTest'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v":1)
Compiling module 'bit3adder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":1) Compiling module 'bit3adder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":1)
Compiling module 'halfadder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v":1) Compiling module 'halfadder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v":1)
Compiling module 'fulladder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":1) Compiling module 'fulladder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":1)
NOTE (EX0101) : Current top module is "ledTest" NOTE (EX0101) : Current top module is "ledTest"
[5%] Running netlist conversion ... [5%] Running netlist conversion ...
Running device independent optimization ... Running device independent optimization ...
[10%] Optimizing Phase 0 completed [10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed [15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed [25%] Optimizing Phase 2 completed
Running inference ... Running inference ...
[30%] Inferring Phase 0 completed [30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed [40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed [50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed [55%] Inferring Phase 3 completed
Running technical mapping ... Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed [60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed [65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed [75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed [80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed [90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "bit3adder" instantiated to "adder" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v":12) WARN (NL0002) : The module "bit3adder" instantiated to "adder" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v":12)
WARN (NL0002) : The module "fulladder" instantiated to "fa0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":10) WARN (NL0002) : The module "fulladder" instantiated to "fa0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":10)
WARN (NL0002) : The module "halfadder" instantiated to "ha1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":8) WARN (NL0002) : The module "halfadder" instantiated to "ha1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "ha2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":9) WARN (NL0002) : The module "halfadder" instantiated to "ha2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "fa1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":11) WARN (NL0002) : The module "fulladder" instantiated to "fa1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "ha1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":8) WARN (NL0002) : The module "halfadder" instantiated to "ha1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "ha2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":9) WARN (NL0002) : The module "halfadder" instantiated to "ha2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v":9)
WARN (NL0002) : The module "halfadder" instantiated to "ha0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":9) WARN (NL0002) : The module "halfadder" instantiated to "ha0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v":9)
[95%] Generate netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg" completed [95%] Generate netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg" completed
[100%] Generate report file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project_syn.rpt.html" completed [100%] Generate report file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project_syn.rpt.html" completed
GowinSynthesis finish GowinSynthesis finish

44
gowin/fpga_project/impl/gwsynthesis/fpga_project.prj
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@ -1,22 +1,22 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project> <!DOCTYPE gowin-synthesis-project>
<Project> <Project>
<Version>beta</Version> <Version>beta</Version>
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/> <Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList> <FileList>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v" type="verilog"/> <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v" type="verilog"/> <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v" type="verilog"/> <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v" type="verilog"/>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v" type="verilog"/> <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v" type="verilog"/>
</FileList> </FileList>
<OptionList> <OptionList>
<Option type="disable_insert_pad" value="0"/> <Option type="disable_insert_pad" value="0"/>
<Option type="global_freq" value="100.000"/> <Option type="global_freq" value="100.000"/>
<Option type="looplimit" value="2000"/> <Option type="looplimit" value="2000"/>
<Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg"/> <Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg"/>
<Option type="print_all_synthesis_warning" value="0"/> <Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="0"/> <Option type="ram_rw_check" value="0"/>
<Option type="verilog_language" value="verilog-2001"/> <Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/> <Option type="vhdl_language" value="vhdl-1993"/>
</OptionList> </OptionList>
</Project> </Project>

100
gowin/fpga_project/impl/gwsynthesis/fpga_project.vg
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@ -1,50 +1,50 @@
// //
//Written by GowinSynthesis //Written by GowinSynthesis
//Tool Version "V1.9.9.03 Education (64-bit)" //Tool Version "V1.9.9.03 Education (64-bit)"
//Fri Jul 5 01:47:50 2024 //Fri Jul 5 01:47:50 2024
//Source file index table: //Source file index table:
//file0 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v" //file0 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v"
//file1 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v" //file1 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v"
//file2 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v" //file2 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v"
//file3 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v" //file3 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v"
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340
gowin/fpga_project/impl/gwsynthesis/fpga_project_syn.rpt.html
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@ -1,170 +1,170 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html> <html>
<head> <head>
<title>synthesis Report</title> <title>synthesis Report</title>
<style type="text/css"> <style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; } body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper{ width: 100%; } div#main_wrapper{ width: 100%; }
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div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; } div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; } div#catalog ul { list-style-type: none; }
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</head> </head>
<body> <body>
<div id="main_wrapper"> <div id="main_wrapper">
<div id="catalog_wrapper"> <div id="catalog_wrapper">
<div id="catalog"> <div id="catalog">
<ul> <ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li> <li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li> <li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a> <li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul> <ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li> <li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li> <li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
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</li> </li>
</ul> </ul>
</div><!-- catalog --> </div><!-- catalog -->
</div><!-- catalog_wrapper --> </div><!-- catalog_wrapper -->
<div id="content"> <div id="content">
<h1><a name="about">Synthesis Messages</a></h1> <h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table"> <table class="summary_table">
<tr> <tr>
<td class="label">Report Title</td> <td class="label">Report Title</td>
<td>GowinSynthesis Report</td> <td>GowinSynthesis Report</td>
</tr> </tr>
<tr> <tr>
<td class="label">Design File</td> <td class="label">Design File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v<br> <td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\bit3adder.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v<br> \\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fulladder.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v<br> \\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\halfadder.v<br>
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v<br> \\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\ledTest.v<br>
</td> </td>
</tr> </tr>
<tr> <tr>
<td class="label">GowinSynthesis Constraints File</td> <td class="label">GowinSynthesis Constraints File</td>
<td>---</td> <td>---</td>
</tr> </tr>
<tr> <tr>
<td class="label">Tool Version</td> <td class="label">Tool Version</td>
<td>V1.9.9.03 Education (64-bit)</td> <td>V1.9.9.03 Education (64-bit)</td>
</tr> </tr>
<tr> <tr>
<td class="label">Part Number</td> <td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td> <td>GW2A-LV18PG256C8/I7</td>
</tr> </tr>
<tr> <tr>
<td class="label">Device</td> <td class="label">Device</td>
<td>GW2A-18</td> <td>GW2A-18</td>
</tr> </tr>
<tr> <tr>
<td class="label">Device Version</td> <td class="label">Device Version</td>
<td>C</td> <td>C</td>
</tr> </tr>
<tr> <tr>
<td class="label">Created Time</td> <td class="label">Created Time</td>
<td>Fri Jul 5 01:47:50 2024 <td>Fri Jul 5 01:47:50 2024
</td> </td>
</tr> </tr>
<tr> <tr>
<td class="label">Legal Announcement</td> <td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td> <td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr> </tr>
</table> </table>
<h1><a name="summary">Synthesis Details</a></h1> <h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table"> <table class="summary_table">
<tr> <tr>
<td class="label">Top Level Module</td> <td class="label">Top Level Module</td>
<td>ledTest</td> <td>ledTest</td>
</tr> </tr>
<tr> <tr>
<td class="label">Synthesis Process</td> <td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.256s, Peak memory usage = 438.125MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 438.125MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 438.125MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.381s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 438.125MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 438.125MB<br/></td> <td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.256s, Peak memory usage = 438.125MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 438.125MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 438.125MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.381s, Peak memory usage = 438.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 438.125MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 438.125MB<br/></td>
</tr> </tr>
<tr> <tr>
<td class="label">Total Time and Memory Usage</td> <td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 0.201s, Elapsed time = 0h 0m 0.729s, Peak memory usage = 438.125MB</td> <td>CPU time = 0h 0m 0.201s, Elapsed time = 0h 0m 0.729s, Peak memory usage = 438.125MB</td>
</tr> </tr>
</table> </table>
<h1><a name="resource">Resource</a></h1> <h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2> <h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table"> <table class="summary_table">
<tr> <tr>
<td class="label"><b>Resource</b></td> <td class="label"><b>Resource</b></td>
<td><b>Usage</b></td> <td><b>Usage</b></td>
</tr> </tr>
<tr> <tr>
<td class="label"><b>I/O Port </b></td> <td class="label"><b>I/O Port </b></td>
<td>7</td> <td>7</td>
</tr> </tr>
<tr> <tr>
<td class="label"><b>I/O Buf </b></td> <td class="label"><b>I/O Buf </b></td>
<td>7</td> <td>7</td>
</tr> </tr>
<tr> <tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td> <td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>4</td> <td>4</td>
</tr> </tr>
<tr> <tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td> <td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>3</td> <td>3</td>
</tr> </tr>
<tr> <tr>
<td class="label"><b>LUT </b></td> <td class="label"><b>LUT </b></td>
<td>2</td> <td>2</td>
</tr> </tr>
<tr> <tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td> <td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>2</td> <td>2</td>
</tr> </tr>
</table> </table>
<h2><a name="utilization">Resource Utilization Summary</a></h2> <h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table"> <table class="summary_table">
<tr> <tr>
<td class="label"><b>Resource</b></td> <td class="label"><b>Resource</b></td>
<td><b>Usage</b></td> <td><b>Usage</b></td>
<td><b>Utilization</b></td> <td><b>Utilization</b></td>
</tr> </tr>
<tr> <tr>
<td class="label">Logic</td> <td class="label">Logic</td>
<td>2(2 LUT, 0 ALU) / 20736</td> <td>2(2 LUT, 0 ALU) / 20736</td>
<td><1%</td> <td><1%</td>
</tr> </tr>
<tr> <tr>
<td class="label">Register</td> <td class="label">Register</td>
<td>0 / 16173</td> <td>0 / 16173</td>
<td>0%</td> <td>0%</td>
</tr> </tr>
<tr> <tr>
<td class="label">&nbsp&nbsp--Register as Latch</td> <td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 16173</td> <td>0 / 16173</td>
<td>0%</td> <td>0%</td>
</tr> </tr>
<tr> <tr>
<td class="label">&nbsp&nbsp--Register as FF</td> <td class="label">&nbsp&nbsp--Register as FF</td>
<td>0 / 16173</td> <td>0 / 16173</td>
<td>0%</td> <td>0%</td>
</tr> </tr>
<tr> <tr>
<td class="label">BSRAM</td> <td class="label">BSRAM</td>
<td>0 / 46</td> <td>0 / 46</td>
<td>0%</td> <td>0%</td>
</tr> </tr>
</table> </table>
</div><!-- content --> </div><!-- content -->
</div><!-- main_wrapper --> </div><!-- main_wrapper -->
</body> </body>
</html> </html>

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gowin/fpga_project/impl/gwsynthesis/fpga_project_syn_resource.html
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html> <html>
<head> <head>
<title>Hierarchy Module Resource</title> <title>Hierarchy Module Resource</title>
<style type="text/css"> <style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; } body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
div#main_wrapper{ width: 100%; } div#main_wrapper{ width: 100%; }
h1 {text-align: center; } h1 {text-align: center; }
h1 {margin-top: 36px; } h1 {margin-top: 36px; }
table, th, td { border: 1px solid #aaa; } table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; } table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { align = "center"; padding: 5px 2px 5px 5px; } th, td { align = "center"; padding: 5px 2px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; } th { color: #fff; font-weight: bold; background-color: #0084ff; }
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; } table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
</style> </style>
</head> </head>
<body> <body>
<div id="main_wrapper"> <div id="main_wrapper">
<div id="content"> <div id="content">
<h1>Hierarchy Module Resource</h1> <h1>Hierarchy Module Resource</h1>
<table> <table>
<tr> <tr>
<th class="label">MODULE NAME</th> <th class="label">MODULE NAME</th>
<th class="label">REG NUMBER</th> <th class="label">REG NUMBER</th>
<th class="label">ALU NUMBER</th> <th class="label">ALU NUMBER</th>
<th class="label">LUT NUMBER</th> <th class="label">LUT NUMBER</th>
<th class="label">DSP NUMBER</th> <th class="label">DSP NUMBER</th>
<th class="label">BSRAM NUMBER</th> <th class="label">BSRAM NUMBER</th>
<th class="label">SSRAM NUMBER</th> <th class="label">SSRAM NUMBER</th>
<th class="label">ROM16 NUMBER</th> <th class="label">ROM16 NUMBER</th>
</tr> </tr>
<tr> <tr>
<td class="label">ledTest (//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v)</td> <td class="label">ledTest (//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v)</td>
<td align = "center">-</td> <td align = "center">-</td>
<td align = "center">-</td> <td align = "center">-</td>
<td align = "center">2</td> <td align = "center">2</td>
<td align = "center">-</td> <td align = "center">-</td>
<td align = "center">-</td> <td align = "center">-</td>
<td align = "center">-</td> <td align = "center">-</td>
<td align = "center">-</td> <td align = "center">-</td>
</tr> </tr>
</table> </table>
</div><!-- content --> </div><!-- content -->
</div><!-- main_wrapper --> </div><!-- main_wrapper -->
</body> </body>
</html> </html>

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gowin/fpga_project/impl/gwsynthesis/fpga_project_syn_rsc.xml
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<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<Module name="ledTest" Lut="2" T_Lut="2(2)"/> <Module name="ledTest" Lut="2" T_Lut="2(2)"/>

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gowin/fpga_project/impl/pnr/cmd.do
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-d \\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg -d \\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg
-p GW2A-18C-PBGA256-8 -p GW2A-18C-PBGA256-8
-pn GW2A-LV18PG256C8/I7 -pn GW2A-LV18PG256C8/I7
-cst \\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fpga_project.cst -cst \\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fpga_project.cst
-cfg \\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\device.cfg -cfg \\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\device.cfg
-bit -bit
-tr -tr
-ph -ph
-timing -timing
-cst_error -cst_error
-correct_hold 1 -correct_hold 1
-route_maxfan 23 -route_maxfan 23
-global_freq 100.000 -global_freq 100.000

42
gowin/fpga_project/impl/pnr/device.cfg
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@ -1,21 +1,21 @@
set JTAG regular_io = false set JTAG regular_io = false
set SSPI regular_io = false set SSPI regular_io = false
set MSPI regular_io = false set MSPI regular_io = false
set READY regular_io = false set READY regular_io = false
set DONE regular_io = false set DONE regular_io = false
set I2C regular_io = false set I2C regular_io = false
set RECONFIG_N regular_io = false set RECONFIG_N regular_io = false
set CRC_check = true set CRC_check = true
set compress = false set compress = false
set encryption = false set encryption = false
set security_bit_enable = true set security_bit_enable = true
set bsram_init_fuse_print = true set bsram_init_fuse_print = true
set background_programming = off set background_programming = off
set secure_mode = false set secure_mode = false
set program_done_bypass = false set program_done_bypass = false
set wake_up = 0 set wake_up = 0
set format = binary set format = binary
set power_on_reset_monitor = true set power_on_reset_monitor = true
set multiboot_spi_flash_address = 0x00000000 set multiboot_spi_flash_address = 0x00000000
set vccx = 3.3 set vccx = 3.3
set unused_pin = default set unused_pin = default

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gowin/fpga_project/impl/pnr/fpga_project.fs
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gowin/fpga_project/impl/pnr/fpga_project.log
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Reading netlist file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg" Reading netlist file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg"
Parsing netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg" completed Parsing netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg" completed
Processing netlist completed Processing netlist completed
Reading constraint file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fpga_project.cst" Reading constraint file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fpga_project.cst"
Physical Constraint parsed completed Physical Constraint parsed completed
Running placement...... Running placement......
[10%] Placement Phase 0 completed [10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed [20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed [30%] Placement Phase 2 completed
[50%] Placement Phase 3 completed [50%] Placement Phase 3 completed
Running routing...... Running routing......
[60%] Routing Phase 0 completed [60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed [70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed [80%] Routing Phase 2 completed
[90%] Routing Phase 3 completed [90%] Routing Phase 3 completed
Running timing analysis...... Running timing analysis......
[95%] Timing analysis completed [95%] Timing analysis completed
Placement and routing completed Placement and routing completed
Bitstream generation in progress...... Bitstream generation in progress......
Bitstream generation completed Bitstream generation completed
Running power analysis...... Running power analysis......
[100%] Power analysis completed [100%] Power analysis completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.power.html" completed Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.power.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.pin.html" completed Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.pin.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.rpt.html" completed Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.rpt.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.rpt.txt" completed Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.rpt.txt" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.tr.html" completed Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.tr.html" completed
Fri Jul 5 01:48:07 2024 Fri Jul 5 01:48:07 2024

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gowin/fpga_project/impl/pnr/fpga_project.power.html
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html> <html>
<head> <head>
<title>Power Analysis Report</title> <title>Power Analysis Report</title>
<style type="text/css"> <style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; } body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper { width: 100%; } div#main_wrapper { width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; } div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; } div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; } div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; } div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; } div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; } div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; } div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; } hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; } h1, h3 { text-align: center; }
h1 {margin-top: 50px; } h1 {margin-top: 50px; }
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table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; } table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; } th, td { padding: 5px 5px 5px 5px; }
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table.detail_table th.label { min-width: 8%; width: 8%; } table.detail_table th.label { min-width: 8%; width: 8%; }
</style> </style>
</head> </head>
<body> <body>
<div id="main_wrapper"> <div id="main_wrapper">
<div id="catalog_wrapper"> <div id="catalog_wrapper">
<div id="catalog"> <div id="catalog">
<ul> <ul>
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a> <li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
<ul> <ul>
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li> <li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
</ul> </ul>
</li> </li>
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a> <li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
<ul> <ul>
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li> <li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li> <li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li> <li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
</ul> </ul>
</li> </li>
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a> <li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
<ul> <ul>
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li> <li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li> <li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li> <li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
</ul> </ul>
</li> </li>
</ul> </ul>
</div><!-- catalog --> </div><!-- catalog -->
</div><!-- catalog_wrapper --> </div><!-- catalog_wrapper -->
<div id="content"> <div id="content">
<h1><a name="Message">Power Messages</a></h1> <h1><a name="Message">Power Messages</a></h1>
<table class="summary_table"> <table class="summary_table">
<tr> <tr>
<td class="label">Report Title</td> <td class="label">Report Title</td>
<td>Power Analysis Report</td> <td>Power Analysis Report</td>
</tr> </tr>
<tr> <tr>
<td class="label">Design File</td> <td class="label">Design File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg</td> <td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg</td>
</tr> </tr>
<tr> <tr>
<td class="label">Physical Constraints File</td> <td class="label">Physical Constraints File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fpga_project.cst</td> <td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fpga_project.cst</td>
</tr> </tr>
<tr> <tr>
<td class="label">Timing Constraints File</td> <td class="label">Timing Constraints File</td>
<td>---</td> <td>---</td>
</tr> </tr>
<tr> <tr>
<td class="label">Tool Version</td> <td class="label">Tool Version</td>
<td>V1.9.9.03 Education (64-bit)</td> <td>V1.9.9.03 Education (64-bit)</td>
</tr> </tr>
<tr> <tr>
<td class="label">Part Number</td> <td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td> <td>GW2A-LV18PG256C8/I7</td>
</tr> </tr>
<tr> <tr>
<td class="label">Device</td> <td class="label">Device</td>
<td>GW2A-18</td> <td>GW2A-18</td>
</tr> </tr>
<tr> <tr>
<td class="label">Device Version</td> <td class="label">Device Version</td>
<td>C</td> <td>C</td>
</tr> </tr>
<tr> <tr>
<td class="label">Created Time</td> <td class="label">Created Time</td>
<td>Fri Jul 5 01:48:01 2024 <td>Fri Jul 5 01:48:01 2024
</td> </td>
</tr> </tr>
<tr> <tr>
<td class="label">Legal Announcement</td> <td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td> <td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr> </tr>
</table> </table>
<h2><a name="Configure_Info">Configure Information:</a></h2> <h2><a name="Configure_Info">Configure Information:</a></h2>
<table class="summary_table"> <table class="summary_table">
<tr> <tr>
<td class="label">Grade</td> <td class="label">Grade</td>
<td>Commercial</td> <td>Commercial</td>
</tr> </tr>
<tr> <tr>
<td class="label">Process</td> <td class="label">Process</td>
<td>Typical</td> <td>Typical</td>
</tr> </tr>
<tr> <tr>
<td class="label">Ambient Temperature</td> <td class="label">Ambient Temperature</td>
<td>25.000 <td>25.000
</tr> </tr>
<tr> <tr>
<td class="label">Use Custom Theta JA</td> <td class="label">Use Custom Theta JA</td>
<td>false</td> <td>false</td>
</tr> </tr>
<tr> <tr>
<td class="label">Heat Sink</td> <td class="label">Heat Sink</td>
<td>None</td> <td>None</td>
</tr> </tr>
<tr> <tr>
<td class="label">Air Flow</td> <td class="label">Air Flow</td>
<td>LFM_0</td> <td>LFM_0</td>
</tr> </tr>
<tr> <tr>
<td class="label">Use Custom Theta SA</td> <td class="label">Use Custom Theta SA</td>
<td>false</td> <td>false</td>
</tr> </tr>
<tr> <tr>
<td class="label">Board Thermal Model</td> <td class="label">Board Thermal Model</td>
<td>None</td> <td>None</td>
</tr> </tr>
<tr> <tr>
<td class="label">Use Custom Theta JB</td> <td class="label">Use Custom Theta JB</td>
<td>false</td> <td>false</td>
</tr> </tr>
<tr> <tr>
<td class="label">Related Vcd File</td> <td class="label">Related Vcd File</td>
<td></td> <td></td>
</tr> </tr>
<tr> <tr>
<td class="label">Related Saif File</td> <td class="label">Related Saif File</td>
<td></td> <td></td>
</tr> </tr>
<tr> <tr>
<td class="label">Filter Glitches</td> <td class="label">Filter Glitches</td>
<td>false</td> <td>false</td>
</tr> </tr>
<tr> <tr>
<td class="label">Default IO Toggle Rate</td> <td class="label">Default IO Toggle Rate</td>
<td>0.125</td> <td>0.125</td>
</tr> </tr>
<tr> <tr>
<td class="label">Default Remain Toggle Rate</td> <td class="label">Default Remain Toggle Rate</td>
<td>0.125</td> <td>0.125</td>
</tr> </tr>
</table> </table>
<h1><a name="Summary">Power Summary</a></h1> <h1><a name="Summary">Power Summary</a></h1>
<h2><a name="Power_Info">Power Information:</a></h2> <h2><a name="Power_Info">Power Information:</a></h2>
<table class="summary_table"> <table class="summary_table">
<tr> <tr>
<td class="label">Total Power (mW)</td> <td class="label">Total Power (mW)</td>
<td>121.872</td> <td>121.872</td>
</tr> </tr>
<tr> <tr>
<td class="label">Quiescent Power (mW)</td> <td class="label">Quiescent Power (mW)</td>
<td>120.982</td> <td>120.982</td>
</tr> </tr>
<tr> <tr>
<td class="label">Dynamic Power (mW)</td> <td class="label">Dynamic Power (mW)</td>
<td>0.890</td> <td>0.890</td>
</tr> </tr>
</table> </table>
<h2><a name="Thermal_Info">Thermal Information:</a></h2> <h2><a name="Thermal_Info">Thermal Information:</a></h2>
<table class="summary_table"> <table class="summary_table">
<tr> <tr>
<td class="label">Junction Temperature</td> <td class="label">Junction Temperature</td>
<td>28.902</td> <td>28.902</td>
</tr> </tr>
<tr> <tr>
<td class="label">Theta JA</td> <td class="label">Theta JA</td>
<td>32.020</td> <td>32.020</td>
</tr> </tr>
<tr> <tr>
<td class="label">Max Allowed Ambient Temperature</td> <td class="label">Max Allowed Ambient Temperature</td>
<td>81.098</td> <td>81.098</td>
</tr> </tr>
</table> </table>
<h2><a name="Supply_Summary">Supply Information:</a></h2> <h2><a name="Supply_Summary">Supply Information:</a></h2>
<table class="summary_table"> <table class="summary_table">
<tr> <tr>
<th class="label">Voltage Source</th> <th class="label">Voltage Source</th>
<th class="label">Voltage</th> <th class="label">Voltage</th>
<th class="label">Dynamic Current(mA)</th> <th class="label">Dynamic Current(mA)</th>
<th class="label">Quiescent Current(mA)</th> <th class="label">Quiescent Current(mA)</th>
<th class="label">Power(mW)</th> <th class="label">Power(mW)</th>
</tr> </tr>
<tr> <tr>
<td>VCC</td> <td>VCC</td>
<td>1.000</td> <td>1.000</td>
<td>0.158</td> <td>0.158</td>
<td>69.996</td> <td>69.996</td>
<td>70.154</td> <td>70.154</td>
</tr> </tr>
<tr> <tr>
<td>VCCX</td> <td>VCCX</td>
<td>3.300</td> <td>3.300</td>
<td>0.158</td> <td>0.158</td>
<td>15.000</td> <td>15.000</td>
<td>50.020</td> <td>50.020</td>
</tr> </tr>
<tr> <tr>
<td>VCCIO12</td> <td>VCCIO12</td>
<td>1.200</td> <td>1.200</td>
<td>0.118</td> <td>0.118</td>
<td>0.429</td> <td>0.429</td>
<td>0.656</td> <td>0.656</td>
</tr> </tr>
<tr> <tr>
<td>VCCIO18</td> <td>VCCIO18</td>
<td>1.800</td> <td>1.800</td>
<td>0.039</td> <td>0.039</td>
<td>0.540</td> <td>0.540</td>
<td>1.042</td> <td>1.042</td>
</tr> </tr>
</table> </table>
<h1><a name="Detail">Power Details</a></h1> <h1><a name="Detail">Power Details</a></h1>
<h2><a name="By_Block_Type">Power By Block Type:</a></h2> <h2><a name="By_Block_Type">Power By Block Type:</a></h2>
<table class="detail_table"> <table class="detail_table">
<tr> <tr>
<th class="label">Block Type</th> <th class="label">Block Type</th>
<th class="label">Total Power(mW)</th> <th class="label">Total Power(mW)</th>
<th class="label">Static Power(mW)</th> <th class="label">Static Power(mW)</th>
<th class="label">Average Toggle Rate(millions of transitions/sec)</th> <th class="label">Average Toggle Rate(millions of transitions/sec)</th>
</tr> </tr>
<tr> <tr>
<td>IO</td> <td>IO</td>
<td>3.178 <td>3.178
<td>2.288 <td>2.288
<td>7.143 <td>7.143
</tr> </tr>
</table> </table>
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2> <h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
<table class="detail_table"> <table class="detail_table">
<tr> <tr>
<th class="label">Hierarchy Entity</th> <th class="label">Hierarchy Entity</th>
<th class="label">Total Power(mW)</th> <th class="label">Total Power(mW)</th>
<th class="label">Block Dynamic Power(mW)</th> <th class="label">Block Dynamic Power(mW)</th>
</tr> </tr>
<tr> <tr>
<td>ledTest</td> <td>ledTest</td>
<td>0.000</td> <td>0.000</td>
<td>0.000(0.000)</td> <td>0.000(0.000)</td>
</table> </table>
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2> <h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
<table class="detail_table"> <table class="detail_table">
<tr> <tr>
<th class="label">Clock Domain</th> <th class="label">Clock Domain</th>
<th class="label">Clock Frequency(Mhz)</th> <th class="label">Clock Frequency(Mhz)</th>
<th class="label">Total Dynamic Power(mW)</th> <th class="label">Total Dynamic Power(mW)</th>
</tr> </tr>
<tr> <tr>
<td>NO CLOCK DOMAIN</td> <td>NO CLOCK DOMAIN</td>
<td>0.000</td> <td>0.000</td>
<td>0.000</td> <td>0.000</td>
</tr> </tr>
</table> </table>
</div><!-- content --> </div><!-- content -->
</div><!-- main_wrapper --> </div><!-- main_wrapper -->
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//Copyright (C)2014-2024 Gowin Semiconductor Corporation. //Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved. //All rights reserved.
1. PnR Messages 1. PnR Messages
<Report Title>: PnR Report <Report Title>: PnR Report
<Design File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg <Design File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg
<Physical Constraints File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fpga_project.cst <Physical Constraints File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fpga_project.cst
<Timing Constraints File>: --- <Timing Constraints File>: ---
<Tool Version>: V1.9.9.03 Education (64-bit) <Tool Version>: V1.9.9.03 Education (64-bit)
<Part Number>: GW2A-LV18PG256C8/I7 <Part Number>: GW2A-LV18PG256C8/I7
<Device>: GW2A-18 <Device>: GW2A-18
<Device Version>: C <Device Version>: C
<Created Time>:Fri Jul 5 01:48:06 2024 <Created Time>:Fri Jul 5 01:48:06 2024
2. PnR Details 2. PnR Details
Running placement: Running placement:
Placement Phase 0: CPU time = 0h 0m 0.016s, Elapsed time = 0h 0m 0.016s Placement Phase 0: CPU time = 0h 0m 0.016s, Elapsed time = 0h 0m 0.016s
Placement Phase 1: CPU time = 0h 0m 0.654s, Elapsed time = 0h 0m 0.654s Placement Phase 1: CPU time = 0h 0m 0.654s, Elapsed time = 0h 0m 0.654s
Placement Phase 2: CPU time = 0h 0m 0.007s, Elapsed time = 0h 0m 0.007s Placement Phase 2: CPU time = 0h 0m 0.007s, Elapsed time = 0h 0m 0.007s
Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Running routing: Running routing:
Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s
Routing Phase 1: CPU time = 0h 0m 0.297s, Elapsed time = 0h 0m 0.297s Routing Phase 1: CPU time = 0h 0m 0.297s, Elapsed time = 0h 0m 0.297s
Routing Phase 2: CPU time = 0h 0m 0.19s, Elapsed time = 0h 0m 0.191s Routing Phase 2: CPU time = 0h 0m 0.19s, Elapsed time = 0h 0m 0.191s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Total Routing: CPU time = 0h 0m 0.488s, Elapsed time = 0h 0m 0.488s Total Routing: CPU time = 0h 0m 0.488s, Elapsed time = 0h 0m 0.488s
Generate output files: Generate output files:
CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s
Total Time and Memory Usage: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 438MB Total Time and Memory Usage: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 438MB
3. Resource Usage Summary 3. Resource Usage Summary
---------------------------------------------------------- ----------------------------------------------------------
Resources | Usage Resources | Usage
---------------------------------------------------------- ----------------------------------------------------------
Logic | 2/20736 <1% Logic | 2/20736 <1%
--LUT,ALU,ROM16 | 2(2 LUT, 0 ALU, 0 ROM16) --LUT,ALU,ROM16 | 2(2 LUT, 0 ALU, 0 ROM16)
--SSRAM(RAM16) | 0 --SSRAM(RAM16) | 0
Register | 0/16173 0% Register | 0/16173 0%
--Logic Register as Latch | 0/15552 0% --Logic Register as Latch | 0/15552 0%
--Logic Register as FF | 0/15552 0% --Logic Register as FF | 0/15552 0%
--I/O Register as Latch | 0/621 0% --I/O Register as Latch | 0/621 0%
--I/O Register as FF | 0/621 0% --I/O Register as FF | 0/621 0%
CLS | 1/10368 <1% CLS | 1/10368 <1%
I/O Port | 7 I/O Port | 7
I/O Buf | 7 I/O Buf | 7
--Input Buf | 4 --Input Buf | 4
--Output Buf | 3 --Output Buf | 3
--Inout Buf | 0 --Inout Buf | 0
IOLOGIC | 0% IOLOGIC | 0%
BSRAM | 0% BSRAM | 0%
DSP | 0% DSP | 0%
PLL | 0/4 0% PLL | 0/4 0%
DCS | 0/8 0% DCS | 0/8 0%
DQCE | 0/24 0% DQCE | 0/24 0%
OSC | 0/1 0% OSC | 0/1 0%
CLKDIV | 0/8 0% CLKDIV | 0/8 0%
DLLDLY | 0/8 0% DLLDLY | 0/8 0%
DQS | 0/9 0% DQS | 0/9 0%
DHCEN | 0/16 0% DHCEN | 0/16 0%
========================================================== ==========================================================
4. I/O Bank Usage Summary 4. I/O Bank Usage Summary
----------------------- -----------------------
I/O Bank | Usage I/O Bank | Usage
----------------------- -----------------------
bank 0 | 0/29(0%) bank 0 | 0/29(0%)
bank 1 | 4/20(20%) bank 1 | 4/20(20%)
bank 2 | 0/20(0%) bank 2 | 0/20(0%)
bank 3 | 0/32(0%) bank 3 | 0/32(0%)
bank 4 | 0/36(0%) bank 4 | 0/36(0%)
bank 5 | 0/36(0%) bank 5 | 0/36(0%)
bank 6 | 0/18(0%) bank 6 | 0/18(0%)
bank 7 | 3/16(18%) bank 7 | 3/16(18%)
======================= =======================
5. Global Clock Usage Summary 5. Global Clock Usage Summary
------------------------------- -------------------------------
Global Clock | Usage Global Clock | Usage
------------------------------- -------------------------------
PRIMARY | 0/8(0%) PRIMARY | 0/8(0%)
LW | 0/8(0%) LW | 0/8(0%)
GCLK_PIN | 0/8(0%) GCLK_PIN | 0/8(0%)
PLL | 0/4(0%) PLL | 0/4(0%)
CLKDIV | 0/8(0%) CLKDIV | 0/8(0%)
DLLDLY | 0/8(0%) DLLDLY | 0/8(0%)
=============================== ===============================
6. Global Clock Signals 6. Global Clock Signals
------------------------------------------- -------------------------------------------
Signal | Global Clock | Location Signal | Global Clock | Location
------------------------------------------- -------------------------------------------
=========================================== ===========================================
7. Pinout by Port Name 7. Pinout by Port Name
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
v1[0] | | B12/7 | N | in | IOL7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2 v1[0] | | B12/7 | N | in | IOL7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2
v1[1] | | B14/7 | N | in | IOL2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2 v1[1] | | B14/7 | N | in | IOL2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2
v2[0] | | A15/7 | N | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2 v2[0] | | A15/7 | N | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2
v2[1] | | K13/1 | N | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 v2[1] | | K13/1 | N | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L14[0] | | N14/1 | Y | out | IOT52[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 L14[0] | | N14/1 | Y | out | IOT52[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
L14[1] | | L14/1 | Y | out | IOT34[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 L14[1] | | L14/1 | Y | out | IOT34[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
L14[2] | | L16/1 | Y | out | IOT34[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 L14[2] | | L16/1 | Y | out | IOT34[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
================================================================================================================================================================================================================== ==================================================================================================================================================================================================================
8. All Package Pins 8. All Package Pins
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Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
L15/0 | - | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L15/0 | - | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D16/0 | - | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D16/0 | - | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E14/0 | - | in | IOT4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E14/0 | - | in | IOT4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C16/0 | - | in | IOT5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C16/0 | - | in | IOT5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F14/0 | - | in | IOT9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F14/0 | - | in | IOT9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F16/0 | - | in | IOT9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F16/0 | - | in | IOT9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J14/0 | - | in | IOT22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J14/0 | - | in | IOT22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H11/0 | - | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H11/0 | - | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L16/1 | L14[2] | out | IOT34[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 L16/1 | L14[2] | out | IOT34[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
L14/1 | L14[1] | out | IOT34[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 L14/1 | L14[1] | out | IOT34[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
K13/1 | v2[1] | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K13/1 | v2[1] | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M14/1 | - | in | IOT40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M14/1 | - | in | IOT40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D14/1 | - | in | IOT44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D14/1 | - | in | IOT44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E15/1 | - | in | IOT44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E15/1 | - | in | IOT44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N16/1 | - | in | IOT52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N16/1 | - | in | IOT52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N14/1 | L14[0] | out | IOT52[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 N14/1 | L14[0] | out | IOT52[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
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A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T4/4 | - | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T4/4 | - | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T5/4 | - | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T5/4 | - | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
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B14/7 | v1[1] | in | IOL2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2 B14/7 | v1[1] | in | IOL2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2
A15/7 | v2[0] | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2 A15/7 | v2[0] | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2
C12/7 | - | in | IOL7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 C12/7 | - | in | IOL7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2
B12/7 | v1[0] | in | IOL7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2 B12/7 | v1[0] | in | IOL7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2
B13/7 | - | in | IOL8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 B13/7 | - | in | IOL8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2
A14/7 | - | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 A14/7 | - | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2
F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2
B11/7 | - | in | IOL13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 B11/7 | - | in | IOL13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2
A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2
A11/7 | - | in | IOL15[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 A11/7 | - | in | IOL15[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2
C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2
D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2
E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2
D11/7 | - | in | IOL22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 D11/7 | - | in | IOL22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2
A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2
C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2
C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E9/6 | - | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E9/6 | - | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E8/6 | - | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E8/6 | - | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
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T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T12/2 | - | in | IOR17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T12/2 | - | in | IOR17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T11/2 | - | in | IOR24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T11/2 | - | in | IOR24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M11/2 | - | in | IOR27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M11/2 | - | in | IOR27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T7/3 | - | in | IOR29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T7/3 | - | in | IOR29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P9/3 | - | in | IOR38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P9/3 | - | in | IOR38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N8/3 | - | in | IOR40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N8/3 | - | in | IOR40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L9/3 | - | in | IOR40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L9/3 | - | in | IOR40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P8/3 | - | in | IOR42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P8/3 | - | in | IOR42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N7/3 | - | in | IOR47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N7/3 | - | in | IOR47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N6/3 | - | in | IOR51[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N6/3 | - | in | IOR51[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P6/3 | - | in | IOR53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P6/3 | - | in | IOR53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
==================================================================================================================================================================================== ====================================================================================================================================================================================

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<title>Timing Analysis Report</title> <title>Timing Analysis Report</title>
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<li><div class="triangle_fake"></div><a href="fpga_project_tr_content.html#Message" target="mainFrame" style=" font-size: 16px;">Timing Messages</a></li> <li><div class="triangle_fake"></div><a href="fpga_project_tr_content.html#Message" target="mainFrame" style=" font-size: 16px;">Timing Messages</a></li>
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</div><!-- catalog_wrapper --> </div><!-- catalog_wrapper -->
</body> </body>
</html> </html>

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<body> <body>
<div id="content"> <div id="content">
<h1><a name="Message">Timing Messages</a></h1> <h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table"> <table class="summary_table">
<tr> <tr>
<td class="label">Report Title</td> <td class="label">Report Title</td>
<td>Timing Analysis Report</td> <td>Timing Analysis Report</td>
</tr> </tr>
<tr> <tr>
<td class="label">Design File</td> <td class="label">Design File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg</td> <td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg</td>
</tr> </tr>
<tr> <tr>
<td class="label">Physical Constraints File</td> <td class="label">Physical Constraints File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fpga_project.cst</td> <td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fpga_project.cst</td>
</tr> </tr>
<tr> <tr>
<td class="label">Timing Constraint File</td> <td class="label">Timing Constraint File</td>
<td>---</td> <td>---</td>
</tr> </tr>
<tr> <tr>
<td class="label">Tool Version</td> <td class="label">Tool Version</td>
<td>V1.9.9.03 Education (64-bit)</td> <td>V1.9.9.03 Education (64-bit)</td>
</tr> </tr>
<tr> <tr>
<td class="label">Part Number</td> <td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td> <td>GW2A-LV18PG256C8/I7</td>
</tr> </tr>
<tr> <tr>
<td class="label">Device</td> <td class="label">Device</td>
<td>GW2A-18</td> <td>GW2A-18</td>
</tr> </tr>
<tr> <tr>
<td class="label">Device Version</td> <td class="label">Device Version</td>
<td>C</td> <td>C</td>
</tr> </tr>
<tr> <tr>
<td class="label">Created Time</td> <td class="label">Created Time</td>
<td>Fri Jul 5 01:48:07 2024 <td>Fri Jul 5 01:48:07 2024
</td> </td>
</tr> </tr>
<tr> <tr>
<td class="label">Legal Announcement</td> <td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td> <td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr> </tr>
</table> </table>
<h1><a name="Summary">Timing Summaries</a></h1> <h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2> <h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table"> <table class="summary_table">
<tr> <tr>
<td class="label">Setup Delay Model</td> <td class="label">Setup Delay Model</td>
<td>Slow 0.95V 85C C8/I7</td> <td>Slow 0.95V 85C C8/I7</td>
</tr> </tr>
<tr> <tr>
<td class="label">Hold Delay Model</td> <td class="label">Hold Delay Model</td>
<td>Fast 1.05V 0C C8/I7</td> <td>Fast 1.05V 0C C8/I7</td>
</tr> </tr>
<tr> <tr>
<td class="label">Numbers of Paths Analyzed</td> <td class="label">Numbers of Paths Analyzed</td>
<td>8</td> <td>8</td>
</tr> </tr>
<tr> <tr>
<td class="label">Numbers of Endpoints Analyzed</td> <td class="label">Numbers of Endpoints Analyzed</td>
<td>3</td> <td>3</td>
</tr> </tr>
<tr> <tr>
<td class="label">Numbers of Falling Endpoints</td> <td class="label">Numbers of Falling Endpoints</td>
<td>0</td> <td>0</td>
</tr> </tr>
<tr> <tr>
<td class="label">Numbers of Setup Violated Endpoints</td> <td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td> <td>0</td>
</tr> </tr>
<tr> <tr>
<td class="label">Numbers of Hold Violated Endpoints</td> <td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td> <td>0</td>
</tr> </tr>
</table> </table>
<h2><a name="Clock_Report">Clock Summary:</a></h2> <h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table"> <table class="detail_table">
<tr> <tr>
<th class="label">Clock Name</th> <th class="label">Clock Name</th>
<th class="label">Type</th> <th class="label">Type</th>
<th class="label">Period</th> <th class="label">Period</th>
<th class="label">Frequency(MHz)</th> <th class="label">Frequency(MHz)</th>
<th class="label">Rise</th> <th class="label">Rise</th>
<th class="label">Fall</th> <th class="label">Fall</th>
<th class="label">Source</th> <th class="label">Source</th>
<th class="label">Master</th> <th class="label">Master</th>
<th class="label">Objects</th> <th class="label">Objects</th>
</tr> </tr>
</table> </table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2> <h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table> <table>
<tr> <tr>
<th>NO.</th> <th>NO.</th>
<th>Clock Name</th> <th>Clock Name</th>
<th>Constraint</th> <th>Constraint</th>
<th>Actual Fmax</th> <th>Actual Fmax</th>
<th>Logic Level</th> <th>Logic Level</th>
<th>Entity</th> <th>Entity</th>
</tr> </tr>
</table> </table>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2> <h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table"> <table class="detail_table">
<tr> <tr>
<th class="label">Clock Name</th> <th class="label">Clock Name</th>
<th class="label">Analysis Type</th> <th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th> <th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th> <th class="label">Number of Endpoints</th>
</tr> </tr>
</table> </table>
<h1><a name="Detail">Timing Details</a></h1> <h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2> <h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3> <h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4> <h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4> <h4>Nothing to report!</h4>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3> <h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4> <h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4> <h4>Nothing to report!</h4>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3> <h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4> <h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4> <h4>Nothing to report!</h4>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3> <h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4> <h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4> <h4>Nothing to report!</h4>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2> <h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table"> <table class="detail_table">
<tr> <tr>
<th class="label">Number</th> <th class="label">Number</th>
<th class="label">Slack</th> <th class="label">Slack</th>
<th class="label">Actual Width</th> <th class="label">Actual Width</th>
<th class="label">Required Width</th> <th class="label">Required Width</th>
<th class="label">Type</th> <th class="label">Type</th>
<th class="label">Clock</th> <th class="label">Clock</th>
<th class="label">Objects</th> <th class="label">Objects</th>
</tr> </tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4> <h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h4>Nothing to report!</h4> <h4>Nothing to report!</h4>
</table> </table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2> <h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3> <h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4> <h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h4>No setup paths to report!</h4> <h4>No setup paths to report!</h4>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3> <h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4> <h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h4>No hold paths to report!</h4> <h4>No hold paths to report!</h4>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3> <h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4> <h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>No recovery paths to report!</h4> <h4>No recovery paths to report!</h4>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3> <h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4> <h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>No removal paths to report!</h4> <h4>No removal paths to report!</h4>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2> <h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4> <h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h4>Nothing to report!</h4> <h4>Nothing to report!</h4>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2> <h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4> <h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table"> <table class="detail_table">
<tr> <tr>
<th class="label">FANOUT</th> <th class="label">FANOUT</th>
<th class="label">NET NAME</th> <th class="label">NET NAME</th>
<th class="label">WORST SLACK</th> <th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th> <th class="label">MAX DELAY</th>
</tr> </tr>
</table> </table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2> <h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4> <h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table"> <table class="detail_table">
<tr> <tr>
<th class="label">GRID LOC</th> <th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th> <th class="label">ROUTE CONGESTIONS</th>
</tr> </tr>
<tr> <tr>
<td>R2C1</td> <td>R2C1</td>
<td>5.56%</td> <td>5.56%</td>
</tr> </tr>
<tr> <tr>
<td>R1C34</td> <td>R1C34</td>
<td>2.78%</td> <td>2.78%</td>
</tr> </tr>
<tr> <tr>
<td>R2C25</td> <td>R2C25</td>
<td>2.78%</td> <td>2.78%</td>
</tr> </tr>
<tr> <tr>
<td>R2C26</td> <td>R2C26</td>
<td>2.78%</td> <td>2.78%</td>
</tr> </tr>
<tr> <tr>
<td>R2C9</td> <td>R2C9</td>
<td>2.78%</td> <td>2.78%</td>
</tr> </tr>
<tr> <tr>
<td>R2C17</td> <td>R2C17</td>
<td>2.78%</td> <td>2.78%</td>
</tr> </tr>
<tr> <tr>
<td>R2C8</td> <td>R2C8</td>
<td>1.39%</td> <td>1.39%</td>
</tr> </tr>
<tr> <tr>
<td>R2C34</td> <td>R2C34</td>
<td>1.39%</td> <td>1.39%</td>
</tr> </tr>
<tr> <tr>
<td>R7C1</td> <td>R7C1</td>
<td>1.39%</td> <td>1.39%</td>
</tr> </tr>
<tr> <tr>
<td>R1C36</td> <td>R1C36</td>
<td>1.39%</td> <td>1.39%</td>
</tr> </tr>
</table> </table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2> <h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3> <h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4> <h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4> <h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3> <h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4> <h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4> <h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3> <h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4> <h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4> <h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3> <h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4> <h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4> <h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2> <h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table"> <table class="detail_table">
<tr> <tr>
<th class="label">SDC Command Type</th> <th class="label">SDC Command Type</th>
<th class="label">State</th> <th class="label">State</th>
<th class="label">Detail Command</th> <th class="label">Detail Command</th>
</tr> </tr>
</table> </table>
</div><!-- content --> </div><!-- content -->
</body> </body>
</html> </html>

162
gowin/fpga_project/impl/temp/rtl_parser.result
View File

@ -1,82 +1,82 @@
[ [
{ {
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v", "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v",
"InstLine" : 1, "InstLine" : 1,
"InstName" : "ledTest", "InstName" : "ledTest",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v",
"ModuleLine" : 1, "ModuleLine" : 1,
"ModuleName" : "ledTest", "ModuleName" : "ledTest",
"SubInsts" : [ "SubInsts" : [
{ {
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v", "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v",
"InstLine" : 8, "InstLine" : 8,
"InstName" : "adder", "InstName" : "adder",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
"ModuleLine" : 1, "ModuleLine" : 1,
"ModuleName" : "bit3adder", "ModuleName" : "bit3adder",
"SubInsts" : [ "SubInsts" : [
{ {
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v", "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
"InstLine" : 9, "InstLine" : 9,
"InstName" : "ha0", "InstName" : "ha0",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
"ModuleLine" : 1, "ModuleLine" : 1,
"ModuleName" : "halfadder" "ModuleName" : "halfadder"
}, },
{ {
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v", "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
"InstLine" : 10, "InstLine" : 10,
"InstName" : "fa0", "InstName" : "fa0",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
"ModuleLine" : 1, "ModuleLine" : 1,
"ModuleName" : "fulladder", "ModuleName" : "fulladder",
"SubInsts" : [ "SubInsts" : [
{ {
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v", "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
"InstLine" : 8, "InstLine" : 8,
"InstName" : "ha1", "InstName" : "ha1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
"ModuleLine" : 1, "ModuleLine" : 1,
"ModuleName" : "halfadder" "ModuleName" : "halfadder"
}, },
{ {
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v", "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
"InstLine" : 9, "InstLine" : 9,
"InstName" : "ha2", "InstName" : "ha2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
"ModuleLine" : 1, "ModuleLine" : 1,
"ModuleName" : "halfadder" "ModuleName" : "halfadder"
} }
] ]
}, },
{ {
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v", "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
"InstLine" : 11, "InstLine" : 11,
"InstName" : "fa1", "InstName" : "fa1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
"ModuleLine" : 1, "ModuleLine" : 1,
"ModuleName" : "fulladder", "ModuleName" : "fulladder",
"SubInsts" : [ "SubInsts" : [
{ {
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v", "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
"InstLine" : 8, "InstLine" : 8,
"InstName" : "ha1", "InstName" : "ha1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
"ModuleLine" : 1, "ModuleLine" : 1,
"ModuleName" : "halfadder" "ModuleName" : "halfadder"
}, },
{ {
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v", "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
"InstLine" : 9, "InstLine" : 9,
"InstName" : "ha2", "InstName" : "ha2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
"ModuleLine" : 1, "ModuleLine" : 1,
"ModuleName" : "halfadder" "ModuleName" : "halfadder"
} }
] ]
} }
] ]
} }
] ]
} }
] ]

56
gowin/fpga_project/impl/temp/rtl_parser_arg.json
View File

@ -1,29 +1,29 @@
{ {
"Device" : "GW2A-18C", "Device" : "GW2A-18C",
"Files" : [ "Files" : [
{ {
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v", "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
"Type" : "verilog" "Type" : "verilog"
}, },
{ {
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v", "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
"Type" : "verilog" "Type" : "verilog"
}, },
{ {
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v", "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
"Type" : "verilog" "Type" : "verilog"
}, },
{ {
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v", "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v",
"Type" : "verilog" "Type" : "verilog"
} }
], ],
"IncludePath" : [ "IncludePath" : [
], ],
"LoopLimit" : 2000, "LoopLimit" : 2000,
"ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/impl/temp/rtl_parser.result", "ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/impl/temp/rtl_parser.result",
"Top" : "", "Top" : "",
"VerilogStd" : "verilog_2001", "VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93" "VhdlStd" : "vhdl_93"
} }

24
gowin/fpga_project/src/bit3adder.v
View File

@ -1,13 +1,13 @@
module bit3adder( module bit3adder(
input [2:0] A, input [2:0] A,
input [2:0] B, input [2:0] B,
output [3:0] C output [3:0] C
); );
wire c1,c2,c3,c4; wire c1,c2,c3,c4;
halfadder ha0(A[0], B[0], C[0], c1); halfadder ha0(A[0], B[0], C[0], c1);
fulladder fa0(A[1], B[1], c1, C[1], c2); fulladder fa0(A[1], B[1], c1, C[1], c2);
fulladder fa1(A[2], B[2], c2, C[2], C[3]); fulladder fa1(A[2], B[2], c2, C[2], C[3]);
endmodule endmodule

30
gowin/fpga_project/src/fpga_project.cst
View File

@ -1,15 +1,15 @@
//Copyright (C)2014-2024 Gowin Semiconductor Corporation. //Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved. //All rights reserved.
//File Title: Physical Constraints file //File Title: Physical Constraints file
//Tool Version: V1.9.9.03 Education (64-bit) //Tool Version: V1.9.9.03 Education (64-bit)
//Part Number: GW2A-LV18PG256C8/I7 //Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18 //Device: GW2A-18
//Device Version: C //Device Version: C
//Created Time: Fri 07 05 01:47:34 2024 //Created Time: Fri 07 05 01:47:34 2024
IO_LOC "L14[2]" L16; IO_LOC "L14[2]" L16;
IO_PORT "L14[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; IO_PORT "L14[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "L14[1]" L14; IO_LOC "L14[1]" L14;
IO_PORT "L14[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; IO_PORT "L14[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "L14[0]" N14; IO_LOC "L14[0]" N14;
IO_PORT "L14[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; IO_PORT "L14[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;

24
gowin/fpga_project/src/fulladder.v
View File

@ -1,13 +1,13 @@
module fulladder( module fulladder(
input A, B, C0, input A, B, C0,
output S, C output S, C
); );
wire S1,C1,C2; wire S1,C1,C2;
halfadder ha1(A, B, S1, C1); halfadder ha1(A, B, S1, C1);
halfadder ha2(S1, C0, S, C2); halfadder ha2(S1, C0, S, C2);
or (C, C2, C1); or (C, C2, C1);
endmodule endmodule

16
gowin/fpga_project/src/halfadder.v
View File

@ -1,9 +1,9 @@
module halfadder( module halfadder(
input A,B, input A,B,
output S,C output S,C
); );
xor (S, A, B); xor (S, A, B);
and (C, A, B); and (C, A, B);
endmodule endmodule

60
gowin/fpga_project/src/ledTest.v
View File

@ -1,31 +1,31 @@
module ledTest ( module ledTest (
input[1:0] v1, v2, input[1:0] v1, v2,
output reg[2:0] L14 output reg[2:0] L14
); );
wire[3:0] sum; wire[3:0] sum;
bit3adder adder( bit3adder adder(
.A({1'b0, v1}), .A({1'b0, v1}),
.B({1'b0, v2}), .B({1'b0, v2}),
.C(sum) .C(sum)
); );
always @(*) begin always @(*) begin
L14 = 6'b000_000; L14 = 6'b000_000;
if(sum == 4'd0) begin if(sum == 4'd0) begin
L14 = 6'b000_000; L14 = 6'b000_000;
end end
else if(sum == 4'd1) else if(sum == 4'd1)
L14 = 3'b01; L14 = 3'b01;
else if(sum == 4'd2) else if(sum == 4'd2)
L14 = 3'b10; L14 = 3'b10;
else if(sum == 4'd3) else if(sum == 4'd3)
L14 = 3'b11; L14 = 3'b11;
end end
endmodule endmodule

50
gowin/seq_light_test/impl/gwsynthesis/seq_light_test.log
View File

@ -1,25 +1,25 @@
GowinSynthesis start GowinSynthesis start
Running parser ... Running parser ...
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v' Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v'
Compiling module 'seqBlink'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v":1) Compiling module 'seqBlink'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v":1)
WARN (EX3791) : Expression size 4 truncated to fit in target size 3("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v":23) WARN (EX3791) : Expression size 4 truncated to fit in target size 3("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v":23)
NOTE (EX0101) : Current top module is "seqBlink" NOTE (EX0101) : Current top module is "seqBlink"
[5%] Running netlist conversion ... [5%] Running netlist conversion ...
Running device independent optimization ... Running device independent optimization ...
[10%] Optimizing Phase 0 completed [10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed [15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed [25%] Optimizing Phase 2 completed
Running inference ... Running inference ...
[30%] Inferring Phase 0 completed [30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed [40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed [50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed [55%] Inferring Phase 3 completed
Running technical mapping ... Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed [60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed [65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed [75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed [80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed [90%] Tech-Mapping Phase 4 completed
[95%] Generate netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg" completed [95%] Generate netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg" completed
[100%] Generate report file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test_syn.rpt.html" completed [100%] Generate report file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test_syn.rpt.html" completed
GowinSynthesis finish GowinSynthesis finish

38
gowin/seq_light_test/impl/gwsynthesis/seq_light_test.prj
View File

@ -1,19 +1,19 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project> <!DOCTYPE gowin-synthesis-project>
<Project> <Project>
<Version>beta</Version> <Version>beta</Version>
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/> <Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList> <FileList>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v" type="verilog"/> <File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v" type="verilog"/>
</FileList> </FileList>
<OptionList> <OptionList>
<Option type="disable_insert_pad" value="0"/> <Option type="disable_insert_pad" value="0"/>
<Option type="global_freq" value="100.000"/> <Option type="global_freq" value="100.000"/>
<Option type="looplimit" value="2000"/> <Option type="looplimit" value="2000"/>
<Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg"/> <Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg"/>
<Option type="print_all_synthesis_warning" value="0"/> <Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="0"/> <Option type="ram_rw_check" value="0"/>
<Option type="verilog_language" value="verilog-2001"/> <Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/> <Option type="vhdl_language" value="vhdl-1993"/>
</OptionList> </OptionList>
</Project> </Project>

550
gowin/seq_light_test/impl/gwsynthesis/seq_light_test.vg
View File

@ -1,275 +1,275 @@
// //
//Written by GowinSynthesis //Written by GowinSynthesis
//Tool Version "V1.9.9.03 Education (64-bit)" //Tool Version "V1.9.9.03 Education (64-bit)"
//Sun Jul 7 15:45:04 2024 //Sun Jul 7 15:45:04 2024
//Source file index table: //Source file index table:
//file0 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v" //file0 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v"
`pragma protect begin_protected `pragma protect begin_protected
`pragma protect version="2.3" `pragma protect version="2.3"
`pragma protect author="default" `pragma protect author="default"
`pragma protect author_info="default" `pragma protect author_info="default"
`pragma protect encrypt_agent="GOWIN" `pragma protect encrypt_agent="GOWIN"
`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3" `pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=256) `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa" `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
`pragma protect key_block `pragma protect key_block
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`pragma protect data_keyowner="default-ip-vendor" `pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key" `pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cfb" `pragma protect data_method="aes128-cfb"
`pragma protect data_block `pragma protect data_block
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+DO9aImU9O12Ia8FpYtloJfBNGxTASQqdRuBn1T+7gjtiEn14FpOTnA5+OmTn9bCGgxlgN8i/eJk +DO9aImU9O12Ia8FpYtloJfBNGxTASQqdRuBn1T+7gjtiEn14FpOTnA5+OmTn9bCGgxlgN8i/eJk
jXi+ jXi+
`pragma protect end_protected `pragma protect end_protected

2590
gowin/seq_light_test/impl/gwsynthesis/seq_light_test_syn.rpt.html
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gowin/seq_light_test/impl/gwsynthesis/seq_light_test_syn_resource.html
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html> <html>
<head> <head>
<title>Hierarchy Module Resource</title> <title>Hierarchy Module Resource</title>
<style type="text/css"> <style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; } body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
div#main_wrapper{ width: 100%; } div#main_wrapper{ width: 100%; }
h1 {text-align: center; } h1 {text-align: center; }
h1 {margin-top: 36px; } h1 {margin-top: 36px; }
table, th, td { border: 1px solid #aaa; } table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; } table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { align = "center"; padding: 5px 2px 5px 5px; } th, td { align = "center"; padding: 5px 2px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; } th { color: #fff; font-weight: bold; background-color: #0084ff; }
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; } table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
</style> </style>
</head> </head>
<body> <body>
<div id="main_wrapper"> <div id="main_wrapper">
<div id="content"> <div id="content">
<h1>Hierarchy Module Resource</h1> <h1>Hierarchy Module Resource</h1>
<table> <table>
<tr> <tr>
<th class="label">MODULE NAME</th> <th class="label">MODULE NAME</th>
<th class="label">REG NUMBER</th> <th class="label">REG NUMBER</th>
<th class="label">ALU NUMBER</th> <th class="label">ALU NUMBER</th>
<th class="label">LUT NUMBER</th> <th class="label">LUT NUMBER</th>
<th class="label">DSP NUMBER</th> <th class="label">DSP NUMBER</th>
<th class="label">BSRAM NUMBER</th> <th class="label">BSRAM NUMBER</th>
<th class="label">SSRAM NUMBER</th> <th class="label">SSRAM NUMBER</th>
<th class="label">ROM16 NUMBER</th> <th class="label">ROM16 NUMBER</th>
</tr> </tr>
<tr> <tr>
<td class="label">seqBlink (//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v)</td> <td class="label">seqBlink (//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v)</td>
<td align = "center">40</td> <td align = "center">40</td>
<td align = "center">31</td> <td align = "center">31</td>
<td align = "center">23</td> <td align = "center">23</td>
<td align = "center">-</td> <td align = "center">-</td>
<td align = "center">-</td> <td align = "center">-</td>
<td align = "center">-</td> <td align = "center">-</td>
<td align = "center">-</td> <td align = "center">-</td>
</tr> </tr>
</table> </table>
</div><!-- content --> </div><!-- content -->
</div><!-- main_wrapper --> </div><!-- main_wrapper -->
</body> </body>
</html> </html>

4
gowin/seq_light_test/impl/gwsynthesis/seq_light_test_syn_rsc.xml
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@ -1,2 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<Module name="seqBlink" Register="40" Alu="31" Lut="23" T_Register="40(40)" T_Alu="31(31)" T_Lut="23(23)"/> <Module name="seqBlink" Register="40" Alu="31" Lut="23" T_Register="40(40)" T_Alu="31(31)" T_Lut="23(23)"/>

26
gowin/seq_light_test/impl/pnr/cmd.do
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@ -1,13 +1,13 @@
-d \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg -d \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg
-p GW2A-18C-PBGA256-8 -p GW2A-18C-PBGA256-8
-pn GW2A-LV18PG256C8/I7 -pn GW2A-LV18PG256C8/I7
-cst \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst -cst \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst
-cfg \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\device.cfg -cfg \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\device.cfg
-bit -bit
-tr -tr
-ph -ph
-timing -timing
-cst_error -cst_error
-correct_hold 1 -correct_hold 1
-route_maxfan 23 -route_maxfan 23
-global_freq 100.000 -global_freq 100.000

42
gowin/seq_light_test/impl/pnr/device.cfg
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@ -1,21 +1,21 @@
set JTAG regular_io = false set JTAG regular_io = false
set SSPI regular_io = false set SSPI regular_io = false
set MSPI regular_io = false set MSPI regular_io = false
set READY regular_io = false set READY regular_io = false
set DONE regular_io = false set DONE regular_io = false
set I2C regular_io = false set I2C regular_io = false
set RECONFIG_N regular_io = false set RECONFIG_N regular_io = false
set CRC_check = true set CRC_check = true
set compress = false set compress = false
set encryption = false set encryption = false
set security_bit_enable = true set security_bit_enable = true
set bsram_init_fuse_print = true set bsram_init_fuse_print = true
set background_programming = off set background_programming = off
set secure_mode = false set secure_mode = false
set program_done_bypass = false set program_done_bypass = false
set wake_up = 0 set wake_up = 0
set format = binary set format = binary
set power_on_reset_monitor = true set power_on_reset_monitor = true
set multiboot_spi_flash_address = 0x00000000 set multiboot_spi_flash_address = 0x00000000
set vccx = 3.3 set vccx = 3.3
set unused_pin = default set unused_pin = default

2756
gowin/seq_light_test/impl/pnr/seq_light_test.fs
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gowin/seq_light_test/impl/pnr/seq_light_test.log
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@ -1,29 +1,29 @@
Reading netlist file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg" Reading netlist file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg"
Parsing netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg" completed Parsing netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg" completed
Processing netlist completed Processing netlist completed
Reading constraint file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst" Reading constraint file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst"
Physical Constraint parsed completed Physical Constraint parsed completed
Running placement...... Running placement......
[10%] Placement Phase 0 completed [10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed [20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed [30%] Placement Phase 2 completed
[50%] Placement Phase 3 completed [50%] Placement Phase 3 completed
Running routing...... Running routing......
[60%] Routing Phase 0 completed [60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed [70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed [80%] Routing Phase 2 completed
[90%] Routing Phase 3 completed [90%] Routing Phase 3 completed
Running timing analysis...... Running timing analysis......
[95%] Timing analysis completed [95%] Timing analysis completed
Placement and routing completed Placement and routing completed
Bitstream generation in progress...... Bitstream generation in progress......
Bitstream generation completed Bitstream generation completed
Running power analysis...... Running power analysis......
[100%] Power analysis completed [100%] Power analysis completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.power.html" completed Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.power.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.pin.html" completed Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.pin.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.rpt.html" completed Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.rpt.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.rpt.txt" completed Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.rpt.txt" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.tr.html" completed Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.tr.html" completed
Sun Jul 7 15:45:27 2024 Sun Jul 7 15:45:27 2024

7074
gowin/seq_light_test/impl/pnr/seq_light_test.pin.html
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gowin/seq_light_test/impl/pnr/seq_light_test.power.html
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@ -1,276 +1,276 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html> <html>
<head> <head>
<title>Power Analysis Report</title> <title>Power Analysis Report</title>
<style type="text/css"> <style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; } body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper { width: 100%; } div#main_wrapper { width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; } div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; } div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; } div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; } div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; } div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; } div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; } div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; } hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; } h1, h3 { text-align: center; }
h1 {margin-top: 50px; } h1 {margin-top: 50px; }
table, th, td {white-space:pre; border: 1px solid #aaa; } table, th, td {white-space:pre; border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; } table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; } th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; } th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; } table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; } table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; } table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table th.label { min-width: 8%; width: 8%; } table.detail_table th.label { min-width: 8%; width: 8%; }
</style> </style>
</head> </head>
<body> <body>
<div id="main_wrapper"> <div id="main_wrapper">
<div id="catalog_wrapper"> <div id="catalog_wrapper">
<div id="catalog"> <div id="catalog">
<ul> <ul>
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a> <li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
<ul> <ul>
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li> <li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
</ul> </ul>
</li> </li>
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a> <li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
<ul> <ul>
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li> <li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li> <li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li> <li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
</ul> </ul>
</li> </li>
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a> <li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
<ul> <ul>
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li> <li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li> <li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li> <li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
</ul> </ul>
</li> </li>
</ul> </ul>
</div><!-- catalog --> </div><!-- catalog -->
</div><!-- catalog_wrapper --> </div><!-- catalog_wrapper -->
<div id="content"> <div id="content">
<h1><a name="Message">Power Messages</a></h1> <h1><a name="Message">Power Messages</a></h1>
<table class="summary_table"> <table class="summary_table">
<tr> <tr>
<td class="label">Report Title</td> <td class="label">Report Title</td>
<td>Power Analysis Report</td> <td>Power Analysis Report</td>
</tr> </tr>
<tr> <tr>
<td class="label">Design File</td> <td class="label">Design File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg</td> <td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg</td>
</tr> </tr>
<tr> <tr>
<td class="label">Physical Constraints File</td> <td class="label">Physical Constraints File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst</td> <td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst</td>
</tr> </tr>
<tr> <tr>
<td class="label">Timing Constraints File</td> <td class="label">Timing Constraints File</td>
<td>---</td> <td>---</td>
</tr> </tr>
<tr> <tr>
<td class="label">Tool Version</td> <td class="label">Tool Version</td>
<td>V1.9.9.03 Education (64-bit)</td> <td>V1.9.9.03 Education (64-bit)</td>
</tr> </tr>
<tr> <tr>
<td class="label">Part Number</td> <td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td> <td>GW2A-LV18PG256C8/I7</td>
</tr> </tr>
<tr> <tr>
<td class="label">Device</td> <td class="label">Device</td>
<td>GW2A-18</td> <td>GW2A-18</td>
</tr> </tr>
<tr> <tr>
<td class="label">Device Version</td> <td class="label">Device Version</td>
<td>C</td> <td>C</td>
</tr> </tr>
<tr> <tr>
<td class="label">Created Time</td> <td class="label">Created Time</td>
<td>Sun Jul 7 15:45:13 2024 <td>Sun Jul 7 15:45:13 2024
</td> </td>
</tr> </tr>
<tr> <tr>
<td class="label">Legal Announcement</td> <td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td> <td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr> </tr>
</table> </table>
<h2><a name="Configure_Info">Configure Information:</a></h2> <h2><a name="Configure_Info">Configure Information:</a></h2>
<table class="summary_table"> <table class="summary_table">
<tr> <tr>
<td class="label">Grade</td> <td class="label">Grade</td>
<td>Commercial</td> <td>Commercial</td>
</tr> </tr>
<tr> <tr>
<td class="label">Process</td> <td class="label">Process</td>
<td>Typical</td> <td>Typical</td>
</tr> </tr>
<tr> <tr>
<td class="label">Ambient Temperature</td> <td class="label">Ambient Temperature</td>
<td>25.000 <td>25.000
</tr> </tr>
<tr> <tr>
<td class="label">Use Custom Theta JA</td> <td class="label">Use Custom Theta JA</td>
<td>false</td> <td>false</td>
</tr> </tr>
<tr> <tr>
<td class="label">Heat Sink</td> <td class="label">Heat Sink</td>
<td>None</td> <td>None</td>
</tr> </tr>
<tr> <tr>
<td class="label">Air Flow</td> <td class="label">Air Flow</td>
<td>LFM_0</td> <td>LFM_0</td>
</tr> </tr>
<tr> <tr>
<td class="label">Use Custom Theta SA</td> <td class="label">Use Custom Theta SA</td>
<td>false</td> <td>false</td>
</tr> </tr>
<tr> <tr>
<td class="label">Board Thermal Model</td> <td class="label">Board Thermal Model</td>
<td>None</td> <td>None</td>
</tr> </tr>
<tr> <tr>
<td class="label">Use Custom Theta JB</td> <td class="label">Use Custom Theta JB</td>
<td>false</td> <td>false</td>
</tr> </tr>
<tr> <tr>
<td class="label">Related Vcd File</td> <td class="label">Related Vcd File</td>
<td></td> <td></td>
</tr> </tr>
<tr> <tr>
<td class="label">Related Saif File</td> <td class="label">Related Saif File</td>
<td></td> <td></td>
</tr> </tr>
<tr> <tr>
<td class="label">Filter Glitches</td> <td class="label">Filter Glitches</td>
<td>false</td> <td>false</td>
</tr> </tr>
<tr> <tr>
<td class="label">Default IO Toggle Rate</td> <td class="label">Default IO Toggle Rate</td>
<td>0.125</td> <td>0.125</td>
</tr> </tr>
<tr> <tr>
<td class="label">Default Remain Toggle Rate</td> <td class="label">Default Remain Toggle Rate</td>
<td>0.125</td> <td>0.125</td>
</tr> </tr>
</table> </table>
<h1><a name="Summary">Power Summary</a></h1> <h1><a name="Summary">Power Summary</a></h1>
<h2><a name="Power_Info">Power Information:</a></h2> <h2><a name="Power_Info">Power Information:</a></h2>
<table class="summary_table"> <table class="summary_table">
<tr> <tr>
<td class="label">Total Power (mW)</td> <td class="label">Total Power (mW)</td>
<td>124.846</td> <td>124.846</td>
</tr> </tr>
<tr> <tr>
<td class="label">Quiescent Power (mW)</td> <td class="label">Quiescent Power (mW)</td>
<td>121.198</td> <td>121.198</td>
</tr> </tr>
<tr> <tr>
<td class="label">Dynamic Power (mW)</td> <td class="label">Dynamic Power (mW)</td>
<td>3.647</td> <td>3.647</td>
</tr> </tr>
</table> </table>
<h2><a name="Thermal_Info">Thermal Information:</a></h2> <h2><a name="Thermal_Info">Thermal Information:</a></h2>
<table class="summary_table"> <table class="summary_table">
<tr> <tr>
<td class="label">Junction Temperature</td> <td class="label">Junction Temperature</td>
<td>28.998</td> <td>28.998</td>
</tr> </tr>
<tr> <tr>
<td class="label">Theta JA</td> <td class="label">Theta JA</td>
<td>32.020</td> <td>32.020</td>
</tr> </tr>
<tr> <tr>
<td class="label">Max Allowed Ambient Temperature</td> <td class="label">Max Allowed Ambient Temperature</td>
<td>81.002</td> <td>81.002</td>
</tr> </tr>
</table> </table>
<h2><a name="Supply_Summary">Supply Information:</a></h2> <h2><a name="Supply_Summary">Supply Information:</a></h2>
<table class="summary_table"> <table class="summary_table">
<tr> <tr>
<th class="label">Voltage Source</th> <th class="label">Voltage Source</th>
<th class="label">Voltage</th> <th class="label">Voltage</th>
<th class="label">Dynamic Current(mA)</th> <th class="label">Dynamic Current(mA)</th>
<th class="label">Quiescent Current(mA)</th> <th class="label">Quiescent Current(mA)</th>
<th class="label">Power(mW)</th> <th class="label">Power(mW)</th>
</tr> </tr>
<tr> <tr>
<td>VCC</td> <td>VCC</td>
<td>1.000</td> <td>1.000</td>
<td>0.863</td> <td>0.863</td>
<td>69.994</td> <td>69.994</td>
<td>70.857</td> <td>70.857</td>
</tr> </tr>
<tr> <tr>
<td>VCCX</td> <td>VCCX</td>
<td>3.300</td> <td>3.300</td>
<td>0.548</td> <td>0.548</td>
<td>15.000</td> <td>15.000</td>
<td>51.307</td> <td>51.307</td>
</tr> </tr>
<tr> <tr>
<td>VCCIO18</td> <td>VCCIO18</td>
<td>1.800</td> <td>1.800</td>
<td>0.543</td> <td>0.543</td>
<td>0.947</td> <td>0.947</td>
<td>2.682</td> <td>2.682</td>
</tr> </tr>
</table> </table>
<h1><a name="Detail">Power Details</a></h1> <h1><a name="Detail">Power Details</a></h1>
<h2><a name="By_Block_Type">Power By Block Type:</a></h2> <h2><a name="By_Block_Type">Power By Block Type:</a></h2>
<table class="detail_table"> <table class="detail_table">
<tr> <tr>
<th class="label">Block Type</th> <th class="label">Block Type</th>
<th class="label">Total Power(mW)</th> <th class="label">Total Power(mW)</th>
<th class="label">Static Power(mW)</th> <th class="label">Static Power(mW)</th>
<th class="label">Average Toggle Rate(millions of transitions/sec)</th> <th class="label">Average Toggle Rate(millions of transitions/sec)</th>
</tr> </tr>
<tr> <tr>
<td>Logic</td> <td>Logic</td>
<td>0.288</td> <td>0.288</td>
<td>NA</td> <td>NA</td>
<td>13.206</td> <td>13.206</td>
</tr> </tr>
<tr> <tr>
<td>IO</td> <td>IO</td>
<td>5.886 <td>5.886
<td>2.553 <td>2.553
<td>30.000 <td>30.000
</tr> </tr>
</table> </table>
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2> <h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
<table class="detail_table"> <table class="detail_table">
<tr> <tr>
<th class="label">Hierarchy Entity</th> <th class="label">Hierarchy Entity</th>
<th class="label">Total Power(mW)</th> <th class="label">Total Power(mW)</th>
<th class="label">Block Dynamic Power(mW)</th> <th class="label">Block Dynamic Power(mW)</th>
</tr> </tr>
<tr> <tr>
<td>seqBlink</td> <td>seqBlink</td>
<td>0.288</td> <td>0.288</td>
<td>0.288(0.000)</td> <td>0.288(0.000)</td>
</table> </table>
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2> <h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
<table class="detail_table"> <table class="detail_table">
<tr> <tr>
<th class="label">Clock Domain</th> <th class="label">Clock Domain</th>
<th class="label">Clock Frequency(Mhz)</th> <th class="label">Clock Frequency(Mhz)</th>
<th class="label">Total Dynamic Power(mW)</th> <th class="label">Total Dynamic Power(mW)</th>
</tr> </tr>
<tr> <tr>
<td>newclk</td> <td>newclk</td>
<td>100.000</td> <td>100.000</td>
<td>0.024</td> <td>0.024</td>
</tr> </tr>
<tr> <tr>
<td>clock</td> <td>clock</td>
<td>100.000</td> <td>100.000</td>
<td>0.291</td> <td>0.291</td>
</tr> </tr>
</table> </table>
</div><!-- content --> </div><!-- content -->
</div><!-- main_wrapper --> </div><!-- main_wrapper -->
</body> </body>
</html> </html>

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//Copyright (C)2014-2024 Gowin Semiconductor Corporation. //Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved. //All rights reserved.
1. PnR Messages 1. PnR Messages
<Report Title>: PnR Report <Report Title>: PnR Report
<Design File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg <Design File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg
<Physical Constraints File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst <Physical Constraints File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst
<Timing Constraints File>: --- <Timing Constraints File>: ---
<Tool Version>: V1.9.9.03 Education (64-bit) <Tool Version>: V1.9.9.03 Education (64-bit)
<Part Number>: GW2A-LV18PG256C8/I7 <Part Number>: GW2A-LV18PG256C8/I7
<Device>: GW2A-18 <Device>: GW2A-18
<Device Version>: C <Device Version>: C
<Created Time>:Sun Jul 7 15:45:18 2024 <Created Time>:Sun Jul 7 15:45:18 2024
2. PnR Details 2. PnR Details
Running placement: Running placement:
Placement Phase 0: CPU time = 0h 0m 0.01s, Elapsed time = 0h 0m 0.01s Placement Phase 0: CPU time = 0h 0m 0.01s, Elapsed time = 0h 0m 0.01s
Placement Phase 1: CPU time = 0h 0m 0.529s, Elapsed time = 0h 0m 0.529s Placement Phase 1: CPU time = 0h 0m 0.529s, Elapsed time = 0h 0m 0.529s
Placement Phase 2: CPU time = 0h 0m 0.012s, Elapsed time = 0h 0m 0.012s Placement Phase 2: CPU time = 0h 0m 0.012s, Elapsed time = 0h 0m 0.012s
Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Running routing: Running routing:
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Routing Phase 1: CPU time = 0h 0m 0.254s, Elapsed time = 0h 0m 0.254s Routing Phase 1: CPU time = 0h 0m 0.254s, Elapsed time = 0h 0m 0.254s
Routing Phase 2: CPU time = 0h 0m 0.283s, Elapsed time = 0h 0m 0.283s Routing Phase 2: CPU time = 0h 0m 0.283s, Elapsed time = 0h 0m 0.283s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Total Routing: CPU time = 0h 0m 0.537s, Elapsed time = 0h 0m 0.537s Total Routing: CPU time = 0h 0m 0.537s, Elapsed time = 0h 0m 0.537s
Generate output files: Generate output files:
CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s
Total Time and Memory Usage: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 439MB Total Time and Memory Usage: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 439MB
3. Resource Usage Summary 3. Resource Usage Summary
---------------------------------------------------------- ----------------------------------------------------------
Resources | Usage Resources | Usage
---------------------------------------------------------- ----------------------------------------------------------
Logic | 55/20736 <1% Logic | 55/20736 <1%
--LUT,ALU,ROM16 | 55(23 LUT, 32 ALU, 0 ROM16) --LUT,ALU,ROM16 | 55(23 LUT, 32 ALU, 0 ROM16)
--SSRAM(RAM16) | 0 --SSRAM(RAM16) | 0
Register | 40/16173 <1% Register | 40/16173 <1%
--Logic Register as Latch | 0/15552 0% --Logic Register as Latch | 0/15552 0%
--Logic Register as FF | 36/15552 <1% --Logic Register as FF | 36/15552 <1%
--I/O Register as Latch | 0/621 0% --I/O Register as Latch | 0/621 0%
--I/O Register as FF | 4/621 <1% --I/O Register as FF | 4/621 <1%
CLS | 30/10368 <1% CLS | 30/10368 <1%
I/O Port | 5 I/O Port | 5
I/O Buf | 5 I/O Buf | 5
--Input Buf | 1 --Input Buf | 1
--Output Buf | 4 --Output Buf | 4
--Inout Buf | 0 --Inout Buf | 0
IOLOGIC | 0% IOLOGIC | 0%
BSRAM | 0% BSRAM | 0%
DSP | 0% DSP | 0%
PLL | 0/4 0% PLL | 0/4 0%
DCS | 0/8 0% DCS | 0/8 0%
DQCE | 0/24 0% DQCE | 0/24 0%
OSC | 0/1 0% OSC | 0/1 0%
CLKDIV | 0/8 0% CLKDIV | 0/8 0%
DLLDLY | 0/8 0% DLLDLY | 0/8 0%
DQS | 0/9 0% DQS | 0/9 0%
DHCEN | 0/16 0% DHCEN | 0/16 0%
========================================================== ==========================================================
4. I/O Bank Usage Summary 4. I/O Bank Usage Summary
----------------------- -----------------------
I/O Bank | Usage I/O Bank | Usage
----------------------- -----------------------
bank 0 | 1/29(3%) bank 0 | 1/29(3%)
bank 1 | 4/20(20%) bank 1 | 4/20(20%)
bank 2 | 0/20(0%) bank 2 | 0/20(0%)
bank 3 | 0/32(0%) bank 3 | 0/32(0%)
bank 4 | 0/36(0%) bank 4 | 0/36(0%)
bank 5 | 0/36(0%) bank 5 | 0/36(0%)
bank 6 | 0/18(0%) bank 6 | 0/18(0%)
bank 7 | 0/16(0%) bank 7 | 0/16(0%)
======================= =======================
5. Global Clock Usage Summary 5. Global Clock Usage Summary
------------------------------- -------------------------------
Global Clock | Usage Global Clock | Usage
------------------------------- -------------------------------
PRIMARY | 2/8(25%) PRIMARY | 2/8(25%)
LW | 0/8(0%) LW | 0/8(0%)
GCLK_PIN | 1/8(13%) GCLK_PIN | 1/8(13%)
PLL | 0/4(0%) PLL | 0/4(0%)
CLKDIV | 0/8(0%) CLKDIV | 0/8(0%)
DLLDLY | 0/8(0%) DLLDLY | 0/8(0%)
=============================== ===============================
6. Global Clock Signals 6. Global Clock Signals
------------------------------------------- -------------------------------------------
Signal | Global Clock | Location Signal | Global Clock | Location
------------------------------------------- -------------------------------------------
clock_d | PRIMARY | TR TL BL clock_d | PRIMARY | TR TL BL
newclk | PRIMARY | TR BL newclk | PRIMARY | TR BL
=========================================== ===========================================
7. Pinout by Port Name 7. Pinout by Port Name
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
clock | | H11/0 | Y | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 clock | | H11/0 | Y | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
led[0] | | N16/1 | Y | out | IOT52[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 led[0] | | N16/1 | Y | out | IOT52[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
led[1] | | N14/1 | Y | out | IOT52[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 led[1] | | N14/1 | Y | out | IOT52[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
led[2] | | L14/1 | Y | out | IOT34[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 led[2] | | L14/1 | Y | out | IOT34[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
led[3] | | L16/1 | Y | out | IOT34[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 led[3] | | L16/1 | Y | out | IOT34[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
================================================================================================================================================================================================================== ==================================================================================================================================================================================================================
8. All Package Pins 8. All Package Pins
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
L15/0 | - | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L15/0 | - | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D16/0 | - | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D16/0 | - | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E14/0 | - | in | IOT4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E14/0 | - | in | IOT4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C16/0 | - | in | IOT5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C16/0 | - | in | IOT5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F14/0 | - | in | IOT9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F14/0 | - | in | IOT9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F16/0 | - | in | IOT9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F16/0 | - | in | IOT9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J14/0 | - | in | IOT22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J14/0 | - | in | IOT22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H11/0 | clock | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H11/0 | clock | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L16/1 | led[3] | out | IOT34[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 L16/1 | led[3] | out | IOT34[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
L14/1 | led[2] | out | IOT34[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 L14/1 | led[2] | out | IOT34[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
K13/1 | - | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K13/1 | - | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M14/1 | - | in | IOT40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M14/1 | - | in | IOT40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D14/1 | - | in | IOT44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D14/1 | - | in | IOT44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E15/1 | - | in | IOT44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E15/1 | - | in | IOT44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N16/1 | led[0] | out | IOT52[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 N16/1 | led[0] | out | IOT52[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
N14/1 | led[1] | out | IOT52[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 N14/1 | led[1] | out | IOT52[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T4/4 | - | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T4/4 | - | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T5/4 | - | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T5/4 | - | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
B14/7 | - | in | IOL2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B14/7 | - | in | IOL2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A15/7 | - | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A15/7 | - | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C12/7 | - | in | IOL7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C12/7 | - | in | IOL7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B12/7 | - | in | IOL7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B12/7 | - | in | IOL7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B13/7 | - | in | IOL8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B13/7 | - | in | IOL8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A14/7 | - | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A14/7 | - | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B11/7 | - | in | IOL13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B11/7 | - | in | IOL13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A11/7 | - | in | IOL15[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A11/7 | - | in | IOL15[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D11/7 | - | in | IOL22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D11/7 | - | in | IOL22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E9/6 | - | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E9/6 | - | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E8/6 | - | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E8/6 | - | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T12/2 | - | in | IOR17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T12/2 | - | in | IOR17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T11/2 | - | in | IOR24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T11/2 | - | in | IOR24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M11/2 | - | in | IOR27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M11/2 | - | in | IOR27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T7/3 | - | in | IOR29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T7/3 | - | in | IOR29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P9/3 | - | in | IOR38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P9/3 | - | in | IOR38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N8/3 | - | in | IOR40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N8/3 | - | in | IOR40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L9/3 | - | in | IOR40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L9/3 | - | in | IOR40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P8/3 | - | in | IOR42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P8/3 | - | in | IOR42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N7/3 | - | in | IOR47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N7/3 | - | in | IOR47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N6/3 | - | in | IOR51[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 N6/3 | - | in | IOR51[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P6/3 | - | in | IOR53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 P6/3 | - | in | IOR53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
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<html> <html>
<head> <head>
<title>Timing Analysis Report</title> <title>Timing Analysis Report</title>
</head> </head>
<frameset cols="20%, 80%"> <frameset cols="20%, 80%">
<frame src="seq_light_test_tr_cata.html" name="cataFrame" /> <frame src="seq_light_test_tr_cata.html" name="cataFrame" />
<frame src="seq_light_test_tr_content.html" name="mainFrame"/> <frame src="seq_light_test_tr_content.html" name="mainFrame"/>
</frameset> </frameset>
</html> </html>

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html> <html>
<head> <head>
<title>Timing Report Navigation</title> <title>Timing Report Navigation</title>
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174
gowin/seq_light_test/impl/seq_light_test_process_config.json
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18
gowin/seq_light_test/impl/temp/rtl_parser.result
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[ [
{ {
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32
gowin/seq_light_test/impl/temp/rtl_parser_arg.json
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{ {
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24
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<!DOCTYPE gowin-fpga-project> <!DOCTYPE gowin-fpga-project>
<Project> <Project>
<Template>FPGA</Template> <Template>FPGA</Template>
<Version>5</Version> <Version>5</Version>
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device> <Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
<FileList> <FileList>
<File path="src/seqBlink.v" type="file.verilog" enable="1"/> <File path="src/seqBlink.v" type="file.verilog" enable="1"/>
<File path="src/seqBlinkTB.v" type="file.verilog" enable="0"/> <File path="src/seqBlinkTB.v" type="file.verilog" enable="0"/>
<File path="src/seq_light_test.cst" type="file.cst" enable="1"/> <File path="src/seq_light_test.cst" type="file.cst" enable="1"/>
</FileList> </FileList>
</Project> </Project>

48
gowin/seq_light_test/seq_light_test.gprj.user
View File

@ -1,24 +1,24 @@
<?xml version="1" encoding="UTF-8"?> <?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData> <!DOCTYPE ProjectUserData>
<UserConfig> <UserConfig>
<Version>1.0</Version> <Version>1.0</Version>
<FlowState> <FlowState>
<Process ID="Synthesis" State="2"/> <Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="2"/> <Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/> <Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/> <Process ID="Rtl_Gao" State="2"/>
</FlowState> </FlowState>
<ResultFileList> <ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/seq_light_test.vg"/> <ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/seq_light_test.vg"/>
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/seq_light_test.fs"/> <ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/seq_light_test.fs"/>
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/seq_light_test.pin.html"/> <ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/seq_light_test.pin.html"/>
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/seq_light_test.db"/> <ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/seq_light_test.db"/>
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/seq_light_test.power.html"/> <ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/seq_light_test.power.html"/>
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/seq_light_test.rpt.html"/> <ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/seq_light_test.rpt.html"/>
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/seq_light_test.timing_paths"/> <ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/seq_light_test.timing_paths"/>
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/seq_light_test.tr.html"/> <ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/seq_light_test.tr.html"/>
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/seq_light_test_syn.rpt.html"/> <ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/seq_light_test_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/seq_light_test_syn_rsc.xml"/> <ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/seq_light_test_syn_rsc.xml"/>
</ResultFileList> </ResultFileList>
<Ui>000000ff00000001fd00000002000000000000018e00000260fc0200000001fc00000063000002600000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000078000000142fc0100000001fc00000000000007800000009b00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000007800fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009b00ffffff000005ea0000026000000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000afffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000183ffffffff0000000000000000</Ui> <Ui>000000ff00000001fd00000002000000000000018e00000260fc0200000001fc00000063000002600000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000078000000142fc0100000001fc00000000000007800000009b00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000007800fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009b00ffffff000005ea0000026000000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000afffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000183ffffffff0000000000000000</Ui>
</UserConfig> </UserConfig>

72
gowin/seq_light_test/src/seqBlink.v
View File

@ -1,36 +1,36 @@
module seqBlink ( module seqBlink (
input clock, input clock,
output reg [3:0] led output reg [3:0] led
); );
reg [2:0] fsm = 0; reg [2:0] fsm = 0;
reg [31:0] clkcnt = 0; reg [31:0] clkcnt = 0;
reg newclk = 0; reg newclk = 0;
always@(posedge clock) begin always@(posedge clock) begin
clkcnt <= clkcnt + 1'b1; clkcnt <= clkcnt + 1'b1;
if (clkcnt > 9_000_000) begin if (clkcnt > 9_000_000) begin
clkcnt <= 0; clkcnt <= 0;
newclk <= ~newclk; newclk <= ~newclk;
end end
end end
always@(posedge newclk) begin always@(posedge newclk) begin
if (fsm == 3'd6) begin if (fsm == 3'd6) begin
fsm <= 0; fsm <= 0;
end else begin end else begin
fsm <= fsm + 1; fsm <= fsm + 1;
end end
case (fsm) case (fsm)
3'b000 : led <= 4'b0111; 3'b000 : led <= 4'b0111;
3'b001 : led <= 4'b1011; 3'b001 : led <= 4'b1011;
3'b010 : led <= 4'b1101; 3'b010 : led <= 4'b1101;
3'b011 : led <= 4'b1110; 3'b011 : led <= 4'b1110;
3'b100 : led <= 4'b1101; 3'b100 : led <= 4'b1101;
3'b101 : led <= 4'b1011; 3'b101 : led <= 4'b1011;
3'b110 : led <= 4'b0111; 3'b110 : led <= 4'b0111;
default: led <= 4'b0000; default: led <= 4'b0000;
endcase endcase
end end
endmodule endmodule

46
gowin/seq_light_test/src/seqBlinkTB.v
View File

@ -1,24 +1,24 @@
module seqBlinkTB(); module seqBlinkTB();
reg clock; reg clock;
wire [3:0] leds; wire [3:0] leds;
seqBlink uut(clock, leds); seqBlink uut(clock, leds);
initial begin initial begin
clock = 0; clock = 0;
end end
always begin always begin
clock = ~clock; #5; clock = ~clock; #5;
end end
initial begin initial begin
$dumpfile("lab5v.vcd"); $dumpfile("lab5v.vcd");
$dumpvars; $dumpvars;
#100; #100;
$finish; $finish;
end end
endmodule endmodule

38
gowin/seq_light_test/src/seq_light_test.cst
View File

@ -1,19 +1,19 @@
//Copyright (C)2014-2024 Gowin Semiconductor Corporation. //Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved. //All rights reserved.
//File Title: Physical Constraints file //File Title: Physical Constraints file
//Tool Version: V1.9.9.03 Education (64-bit) //Tool Version: V1.9.9.03 Education (64-bit)
//Part Number: GW2A-LV18PG256C8/I7 //Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18 //Device: GW2A-18
//Device Version: C //Device Version: C
//Created Time: Sun 07 07 15:26:30 2024 //Created Time: Sun 07 07 15:26:30 2024
IO_LOC "led[3]" L16; IO_LOC "led[3]" L16;
IO_PORT "led[3]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; IO_PORT "led[3]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "led[2]" L14; IO_LOC "led[2]" L14;
IO_PORT "led[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; IO_PORT "led[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "led[1]" N14; IO_LOC "led[1]" N14;
IO_PORT "led[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; IO_PORT "led[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "led[0]" N16; IO_LOC "led[0]" N16;
IO_PORT "led[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8; IO_PORT "led[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "clock" H11; IO_LOC "clock" H11;
IO_PORT "clock" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8; IO_PORT "clock" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;

76
iverilog/lab2/HammingDistance/ham.vcd → iverilog/tobb/lab2/HammingDistance/ham.vcd
View File

@ -1,38 +1,38 @@
$date $date
Wed Nov 6 15:42:14 2024 Wed Nov 6 15:42:14 2024
$end $end
$version $version
Icarus Verilog Icarus Verilog
$end $end
$timescale $timescale
1s 1s
$end $end
$scope module htb $end $scope module htb $end
$var wire 4 ! hammingValue [3:0] $end $var wire 4 ! hammingValue [3:0] $end
$var reg 8 " value1 [7:0] $end $var reg 8 " value1 [7:0] $end
$var reg 8 # value2 [7:0] $end $var reg 8 # value2 [7:0] $end
$scope module uut $end $scope module uut $end
$var wire 8 $ value1 [7:0] $end $var wire 8 $ value1 [7:0] $end
$var wire 8 % value2 [7:0] $end $var wire 8 % value2 [7:0] $end
$var reg 4 & hammingValue [3:0] $end $var reg 4 & hammingValue [3:0] $end
$var integer 32 ' i [31:0] $end $var integer 32 ' i [31:0] $end
$upscope $end $upscope $end
$upscope $end $upscope $end
$enddefinitions $end $enddefinitions $end
#0 #0
$dumpvars $dumpvars
b1000 ' b1000 '
b100 & b100 &
b10111111 % b10111111 %
b10110000 $ b10110000 $
b10111111 # b10111111 #
b10110000 " b10110000 "
b100 ! b100 !
$end $end
#10 #10
b1000 ' b1000 '
b0 ! b0 !
b0 & b0 &
b10111111 " b10111111 "
b10111111 $ b10111111 $
#20 #20

166
iverilog/lab2/HammingDistance/hamming → iverilog/tobb/lab2/HammingDistance/hamming
View File

@ -1,83 +1,83 @@
#! /usr/bin/vvp #! /usr/bin/vvp
:ivl_version "11.0 (stable)"; :ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL"; :ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0; :vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55be1d5c3f90 .scope module, "htb" "htb" 2 1; S_0x55be1d5c3f90 .scope module, "htb" "htb" 2 1;
.timescale 0 0; .timescale 0 0;
v0x55be1d5d5ae0_0 .net "hammingValue", 3 0, v0x55be1d58ab00_0; 1 drivers v0x55be1d5d5ae0_0 .net "hammingValue", 3 0, v0x55be1d58ab00_0; 1 drivers
v0x55be1d5d5bd0_0 .var "value1", 7 0; v0x55be1d5d5bd0_0 .var "value1", 7 0;
v0x55be1d5d5ca0_0 .var "value2", 7 0; v0x55be1d5d5ca0_0 .var "value2", 7 0;
S_0x55be1d5c4120 .scope module, "uut" "hamming" 2 7, 3 1 0, S_0x55be1d5c3f90; S_0x55be1d5c4120 .scope module, "uut" "hamming" 2 7, 3 1 0, S_0x55be1d5c3f90;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 8 "value1"; .port_info 0 /INPUT 8 "value1";
.port_info 1 /INPUT 8 "value2"; .port_info 1 /INPUT 8 "value2";
.port_info 2 /OUTPUT 4 "hammingValue"; .port_info 2 /OUTPUT 4 "hammingValue";
v0x55be1d58ab00_0 .var "hammingValue", 3 0; v0x55be1d58ab00_0 .var "hammingValue", 3 0;
v0x55be1d58af10_0 .var/i "i", 31 0; v0x55be1d58af10_0 .var/i "i", 31 0;
v0x55be1d5d58c0_0 .net "value1", 7 0, v0x55be1d5d5bd0_0; 1 drivers v0x55be1d5d58c0_0 .net "value1", 7 0, v0x55be1d5d5bd0_0; 1 drivers
v0x55be1d5d5980_0 .net "value2", 7 0, v0x55be1d5d5ca0_0; 1 drivers v0x55be1d5d5980_0 .net "value2", 7 0, v0x55be1d5d5ca0_0; 1 drivers
E_0x55be1d589690 .event edge, v0x55be1d5d58c0_0, v0x55be1d5d5980_0, v0x55be1d58ab00_0; E_0x55be1d589690 .event edge, v0x55be1d5d58c0_0, v0x55be1d5d5980_0, v0x55be1d58ab00_0;
.scope S_0x55be1d5c4120; .scope S_0x55be1d5c4120;
T_0 ; T_0 ;
%pushi/vec4 0, 0, 32; %pushi/vec4 0, 0, 32;
%store/vec4 v0x55be1d58af10_0, 0, 32; %store/vec4 v0x55be1d58af10_0, 0, 32;
%end; %end;
.thread T_0; .thread T_0;
.scope S_0x55be1d5c4120; .scope S_0x55be1d5c4120;
T_1 ; T_1 ;
%wait E_0x55be1d589690; %wait E_0x55be1d589690;
%pushi/vec4 0, 0, 4; %pushi/vec4 0, 0, 4;
%store/vec4 v0x55be1d58ab00_0, 0, 4; %store/vec4 v0x55be1d58ab00_0, 0, 4;
%pushi/vec4 0, 0, 32; %pushi/vec4 0, 0, 32;
%store/vec4 v0x55be1d58af10_0, 0, 32; %store/vec4 v0x55be1d58af10_0, 0, 32;
T_1.0 ; T_1.0 ;
%load/vec4 v0x55be1d58af10_0; %load/vec4 v0x55be1d58af10_0;
%cmpi/s 8, 0, 32; %cmpi/s 8, 0, 32;
%jmp/0xz T_1.1, 5; %jmp/0xz T_1.1, 5;
%load/vec4 v0x55be1d5d58c0_0; %load/vec4 v0x55be1d5d58c0_0;
%load/vec4 v0x55be1d58af10_0; %load/vec4 v0x55be1d58af10_0;
%part/s 1; %part/s 1;
%load/vec4 v0x55be1d5d5980_0; %load/vec4 v0x55be1d5d5980_0;
%load/vec4 v0x55be1d58af10_0; %load/vec4 v0x55be1d58af10_0;
%part/s 1; %part/s 1;
%cmp/ne; %cmp/ne;
%jmp/0xz T_1.2, 4; %jmp/0xz T_1.2, 4;
%load/vec4 v0x55be1d58ab00_0; %load/vec4 v0x55be1d58ab00_0;
%addi 1, 0, 4; %addi 1, 0, 4;
%store/vec4 v0x55be1d58ab00_0, 0, 4; %store/vec4 v0x55be1d58ab00_0, 0, 4;
T_1.2 ; T_1.2 ;
%load/vec4 v0x55be1d58af10_0; %load/vec4 v0x55be1d58af10_0;
%addi 1, 0, 32; %addi 1, 0, 32;
%store/vec4 v0x55be1d58af10_0, 0, 32; %store/vec4 v0x55be1d58af10_0, 0, 32;
%jmp T_1.0; %jmp T_1.0;
T_1.1 ; T_1.1 ;
%jmp T_1; %jmp T_1;
.thread T_1, $push; .thread T_1, $push;
.scope S_0x55be1d5c3f90; .scope S_0x55be1d5c3f90;
T_2 ; T_2 ;
%vpi_call 2 14 "$dumpfile", "ham.vcd" {0 0 0}; %vpi_call 2 14 "$dumpfile", "ham.vcd" {0 0 0};
%vpi_call 2 15 "$dumpvars" {0 0 0}; %vpi_call 2 15 "$dumpvars" {0 0 0};
%pushi/vec4 176, 0, 8; %pushi/vec4 176, 0, 8;
%store/vec4 v0x55be1d5d5bd0_0, 0, 8; %store/vec4 v0x55be1d5d5bd0_0, 0, 8;
%pushi/vec4 191, 0, 8; %pushi/vec4 191, 0, 8;
%store/vec4 v0x55be1d5d5ca0_0, 0, 8; %store/vec4 v0x55be1d5d5ca0_0, 0, 8;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 191, 0, 8; %pushi/vec4 191, 0, 8;
%store/vec4 v0x55be1d5d5bd0_0, 0, 8; %store/vec4 v0x55be1d5d5bd0_0, 0, 8;
%pushi/vec4 191, 0, 8; %pushi/vec4 191, 0, 8;
%store/vec4 v0x55be1d5d5ca0_0, 0, 8; %store/vec4 v0x55be1d5d5ca0_0, 0, 8;
%delay 10, 0; %delay 10, 0;
%vpi_call 2 18 "$display", v0x55be1d5d5ae0_0 {0 0 0}; %vpi_call 2 18 "$display", v0x55be1d5d5ae0_0 {0 0 0};
%end; %end;
.thread T_2; .thread T_2;
# The file index is used to find the file name in the following table. # The file index is used to find the file name in the following table.
:file_names 4; :file_names 4;
"N/A"; "N/A";
"<interactive>"; "<interactive>";
"htb.v"; "htb.v";
"hamming.v"; "hamming.v";

32
iverilog/lab2/HammingDistance/hamming.v → iverilog/tobb/lab2/HammingDistance/hamming.v
View File

@ -1,17 +1,17 @@
module hamming ( module hamming (
input[7:0] value1, input[7:0] value1,
input[7:0] value2, input[7:0] value2,
output reg[3:0] hammingValue output reg[3:0] hammingValue
); );
integer i = 0; integer i = 0;
always @(*) begin always @(*) begin
hammingValue = 0; hammingValue = 0;
for(i = 0; i < 8; i = i+1) begin for(i = 0; i < 8; i = i+1) begin
if (value1[i] != value2[i]) begin if (value1[i] != value2[i]) begin
hammingValue = hammingValue + 1; hammingValue = hammingValue + 1;
end end
end end
end end
endmodule endmodule

38
iverilog/lab2/HammingDistance/htb.v → iverilog/tobb/lab2/HammingDistance/htb.v
View File

@ -1,20 +1,20 @@
module htb (); module htb ();
reg [7:0] value1; reg [7:0] value1;
reg [7:0] value2; reg [7:0] value2;
wire [3:0] hammingValue; wire [3:0] hammingValue;
hamming uut ( hamming uut (
.value1(value1), .value1(value1),
.value2(value2), .value2(value2),
.hammingValue(hammingValue) .hammingValue(hammingValue)
); );
initial begin initial begin
$dumpfile("ham.vcd"); $dumpfile("ham.vcd");
$dumpvars; $dumpvars;
value1 = 8'hB0; value2 = 8'hBF; #10; value1 = 8'hB0; value2 = 8'hBF; #10;
value1 = 8'hBF; value2 = 8'hBF; #10; value1 = 8'hBF; value2 = 8'hBF; #10;
$display(hammingValue); $display(hammingValue);
end end
endmodule endmodule

168
iverilog/lab2/fdmp.vcd → iverilog/tobb/lab2/fdmp.vcd
View File

@ -1,84 +1,84 @@
$date $date
Tue Oct 8 14:05:40 2024 Tue Oct 8 14:05:40 2024
$end $end
$version $version
Icarus Verilog Icarus Verilog
$end $end
$timescale $timescale
1s 1s
$end $end
$scope module fulladdertb $end $scope module fulladdertb $end
$var wire 1 ! w2 $end $var wire 1 ! w2 $end
$var wire 1 " w1 $end $var wire 1 " w1 $end
$var reg 1 # r1 $end $var reg 1 # r1 $end
$var reg 1 $ r2 $end $var reg 1 $ r2 $end
$var reg 1 % r3 $end $var reg 1 % r3 $end
$scope module uut $end $scope module uut $end
$var wire 1 # A $end $var wire 1 # A $end
$var wire 1 $ B $end $var wire 1 $ B $end
$var wire 1 % Cin $end $var wire 1 % Cin $end
$var wire 1 ! Cout $end $var wire 1 ! Cout $end
$var wire 1 " S $end $var wire 1 " S $end
$var wire 1 & AxB $end $var wire 1 & AxB $end
$var wire 1 ' AnB2 $end $var wire 1 ' AnB2 $end
$var wire 1 ( AnB1 $end $var wire 1 ( AnB1 $end
$scope module h1 $end $scope module h1 $end
$var wire 1 # A $end $var wire 1 # A $end
$var wire 1 $ B $end $var wire 1 $ B $end
$var wire 1 ' C $end $var wire 1 ' C $end
$var wire 1 & S $end $var wire 1 & S $end
$upscope $end $upscope $end
$scope module h2 $end $scope module h2 $end
$var wire 1 & A $end $var wire 1 & A $end
$var wire 1 % B $end $var wire 1 % B $end
$var wire 1 ( C $end $var wire 1 ( C $end
$var wire 1 " S $end $var wire 1 " S $end
$upscope $end $upscope $end
$upscope $end $upscope $end
$upscope $end $upscope $end
$enddefinitions $end $enddefinitions $end
#0 #0
$dumpvars $dumpvars
0( 0(
0' 0'
0& 0&
0% 0%
0$ 0$
0# 0#
0" 0"
0! 0!
$end $end
#10 #10
1" 1"
1% 1%
#20 #20
1& 1&
0% 0%
1$ 1$
#30 #30
1! 1!
0" 0"
1( 1(
1% 1%
#40 #40
0! 0!
1" 1"
0( 0(
0% 0%
0$ 0$
1# 1#
#50 #50
1! 1!
0" 0"
1( 1(
1% 1%
#60 #60
0( 0(
0& 0&
1' 1'
0% 0%
1$ 1$
#70 #70
1" 1"
1% 1%
#80 #80

254
iverilog/lab2/fulladder → iverilog/tobb/lab2/fulladder
View File

@ -1,127 +1,127 @@
#! /usr/bin/vvp #! /usr/bin/vvp
:ivl_version "11.0 (stable)"; :ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL"; :ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0; :vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x557fe3a27ae0 .scope module, "fulladdertb" "fulladdertb" 2 1; S_0x557fe3a27ae0 .scope module, "fulladdertb" "fulladdertb" 2 1;
.timescale 0 0; .timescale 0 0;
v0x557fe3a3b940_0 .var "r1", 0 0; v0x557fe3a3b940_0 .var "r1", 0 0;
v0x557fe3a3ba30_0 .var "r2", 0 0; v0x557fe3a3ba30_0 .var "r2", 0 0;
v0x557fe3a3bb40_0 .var "r3", 0 0; v0x557fe3a3bb40_0 .var "r3", 0 0;
v0x557fe3a3bc30_0 .net "w1", 0 0, L_0x557fe3a3bf40; 1 drivers v0x557fe3a3bc30_0 .net "w1", 0 0, L_0x557fe3a3bf40; 1 drivers
v0x557fe3a3bd20_0 .net "w2", 0 0, L_0x557fe3a3c1a0; 1 drivers v0x557fe3a3bd20_0 .net "w2", 0 0, L_0x557fe3a3c1a0; 1 drivers
S_0x557fe3a27c70 .scope module, "uut" "fullAdder" 2 6, 3 1 0, S_0x557fe3a27ae0; S_0x557fe3a27c70 .scope module, "uut" "fullAdder" 2 6, 3 1 0, S_0x557fe3a27ae0;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Cin"; .port_info 2 /INPUT 1 "Cin";
.port_info 3 /OUTPUT 1 "S"; .port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "Cout"; .port_info 4 /OUTPUT 1 "Cout";
L_0x557fe3a3c1a0 .functor OR 1, L_0x557fe3a3c080, L_0x557fe3a3be80, C4<0>, C4<0>; L_0x557fe3a3c1a0 .functor OR 1, L_0x557fe3a3c080, L_0x557fe3a3be80, C4<0>, C4<0>;
v0x557fe3a3b290_0 .net "A", 0 0, v0x557fe3a3b940_0; 1 drivers v0x557fe3a3b290_0 .net "A", 0 0, v0x557fe3a3b940_0; 1 drivers
v0x557fe3a3b350_0 .net "AnB1", 0 0, L_0x557fe3a3c080; 1 drivers v0x557fe3a3b350_0 .net "AnB1", 0 0, L_0x557fe3a3c080; 1 drivers
v0x557fe3a3b420_0 .net "AnB2", 0 0, L_0x557fe3a3be80; 1 drivers v0x557fe3a3b420_0 .net "AnB2", 0 0, L_0x557fe3a3be80; 1 drivers
v0x557fe3a3b520_0 .net "AxB", 0 0, L_0x557fe3a3be10; 1 drivers v0x557fe3a3b520_0 .net "AxB", 0 0, L_0x557fe3a3be10; 1 drivers
v0x557fe3a3b610_0 .net "B", 0 0, v0x557fe3a3ba30_0; 1 drivers v0x557fe3a3b610_0 .net "B", 0 0, v0x557fe3a3ba30_0; 1 drivers
v0x557fe3a3b700_0 .net "Cin", 0 0, v0x557fe3a3bb40_0; 1 drivers v0x557fe3a3b700_0 .net "Cin", 0 0, v0x557fe3a3bb40_0; 1 drivers
v0x557fe3a3b7a0_0 .net "Cout", 0 0, L_0x557fe3a3c1a0; alias, 1 drivers v0x557fe3a3b7a0_0 .net "Cout", 0 0, L_0x557fe3a3c1a0; alias, 1 drivers
v0x557fe3a3b840_0 .net "S", 0 0, L_0x557fe3a3bf40; alias, 1 drivers v0x557fe3a3b840_0 .net "S", 0 0, L_0x557fe3a3bf40; alias, 1 drivers
S_0x557fe3a22df0 .scope module, "h1" "halfadder" 3 9, 4 1 0, S_0x557fe3a27c70; S_0x557fe3a22df0 .scope module, "h1" "halfadder" 3 9, 4 1 0, S_0x557fe3a27c70;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S"; .port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C"; .port_info 3 /OUTPUT 1 "C";
L_0x557fe3a3be10 .functor XOR 1, v0x557fe3a3b940_0, v0x557fe3a3ba30_0, C4<0>, C4<0>; L_0x557fe3a3be10 .functor XOR 1, v0x557fe3a3b940_0, v0x557fe3a3ba30_0, C4<0>, C4<0>;
L_0x557fe3a3be80 .functor AND 1, v0x557fe3a3b940_0, v0x557fe3a3ba30_0, C4<1>, C4<1>; L_0x557fe3a3be80 .functor AND 1, v0x557fe3a3b940_0, v0x557fe3a3ba30_0, C4<1>, C4<1>;
v0x557fe3a23070_0 .net "A", 0 0, v0x557fe3a3b940_0; alias, 1 drivers v0x557fe3a23070_0 .net "A", 0 0, v0x557fe3a3b940_0; alias, 1 drivers
v0x557fe3a3a970_0 .net "B", 0 0, v0x557fe3a3ba30_0; alias, 1 drivers v0x557fe3a3a970_0 .net "B", 0 0, v0x557fe3a3ba30_0; alias, 1 drivers
v0x557fe3a3aa30_0 .net "C", 0 0, L_0x557fe3a3be80; alias, 1 drivers v0x557fe3a3aa30_0 .net "C", 0 0, L_0x557fe3a3be80; alias, 1 drivers
v0x557fe3a3ab00_0 .net "S", 0 0, L_0x557fe3a3be10; alias, 1 drivers v0x557fe3a3ab00_0 .net "S", 0 0, L_0x557fe3a3be10; alias, 1 drivers
S_0x557fe3a3ac70 .scope module, "h2" "halfadder" 3 10, 4 1 0, S_0x557fe3a27c70; S_0x557fe3a3ac70 .scope module, "h2" "halfadder" 3 10, 4 1 0, S_0x557fe3a27c70;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S"; .port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C"; .port_info 3 /OUTPUT 1 "C";
L_0x557fe3a3bf40 .functor XOR 1, L_0x557fe3a3be10, v0x557fe3a3bb40_0, C4<0>, C4<0>; L_0x557fe3a3bf40 .functor XOR 1, L_0x557fe3a3be10, v0x557fe3a3bb40_0, C4<0>, C4<0>;
L_0x557fe3a3c080 .functor AND 1, L_0x557fe3a3be10, v0x557fe3a3bb40_0, C4<1>, C4<1>; L_0x557fe3a3c080 .functor AND 1, L_0x557fe3a3be10, v0x557fe3a3bb40_0, C4<1>, C4<1>;
v0x557fe3a3aee0_0 .net "A", 0 0, L_0x557fe3a3be10; alias, 1 drivers v0x557fe3a3aee0_0 .net "A", 0 0, L_0x557fe3a3be10; alias, 1 drivers
v0x557fe3a3afb0_0 .net "B", 0 0, v0x557fe3a3bb40_0; alias, 1 drivers v0x557fe3a3afb0_0 .net "B", 0 0, v0x557fe3a3bb40_0; alias, 1 drivers
v0x557fe3a3b050_0 .net "C", 0 0, L_0x557fe3a3c080; alias, 1 drivers v0x557fe3a3b050_0 .net "C", 0 0, L_0x557fe3a3c080; alias, 1 drivers
v0x557fe3a3b120_0 .net "S", 0 0, L_0x557fe3a3bf40; alias, 1 drivers v0x557fe3a3b120_0 .net "S", 0 0, L_0x557fe3a3bf40; alias, 1 drivers
.scope S_0x557fe3a27ae0; .scope S_0x557fe3a27ae0;
T_0 ; T_0 ;
%vpi_call 2 15 "$dumpfile", "fdmp.vcd" {0 0 0}; %vpi_call 2 15 "$dumpfile", "fdmp.vcd" {0 0 0};
%vpi_call 2 16 "$dumpvars" {0 0 0}; %vpi_call 2 16 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1; %store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1; %store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1; %store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1; %store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1; %store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1; %store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1; %store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1; %store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1; %store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1; %store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1; %store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1; %store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1; %store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1; %store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1; %store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1; %store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1; %store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1; %store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1; %store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1; %store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1; %store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1; %store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1; %store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1; %store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0; %delay 10, 0;
%vpi_call 2 25 "$display", v0x557fe3a3bc30_0 {0 0 0}; %vpi_call 2 25 "$display", v0x557fe3a3bc30_0 {0 0 0};
%vpi_call 2 26 "$display", v0x557fe3a3bd20_0 {0 0 0}; %vpi_call 2 26 "$display", v0x557fe3a3bd20_0 {0 0 0};
%end; %end;
.thread T_0; .thread T_0;
# The file index is used to find the file name in the following table. # The file index is used to find the file name in the following table.
:file_names 5; :file_names 5;
"N/A"; "N/A";
"<interactive>"; "<interactive>";
"fulladdertb.v"; "fulladdertb.v";
"fulladder.v"; "fulladder.v";
"halfadder.v"; "halfadder.v";

24
iverilog/lab2/fulladder.v → iverilog/tobb/lab2/fulladder.v
View File

@ -1,13 +1,13 @@
module fullAdder ( module fullAdder (
input A, input A,
input B, input B,
input Cin, input Cin,
output S, output S,
output Cout output Cout
); );
wire AxB, AnB1, AnB2; wire AxB, AnB1, AnB2;
halfadder h1(A, B, AxB, AnB2); halfadder h1(A, B, AxB, AnB2);
halfadder h2(AxB, Cin, S, AnB1); halfadder h2(AxB, Cin, S, AnB1);
or o1(Cout, AnB1, AnB2); or o1(Cout, AnB1, AnB2);
endmodule endmodule

56
iverilog/lab2/fulladdertb.v → iverilog/tobb/lab2/fulladdertb.v
View File

@ -1,29 +1,29 @@
module fulladdertb (); module fulladdertb ();
reg r1, r2, r3; reg r1, r2, r3;
wire w1, w2; wire w1, w2;
fullAdder uut( fullAdder uut(
.A(r1), .A(r1),
.B(r2), .B(r2),
.Cin(r3), .Cin(r3),
.S(w1), .S(w1),
.Cout(w2) .Cout(w2)
); );
initial begin initial begin
$dumpfile("fdmp.vcd"); $dumpfile("fdmp.vcd");
$dumpvars; $dumpvars;
r1 = 0; r2 = 0; r3 = 0; #10 r1 = 0; r2 = 0; r3 = 0; #10
r1 = 0; r2 = 0; r3 = 1; #10 r1 = 0; r2 = 0; r3 = 1; #10
r1 = 0; r2 = 1; r3 = 0; #10 r1 = 0; r2 = 1; r3 = 0; #10
r1 = 0; r2 = 1; r3 = 1; #10 r1 = 0; r2 = 1; r3 = 1; #10
r1 = 1; r2 = 0; r3 = 0; #10 r1 = 1; r2 = 0; r3 = 0; #10
r1 = 1; r2 = 0; r3 = 1; #10 r1 = 1; r2 = 0; r3 = 1; #10
r1 = 1; r2 = 1; r3 = 0; #10 r1 = 1; r2 = 1; r3 = 0; #10
r1 = 1; r2 = 1; r3 = 1; #10 r1 = 1; r2 = 1; r3 = 1; #10
$display(w1); $display(w1);
$display(w2); $display(w2);
end end
endmodule endmodule

80
iverilog/lab2/hadmp.vcd → iverilog/tobb/lab2/hadmp.vcd
View File

@ -1,40 +1,40 @@
$date $date
Tue Oct 8 10:23:08 2024 Tue Oct 8 10:23:08 2024
$end $end
$version $version
Icarus Verilog Icarus Verilog
$end $end
$timescale $timescale
1s 1s
$end $end
$scope module halfaddertb $end $scope module halfaddertb $end
$var wire 1 ! S $end $var wire 1 ! S $end
$var wire 1 " C $end $var wire 1 " C $end
$var reg 1 # A $end $var reg 1 # A $end
$var reg 1 $ B $end $var reg 1 $ B $end
$scope module uut $end $scope module uut $end
$var wire 1 # A $end $var wire 1 # A $end
$var wire 1 $ B $end $var wire 1 $ B $end
$var wire 1 " C $end $var wire 1 " C $end
$var wire 1 ! S $end $var wire 1 ! S $end
$upscope $end $upscope $end
$upscope $end $upscope $end
$enddefinitions $end $enddefinitions $end
#0 #0
$dumpvars $dumpvars
0$ 0$
0# 0#
0" 0"
0! 0!
$end $end
#10 #10
1! 1!
1$ 1$
#20 #20
0$ 0$
1# 1#
#30 #30
0! 0!
1" 1"
1$ 1$
#40 #40

118
iverilog/lab2/halfadder → iverilog/tobb/lab2/halfadder
View File

@ -1,59 +1,59 @@
#! /usr/bin/vvp #! /usr/bin/vvp
:ivl_version "11.0 (stable)"; :ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL"; :ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0; :vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x5583f1e33260 .scope module, "halfaddertb" "halfaddertb" 2 1; S_0x5583f1e33260 .scope module, "halfaddertb" "halfaddertb" 2 1;
.timescale 0 0; .timescale 0 0;
v0x5583f1e44440_0 .var "A", 0 0; v0x5583f1e44440_0 .var "A", 0 0;
v0x5583f1e44500_0 .var "B", 0 0; v0x5583f1e44500_0 .var "B", 0 0;
v0x5583f1e445d0_0 .net "C", 0 0, L_0x5583f1e44900; 1 drivers v0x5583f1e445d0_0 .net "C", 0 0, L_0x5583f1e44900; 1 drivers
v0x5583f1e446d0_0 .net "S", 0 0, L_0x5583f1e447a0; 1 drivers v0x5583f1e446d0_0 .net "S", 0 0, L_0x5583f1e447a0; 1 drivers
S_0x5583f1e333f0 .scope module, "uut" "halfadder" 2 5, 3 1 0, S_0x5583f1e33260; S_0x5583f1e333f0 .scope module, "uut" "halfadder" 2 5, 3 1 0, S_0x5583f1e33260;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "A"; .port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B"; .port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S"; .port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C"; .port_info 3 /OUTPUT 1 "C";
L_0x5583f1e447a0 .functor XOR 1, v0x5583f1e44440_0, v0x5583f1e44500_0, C4<0>, C4<0>; L_0x5583f1e447a0 .functor XOR 1, v0x5583f1e44440_0, v0x5583f1e44500_0, C4<0>, C4<0>;
L_0x5583f1e44900 .functor AND 1, v0x5583f1e44440_0, v0x5583f1e44500_0, C4<1>, C4<1>; L_0x5583f1e44900 .functor AND 1, v0x5583f1e44440_0, v0x5583f1e44500_0, C4<1>, C4<1>;
v0x5583f1dfbc00_0 .net "A", 0 0, v0x5583f1e44440_0; 1 drivers v0x5583f1dfbc00_0 .net "A", 0 0, v0x5583f1e44440_0; 1 drivers
v0x5583f1e44140_0 .net "B", 0 0, v0x5583f1e44500_0; 1 drivers v0x5583f1e44140_0 .net "B", 0 0, v0x5583f1e44500_0; 1 drivers
v0x5583f1e44200_0 .net "C", 0 0, L_0x5583f1e44900; alias, 1 drivers v0x5583f1e44200_0 .net "C", 0 0, L_0x5583f1e44900; alias, 1 drivers
v0x5583f1e442d0_0 .net "S", 0 0, L_0x5583f1e447a0; alias, 1 drivers v0x5583f1e442d0_0 .net "S", 0 0, L_0x5583f1e447a0; alias, 1 drivers
.scope S_0x5583f1e33260; .scope S_0x5583f1e33260;
T_0 ; T_0 ;
%vpi_call 2 10 "$dumpfile", "hadmp.vcd" {0 0 0}; %vpi_call 2 10 "$dumpfile", "hadmp.vcd" {0 0 0};
%vpi_call 2 11 "$dumpvars" {0 0 0}; %vpi_call 2 11 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x5583f1e44440_0, 0, 1; %store/vec4 v0x5583f1e44440_0, 0, 1;
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x5583f1e44500_0, 0, 1; %store/vec4 v0x5583f1e44500_0, 0, 1;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x5583f1e44440_0, 0, 1; %store/vec4 v0x5583f1e44440_0, 0, 1;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x5583f1e44500_0, 0, 1; %store/vec4 v0x5583f1e44500_0, 0, 1;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x5583f1e44440_0, 0, 1; %store/vec4 v0x5583f1e44440_0, 0, 1;
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x5583f1e44500_0, 0, 1; %store/vec4 v0x5583f1e44500_0, 0, 1;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x5583f1e44440_0, 0, 1; %store/vec4 v0x5583f1e44440_0, 0, 1;
%pushi/vec4 1, 0, 1; %pushi/vec4 1, 0, 1;
%store/vec4 v0x5583f1e44500_0, 0, 1; %store/vec4 v0x5583f1e44500_0, 0, 1;
%delay 10, 0; %delay 10, 0;
%end; %end;
.thread T_0; .thread T_0;
# The file index is used to find the file name in the following table. # The file index is used to find the file name in the following table.
:file_names 4; :file_names 4;
"N/A"; "N/A";
"<interactive>"; "<interactive>";
"halfaddertb.v"; "halfaddertb.v";
"halfadder.v"; "halfadder.v";

16
iverilog/lab2/halfadder.v → iverilog/tobb/lab2/halfadder.v
View File

@ -1,9 +1,9 @@
module halfadder ( module halfadder (
input A, input A,
input B, input B,
output S, output S,
output C output C
); );
xor x1(S, A, B); xor x1(S, A, B);
and a1(C, A, B); and a1(C, A, B);
endmodule endmodule

34
iverilog/lab2/halfaddertb.v → iverilog/tobb/lab2/halfaddertb.v
View File

@ -1,18 +1,18 @@
module halfaddertb (); module halfaddertb ();
reg A, B; reg A, B;
wire S, C; wire S, C;
halfadder uut( halfadder uut(
.A(A), .B(B), .S(S), .C(C) .A(A), .B(B), .S(S), .C(C)
); );
initial begin initial begin
$dumpfile("hadmp.vcd"); $dumpfile("hadmp.vcd");
$dumpvars; $dumpvars;
A = 1'b0; B = 1'b0; #10; A = 1'b0; B = 1'b0; #10;
A = 1'b0; B = 1'b1; #10; A = 1'b0; B = 1'b1; #10;
A = 1'b1; B = 1'b0; #10; A = 1'b1; B = 1'b0; #10;
A = 1'b1; B = 1'b1; #10; A = 1'b1; B = 1'b1; #10;
end end
endmodule endmodule

404
tetirs/a.out → iverilog/tobb/lab7tetris/a.out
View File

@ -1,202 +1,202 @@
#! /usr/bin/vvp #! /usr/bin/vvp
:ivl_version "11.0 (stable)"; :ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL"; :ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0; :vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; :vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x5555993ec6a0 .scope module, "tb" "tb" 2 1; S_0x5555993ec6a0 .scope module, "tb" "tb" 2 1;
.timescale 0 0; .timescale 0 0;
v0x5555994063f0_0 .net "bitti_mi", 0 0, L_0x5555994068b0; 1 drivers v0x5555994063f0_0 .net "bitti_mi", 0 0, L_0x5555994068b0; 1 drivers
v0x5555994064b0_0 .net "cevrim", 4 0, L_0x5555994067c0; 1 drivers v0x5555994064b0_0 .net "cevrim", 4 0, L_0x5555994067c0; 1 drivers
v0x555599406550_0 .var "clk", 0 0; v0x555599406550_0 .var "clk", 0 0;
v0x555599406650_0 .var "parca", 2 0; v0x555599406650_0 .var "parca", 2 0;
v0x555599406720_0 .net "yukseklik", 4 0, v0x555599406270_0; 1 drivers v0x555599406720_0 .net "yukseklik", 4 0, v0x555599406270_0; 1 drivers
S_0x5555993ec830 .scope module, "uut" "tetris" 2 10, 3 1 0, S_0x5555993ec6a0; S_0x5555993ec830 .scope module, "uut" "tetris" 2 10, 3 1 0, S_0x5555993ec6a0;
.timescale 0 0; .timescale 0 0;
.port_info 0 /INPUT 1 "clk"; .port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 3 "parca"; .port_info 1 /INPUT 3 "parca";
.port_info 2 /OUTPUT 5 "yukseklik"; .port_info 2 /OUTPUT 5 "yukseklik";
.port_info 3 /OUTPUT 5 "cevrim"; .port_info 3 /OUTPUT 5 "cevrim";
.port_info 4 /OUTPUT 1 "bitti_mi"; .port_info 4 /OUTPUT 1 "bitti_mi";
L_0x5555994067c0 .functor BUFZ 5, v0x555599405d00_0, C4<00000>, C4<00000>, C4<00000>; L_0x5555994067c0 .functor BUFZ 5, v0x555599405d00_0, C4<00000>, C4<00000>, C4<00000>;
L_0x7f7b9f218018 .functor BUFT 1, C4<10000>, C4<0>, C4<0>, C4<0>; L_0x7f7b9f218018 .functor BUFT 1, C4<10000>, C4<0>, C4<0>, C4<0>;
v0x5555993ec9e0_0 .net/2u *"_ivl_2", 4 0, L_0x7f7b9f218018; 1 drivers v0x5555993ec9e0_0 .net/2u *"_ivl_2", 4 0, L_0x7f7b9f218018; 1 drivers
v0x555599405b80_0 .net "bitti_mi", 0 0, L_0x5555994068b0; alias, 1 drivers v0x555599405b80_0 .net "bitti_mi", 0 0, L_0x5555994068b0; alias, 1 drivers
v0x555599405c40_0 .net "cevrim", 4 0, L_0x5555994067c0; alias, 1 drivers v0x555599405c40_0 .net "cevrim", 4 0, L_0x5555994067c0; alias, 1 drivers
v0x555599405d00_0 .var "cevrim_r", 4 0; v0x555599405d00_0 .var "cevrim_r", 4 0;
v0x555599405de0_0 .net "clk", 0 0, v0x555599406550_0; 1 drivers v0x555599405de0_0 .net "clk", 0 0, v0x555599406550_0; 1 drivers
v0x555599405ef0_0 .net "parca", 2 0, v0x555599406650_0; 1 drivers v0x555599405ef0_0 .net "parca", 2 0, v0x555599406650_0; 1 drivers
v0x555599405fd0_0 .var "y_0", 4 0; v0x555599405fd0_0 .var "y_0", 4 0;
v0x5555994060b0_0 .var "y_1", 4 0; v0x5555994060b0_0 .var "y_1", 4 0;
v0x555599406190_0 .var "y_2", 4 0; v0x555599406190_0 .var "y_2", 4 0;
v0x555599406270_0 .var "yukseklik", 4 0; v0x555599406270_0 .var "yukseklik", 4 0;
E_0x5555993e7d70 .event posedge, v0x555599405b80_0; E_0x5555993e7d70 .event posedge, v0x555599405b80_0;
E_0x5555993af500 .event posedge, v0x555599405de0_0; E_0x5555993af500 .event posedge, v0x555599405de0_0;
L_0x5555994068b0 .cmp/eq 5, v0x555599405d00_0, L_0x7f7b9f218018; L_0x5555994068b0 .cmp/eq 5, v0x555599405d00_0, L_0x7f7b9f218018;
.scope S_0x5555993ec830; .scope S_0x5555993ec830;
T_0 ; T_0 ;
%pushi/vec4 0, 0, 5; %pushi/vec4 0, 0, 5;
%store/vec4 v0x555599405d00_0, 0, 5; %store/vec4 v0x555599405d00_0, 0, 5;
%pushi/vec4 0, 0, 5; %pushi/vec4 0, 0, 5;
%store/vec4 v0x555599405fd0_0, 0, 5; %store/vec4 v0x555599405fd0_0, 0, 5;
%pushi/vec4 0, 0, 5; %pushi/vec4 0, 0, 5;
%store/vec4 v0x5555994060b0_0, 0, 5; %store/vec4 v0x5555994060b0_0, 0, 5;
%pushi/vec4 0, 0, 5; %pushi/vec4 0, 0, 5;
%store/vec4 v0x555599406190_0, 0, 5; %store/vec4 v0x555599406190_0, 0, 5;
%end; %end;
.thread T_0; .thread T_0;
.scope S_0x5555993ec830; .scope S_0x5555993ec830;
T_1 ; T_1 ;
%wait E_0x5555993af500; %wait E_0x5555993af500;
%load/vec4 v0x555599405c40_0; %load/vec4 v0x555599405c40_0;
%cmpi/ne 16, 0, 5; %cmpi/ne 16, 0, 5;
%jmp/0xz T_1.0, 4; %jmp/0xz T_1.0, 4;
%load/vec4 v0x555599405d00_0; %load/vec4 v0x555599405d00_0;
%addi 1, 0, 5; %addi 1, 0, 5;
%assign/vec4 v0x555599405d00_0, 0; %assign/vec4 v0x555599405d00_0, 0;
%load/vec4 v0x555599405fd0_0; %load/vec4 v0x555599405fd0_0;
%pushi/vec4 0, 0, 4; %pushi/vec4 0, 0, 4;
%load/vec4 v0x555599405ef0_0; %load/vec4 v0x555599405ef0_0;
%parti/s 1, 0, 2; %parti/s 1, 0, 2;
%concat/vec4; draw_concat_vec4 %concat/vec4; draw_concat_vec4
%add; %add;
%assign/vec4 v0x555599405fd0_0, 0; %assign/vec4 v0x555599405fd0_0, 0;
%load/vec4 v0x5555994060b0_0; %load/vec4 v0x5555994060b0_0;
%pushi/vec4 0, 0, 4; %pushi/vec4 0, 0, 4;
%load/vec4 v0x555599405ef0_0; %load/vec4 v0x555599405ef0_0;
%parti/s 1, 1, 2; %parti/s 1, 1, 2;
%concat/vec4; draw_concat_vec4 %concat/vec4; draw_concat_vec4
%add; %add;
%assign/vec4 v0x5555994060b0_0, 0; %assign/vec4 v0x5555994060b0_0, 0;
%load/vec4 v0x555599406190_0; %load/vec4 v0x555599406190_0;
%pushi/vec4 0, 0, 4; %pushi/vec4 0, 0, 4;
%load/vec4 v0x555599405ef0_0; %load/vec4 v0x555599405ef0_0;
%parti/s 1, 2, 3; %parti/s 1, 2, 3;
%concat/vec4; draw_concat_vec4 %concat/vec4; draw_concat_vec4
%add; %add;
%assign/vec4 v0x555599406190_0, 0; %assign/vec4 v0x555599406190_0, 0;
T_1.0 ; T_1.0 ;
%jmp T_1; %jmp T_1;
.thread T_1; .thread T_1;
.scope S_0x5555993ec830; .scope S_0x5555993ec830;
T_2 ; T_2 ;
%wait E_0x5555993e7d70; %wait E_0x5555993e7d70;
%load/vec4 v0x5555994060b0_0; %load/vec4 v0x5555994060b0_0;
%load/vec4 v0x555599405fd0_0; %load/vec4 v0x555599405fd0_0;
%cmp/u; %cmp/u;
%jmp/0xz T_2.0, 5; %jmp/0xz T_2.0, 5;
%load/vec4 v0x555599406190_0; %load/vec4 v0x555599406190_0;
%load/vec4 v0x555599405fd0_0; %load/vec4 v0x555599405fd0_0;
%cmp/u; %cmp/u;
%jmp/0xz T_2.2, 5; %jmp/0xz T_2.2, 5;
%load/vec4 v0x555599405fd0_0; %load/vec4 v0x555599405fd0_0;
%assign/vec4 v0x555599406270_0, 0; %assign/vec4 v0x555599406270_0, 0;
%jmp T_2.3; %jmp T_2.3;
T_2.2 ; T_2.2 ;
%load/vec4 v0x555599406190_0; %load/vec4 v0x555599406190_0;
%assign/vec4 v0x555599406270_0, 0; %assign/vec4 v0x555599406270_0, 0;
T_2.3 ; T_2.3 ;
%jmp T_2.1; %jmp T_2.1;
T_2.0 ; T_2.0 ;
%load/vec4 v0x5555994060b0_0; %load/vec4 v0x5555994060b0_0;
%load/vec4 v0x555599405fd0_0; %load/vec4 v0x555599405fd0_0;
%cmp/u; %cmp/u;
%jmp/0xz T_2.4, 5; %jmp/0xz T_2.4, 5;
%load/vec4 v0x555599406190_0; %load/vec4 v0x555599406190_0;
%load/vec4 v0x5555994060b0_0; %load/vec4 v0x5555994060b0_0;
%cmp/u; %cmp/u;
%jmp/0xz T_2.6, 5; %jmp/0xz T_2.6, 5;
%load/vec4 v0x5555994060b0_0; %load/vec4 v0x5555994060b0_0;
%assign/vec4 v0x555599406270_0, 0; %assign/vec4 v0x555599406270_0, 0;
%jmp T_2.7; %jmp T_2.7;
T_2.6 ; T_2.6 ;
%load/vec4 v0x555599406190_0; %load/vec4 v0x555599406190_0;
%assign/vec4 v0x555599406270_0, 0; %assign/vec4 v0x555599406270_0, 0;
T_2.7 ; T_2.7 ;
T_2.4 ; T_2.4 ;
T_2.1 ; T_2.1 ;
%jmp T_2; %jmp T_2;
.thread T_2; .thread T_2;
.scope S_0x5555993ec6a0; .scope S_0x5555993ec6a0;
T_3 ; T_3 ;
%pushi/vec4 0, 0, 1; %pushi/vec4 0, 0, 1;
%store/vec4 v0x555599406550_0, 0, 1; %store/vec4 v0x555599406550_0, 0, 1;
%end; %end;
.thread T_3; .thread T_3;
.scope S_0x5555993ec6a0; .scope S_0x5555993ec6a0;
T_4 ; T_4 ;
%load/vec4 v0x555599406550_0; %load/vec4 v0x555599406550_0;
%inv; %inv;
%store/vec4 v0x555599406550_0, 0, 1; %store/vec4 v0x555599406550_0, 0, 1;
%delay 5, 0; %delay 5, 0;
%jmp T_4; %jmp T_4;
.thread T_4; .thread T_4;
.scope S_0x5555993ec6a0; .scope S_0x5555993ec6a0;
T_5 ; T_5 ;
%vpi_call 2 23 "$dumpvars" {0 0 0}; %vpi_call 2 23 "$dumpvars" {0 0 0};
%pushi/vec4 5, 0, 3; %pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 5, 0, 3; %pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 5, 0, 3; %pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 5, 0, 3; %pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 5, 0, 3; %pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 5, 0, 3; %pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 5, 0, 3; %pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 5, 0, 3; %pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 5, 0, 3; %pushi/vec4 5, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%pushi/vec4 0, 0, 3; %pushi/vec4 0, 0, 3;
%store/vec4 v0x555599406650_0, 0, 3; %store/vec4 v0x555599406650_0, 0, 3;
%delay 10, 0; %delay 10, 0;
%vpi_call 2 42 "$finish" {0 0 0}; %vpi_call 2 42 "$finish" {0 0 0};
%end; %end;
.thread T_5; .thread T_5;
# The file index is used to find the file name in the following table. # The file index is used to find the file name in the following table.
:file_names 4; :file_names 4;
"N/A"; "N/A";
"<interactive>"; "<interactive>";
"tb.v"; "tb.v";
"tetris.v"; "tetris.v";

0
tetirs/obj_dir/Vtb → iverilog/tobb/lab7tetris/obj_dir/Vtb
View File

184
tetirs/obj_dir/Vtb.cpp → iverilog/tobb/lab7tetris/obj_dir/Vtb.cpp
View File

@ -1,92 +1,92 @@
// Verilated -*- C++ -*- // Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Model implementation (design independent parts) // DESCRIPTION: Verilator output: Model implementation (design independent parts)
#include "Vtb.h" #include "Vtb.h"
#include "Vtb__Syms.h" #include "Vtb__Syms.h"
//============================================================ //============================================================
// Constructors // Constructors
Vtb::Vtb(VerilatedContext* _vcontextp__, const char* _vcname__) Vtb::Vtb(VerilatedContext* _vcontextp__, const char* _vcname__)
: VerilatedModel{*_vcontextp__} : VerilatedModel{*_vcontextp__}
, vlSymsp{new Vtb__Syms(contextp(), _vcname__, this)} , vlSymsp{new Vtb__Syms(contextp(), _vcname__, this)}
, rootp{&(vlSymsp->TOP)} , rootp{&(vlSymsp->TOP)}
{ {
// Register model with the context // Register model with the context
contextp()->addModel(this); contextp()->addModel(this);
} }
Vtb::Vtb(const char* _vcname__) Vtb::Vtb(const char* _vcname__)
: Vtb(Verilated::threadContextp(), _vcname__) : Vtb(Verilated::threadContextp(), _vcname__)
{ {
} }
//============================================================ //============================================================
// Destructor // Destructor
Vtb::~Vtb() { Vtb::~Vtb() {
delete vlSymsp; delete vlSymsp;
} }
//============================================================ //============================================================
// Evaluation function // Evaluation function
#ifdef VL_DEBUG #ifdef VL_DEBUG
void Vtb___024root___eval_debug_assertions(Vtb___024root* vlSelf); void Vtb___024root___eval_debug_assertions(Vtb___024root* vlSelf);
#endif // VL_DEBUG #endif // VL_DEBUG
void Vtb___024root___eval_static(Vtb___024root* vlSelf); void Vtb___024root___eval_static(Vtb___024root* vlSelf);
void Vtb___024root___eval_initial(Vtb___024root* vlSelf); void Vtb___024root___eval_initial(Vtb___024root* vlSelf);
void Vtb___024root___eval_settle(Vtb___024root* vlSelf); void Vtb___024root___eval_settle(Vtb___024root* vlSelf);
void Vtb___024root___eval(Vtb___024root* vlSelf); void Vtb___024root___eval(Vtb___024root* vlSelf);
void Vtb::eval_step() { void Vtb::eval_step() {
VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vtb::eval_step\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vtb::eval_step\n"); );
#ifdef VL_DEBUG #ifdef VL_DEBUG
// Debug assertions // Debug assertions
Vtb___024root___eval_debug_assertions(&(vlSymsp->TOP)); Vtb___024root___eval_debug_assertions(&(vlSymsp->TOP));
#endif // VL_DEBUG #endif // VL_DEBUG
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) { if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) {
vlSymsp->__Vm_didInit = true; vlSymsp->__Vm_didInit = true;
VL_DEBUG_IF(VL_DBG_MSGF("+ Initial\n");); VL_DEBUG_IF(VL_DBG_MSGF("+ Initial\n"););
Vtb___024root___eval_static(&(vlSymsp->TOP)); Vtb___024root___eval_static(&(vlSymsp->TOP));
Vtb___024root___eval_initial(&(vlSymsp->TOP)); Vtb___024root___eval_initial(&(vlSymsp->TOP));
Vtb___024root___eval_settle(&(vlSymsp->TOP)); Vtb___024root___eval_settle(&(vlSymsp->TOP));
} }
// MTask 0 start // MTask 0 start
VL_DEBUG_IF(VL_DBG_MSGF("MTask0 starting\n");); VL_DEBUG_IF(VL_DBG_MSGF("MTask0 starting\n"););
Verilated::mtaskId(0); Verilated::mtaskId(0);
VL_DEBUG_IF(VL_DBG_MSGF("+ Eval\n");); VL_DEBUG_IF(VL_DBG_MSGF("+ Eval\n"););
Vtb___024root___eval(&(vlSymsp->TOP)); Vtb___024root___eval(&(vlSymsp->TOP));
// Evaluate cleanup // Evaluate cleanup
Verilated::endOfThreadMTask(vlSymsp->__Vm_evalMsgQp); Verilated::endOfThreadMTask(vlSymsp->__Vm_evalMsgQp);
Verilated::endOfEval(vlSymsp->__Vm_evalMsgQp); Verilated::endOfEval(vlSymsp->__Vm_evalMsgQp);
} }
//============================================================ //============================================================
// Events and timing // Events and timing
bool Vtb::eventsPending() { return !vlSymsp->TOP.__VdlySched.empty(); } bool Vtb::eventsPending() { return !vlSymsp->TOP.__VdlySched.empty(); }
uint64_t Vtb::nextTimeSlot() { return vlSymsp->TOP.__VdlySched.nextTimeSlot(); } uint64_t Vtb::nextTimeSlot() { return vlSymsp->TOP.__VdlySched.nextTimeSlot(); }
//============================================================ //============================================================
// Utilities // Utilities
const char* Vtb::name() const { const char* Vtb::name() const {
return vlSymsp->name(); return vlSymsp->name();
} }
//============================================================ //============================================================
// Invoke final blocks // Invoke final blocks
void Vtb___024root___eval_final(Vtb___024root* vlSelf); void Vtb___024root___eval_final(Vtb___024root* vlSelf);
VL_ATTR_COLD void Vtb::final() { VL_ATTR_COLD void Vtb::final() {
Vtb___024root___eval_final(&(vlSymsp->TOP)); Vtb___024root___eval_final(&(vlSymsp->TOP));
} }
//============================================================ //============================================================
// Implementations of abstract methods from VerilatedModel // Implementations of abstract methods from VerilatedModel
const char* Vtb::hierName() const { return vlSymsp->name(); } const char* Vtb::hierName() const { return vlSymsp->name(); }
const char* Vtb::modelName() const { return "Vtb"; } const char* Vtb::modelName() const { return "Vtb"; }
unsigned Vtb::threads() const { return 1; } unsigned Vtb::threads() const { return 1; }

144
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@ -1,72 +1,72 @@
// Verilated -*- C++ -*- // Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary model header // DESCRIPTION: Verilator output: Primary model header
// //
// This header should be included by all source files instantiating the design. // This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design. // The class here is then constructed to instantiate the design.
// See the Verilator manual for examples. // See the Verilator manual for examples.
#ifndef VERILATED_VTB_H_ #ifndef VERILATED_VTB_H_
#define VERILATED_VTB_H_ // guard #define VERILATED_VTB_H_ // guard
#include "verilated.h" #include "verilated.h"
class Vtb__Syms; class Vtb__Syms;
class Vtb___024root; class Vtb___024root;
// This class is the main interface to the Verilated model // This class is the main interface to the Verilated model
class Vtb VL_NOT_FINAL : public VerilatedModel { class Vtb VL_NOT_FINAL : public VerilatedModel {
private: private:
// Symbol table holding complete model state (owned by this class) // Symbol table holding complete model state (owned by this class)
Vtb__Syms* const vlSymsp; Vtb__Syms* const vlSymsp;
public: public:
// PORTS // PORTS
// The application code writes and reads these signals to // The application code writes and reads these signals to
// propagate new values into/out from the Verilated model. // propagate new values into/out from the Verilated model.
// CELLS // CELLS
// Public to allow access to /* verilator public */ items. // Public to allow access to /* verilator public */ items.
// Otherwise the application code can consider these internals. // Otherwise the application code can consider these internals.
// Root instance pointer to allow access to model internals, // Root instance pointer to allow access to model internals,
// including inlined /* verilator public_flat_* */ items. // including inlined /* verilator public_flat_* */ items.
Vtb___024root* const rootp; Vtb___024root* const rootp;
// CONSTRUCTORS // CONSTRUCTORS
/// Construct the model; called by application code /// Construct the model; called by application code
/// If contextp is null, then the model will use the default global context /// If contextp is null, then the model will use the default global context
/// If name is "", then makes a wrapper with a /// If name is "", then makes a wrapper with a
/// single model invisible with respect to DPI scope names. /// single model invisible with respect to DPI scope names.
explicit Vtb(VerilatedContext* contextp, const char* name = "TOP"); explicit Vtb(VerilatedContext* contextp, const char* name = "TOP");
explicit Vtb(const char* name = "TOP"); explicit Vtb(const char* name = "TOP");
/// Destroy the model; called (often implicitly) by application code /// Destroy the model; called (often implicitly) by application code
virtual ~Vtb(); virtual ~Vtb();
private: private:
VL_UNCOPYABLE(Vtb); ///< Copying not allowed VL_UNCOPYABLE(Vtb); ///< Copying not allowed
public: public:
// API METHODS // API METHODS
/// Evaluate the model. Application must call when inputs change. /// Evaluate the model. Application must call when inputs change.
void eval() { eval_step(); } void eval() { eval_step(); }
/// Evaluate when calling multiple units/models per time step. /// Evaluate when calling multiple units/models per time step.
void eval_step(); void eval_step();
/// Evaluate at end of a timestep for tracing, when using eval_step(). /// Evaluate at end of a timestep for tracing, when using eval_step().
/// Application must call after all eval() and before time changes. /// Application must call after all eval() and before time changes.
void eval_end_step() {} void eval_end_step() {}
/// Simulation complete, run final blocks. Application must call on completion. /// Simulation complete, run final blocks. Application must call on completion.
void final(); void final();
/// Are there scheduled events to handle? /// Are there scheduled events to handle?
bool eventsPending(); bool eventsPending();
/// Returns time at next time slot. Aborts if !eventsPending() /// Returns time at next time slot. Aborts if !eventsPending()
uint64_t nextTimeSlot(); uint64_t nextTimeSlot();
/// Retrieve name of this model instance (as passed to constructor). /// Retrieve name of this model instance (as passed to constructor).
const char* name() const; const char* name() const;
// Abstract methods from VerilatedModel // Abstract methods from VerilatedModel
const char* hierName() const override final; const char* hierName() const override final;
const char* modelName() const override final; const char* modelName() const override final;
unsigned threads() const override final; unsigned threads() const override final;
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); } VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
#endif // guard #endif // guard

130
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@ -1,65 +1,65 @@
# Verilated -*- Makefile -*- # Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable # DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
# #
# Execute this makefile from the object directory: # Execute this makefile from the object directory:
# make -f Vtb.mk # make -f Vtb.mk
default: Vtb default: Vtb
### Constants... ### Constants...
# Perl executable (from $PERL) # Perl executable (from $PERL)
PERL = perl PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT) # Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/share/verilator VERILATOR_ROOT = /usr/share/verilator
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) # SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?= SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) # SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?= SYSTEMC_LIBDIR ?=
### Switches... ### Switches...
# C++ code coverage 0/1 (from --prof-c) # C++ code coverage 0/1 (from --prof-c)
VM_PROFC = 0 VM_PROFC = 0
# SystemC output mode? 0/1 (from --sc) # SystemC output mode? 0/1 (from --sc)
VM_SC = 0 VM_SC = 0
# Legacy or SystemC output mode? 0/1 (from --sc) # Legacy or SystemC output mode? 0/1 (from --sc)
VM_SP_OR_SC = $(VM_SC) VM_SP_OR_SC = $(VM_SC)
# Deprecated # Deprecated
VM_PCLI = 1 VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) # Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux VM_SC_TARGET_ARCH = linux
### Vars... ### Vars...
# Design prefix (from --prefix) # Design prefix (from --prefix)
VM_PREFIX = Vtb VM_PREFIX = Vtb
# Module prefix (from --prefix) # Module prefix (from --prefix)
VM_MODPREFIX = Vtb VM_MODPREFIX = Vtb
# User CFLAGS (from -CFLAGS on Verilator command line) # User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \ VM_USER_CFLAGS = \
-DVL_TIME_CONTEXT \ -DVL_TIME_CONTEXT \
# User LDLIBS (from -LDFLAGS on Verilator command line) # User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \ VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line) # User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \ VM_USER_CLASSES = \
# User .cpp directories (from .cpp's on Verilator command line) # User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \ VM_USER_DIR = \
### Default rules... ### Default rules...
# Include list of all generated classes # Include list of all generated classes
include Vtb_classes.mk include Vtb_classes.mk
# Include global rules # Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk include $(VERILATOR_ROOT)/include/verilated.mk
### Executable rules... (from --exe) ### Executable rules... (from --exe)
VPATH += $(VM_USER_DIR) VPATH += $(VM_USER_DIR)
### Link rules... (from --exe) ### Link rules... (from --exe)
Vtb: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a $(VM_HIER_LIBS) Vtb: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a $(VM_HIER_LIBS)
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) $(LIBS) $(SC_LIBS) -o $@ $(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) $(LIBS) $(SC_LIBS) -o $@
# Verilated -*- Makefile -*- # Verilated -*- Makefile -*-

0
tetirs/obj_dir/Vtb__ALL.a → iverilog/tobb/lab7tetris/obj_dir/Vtb__ALL.a
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20
tetirs/obj_dir/Vtb__ALL.cpp → iverilog/tobb/lab7tetris/obj_dir/Vtb__ALL.cpp
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@ -1,10 +1,10 @@
// DESCRIPTION: Generated by verilator_includer via makefile // DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include #define VL_INCLUDE_OPT include
#include "Vtb.cpp" #include "Vtb.cpp"
#include "Vtb___024root__DepSet_hfe20aad3__0.cpp" #include "Vtb___024root__DepSet_hfe20aad3__0.cpp"
#include "Vtb___024root__DepSet_ha183790c__0.cpp" #include "Vtb___024root__DepSet_ha183790c__0.cpp"
#include "Vtb__main.cpp" #include "Vtb__main.cpp"
#include "Vtb___024root__Slow.cpp" #include "Vtb___024root__Slow.cpp"
#include "Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp" #include "Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp"
#include "Vtb___024root__DepSet_ha183790c__0__Slow.cpp" #include "Vtb___024root__DepSet_ha183790c__0__Slow.cpp"
#include "Vtb__Syms.cpp" #include "Vtb__Syms.cpp"

24
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@ -1,12 +1,12 @@
Vtb__ALL.o: Vtb__ALL.cpp Vtb.cpp Vtb.h \ Vtb__ALL.o: Vtb__ALL.cpp Vtb.cpp Vtb.h \
/usr/share/verilator/include/verilated.h \ /usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilatedos.h \ /usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated_config.h \ /usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilated_types.h \ /usr/share/verilator/include/verilated_types.h \
/usr/share/verilator/include/verilated_funcs.h Vtb__Syms.h \ /usr/share/verilator/include/verilated_funcs.h Vtb__Syms.h \
Vtb___024root.h /usr/share/verilator/include/verilated_timing.h \ Vtb___024root.h /usr/share/verilator/include/verilated_timing.h \
/usr/share/verilator/include/verilated.h \ /usr/share/verilator/include/verilated.h \
Vtb___024root__DepSet_hfe20aad3__0.cpp \ Vtb___024root__DepSet_hfe20aad3__0.cpp \
Vtb___024root__DepSet_ha183790c__0.cpp Vtb__main.cpp \ Vtb___024root__DepSet_ha183790c__0.cpp Vtb__main.cpp \
Vtb___024root__Slow.cpp Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp \ Vtb___024root__Slow.cpp Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp \
Vtb___024root__DepSet_ha183790c__0__Slow.cpp Vtb__Syms.cpp Vtb___024root__DepSet_ha183790c__0__Slow.cpp Vtb__Syms.cpp

0
tetirs/obj_dir/Vtb__ALL.o → iverilog/tobb/lab7tetris/obj_dir/Vtb__ALL.o
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52
tetirs/obj_dir/Vtb__Syms.cpp → iverilog/tobb/lab7tetris/obj_dir/Vtb__Syms.cpp
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@ -1,26 +1,26 @@
// Verilated -*- C++ -*- // Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals // DESCRIPTION: Verilator output: Symbol table implementation internals
#include "Vtb__Syms.h" #include "Vtb__Syms.h"
#include "Vtb.h" #include "Vtb.h"
#include "Vtb___024root.h" #include "Vtb___024root.h"
// FUNCTIONS // FUNCTIONS
Vtb__Syms::~Vtb__Syms() Vtb__Syms::~Vtb__Syms()
{ {
} }
Vtb__Syms::Vtb__Syms(VerilatedContext* contextp, const char* namep, Vtb* modelp) Vtb__Syms::Vtb__Syms(VerilatedContext* contextp, const char* namep, Vtb* modelp)
: VerilatedSyms{contextp} : VerilatedSyms{contextp}
// Setup internal state of the Syms class // Setup internal state of the Syms class
, __Vm_modelp{modelp} , __Vm_modelp{modelp}
// Setup module instances // Setup module instances
, TOP{this, namep} , TOP{this, namep}
{ {
// Configure time unit / time precision // Configure time unit / time precision
_vm_contextp__->timeunit(-12); _vm_contextp__->timeunit(-12);
_vm_contextp__->timeprecision(-12); _vm_contextp__->timeprecision(-12);
// Setup each module's pointers to their submodules // Setup each module's pointers to their submodules
// Setup each module's pointer back to symbol table (for public functions) // Setup each module's pointer back to symbol table (for public functions)
TOP.__Vconfigure(true); TOP.__Vconfigure(true);
} }

74
tetirs/obj_dir/Vtb__Syms.h → iverilog/tobb/lab7tetris/obj_dir/Vtb__Syms.h
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@ -1,37 +1,37 @@
// Verilated -*- C++ -*- // Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header // DESCRIPTION: Verilator output: Symbol table internal header
// //
// Internal details; most calling programs do not need this header, // Internal details; most calling programs do not need this header,
// unless using verilator public meta comments. // unless using verilator public meta comments.
#ifndef VERILATED_VTB__SYMS_H_ #ifndef VERILATED_VTB__SYMS_H_
#define VERILATED_VTB__SYMS_H_ // guard #define VERILATED_VTB__SYMS_H_ // guard
#include "verilated.h" #include "verilated.h"
// INCLUDE MODEL CLASS // INCLUDE MODEL CLASS
#include "Vtb.h" #include "Vtb.h"
// INCLUDE MODULE CLASSES // INCLUDE MODULE CLASSES
#include "Vtb___024root.h" #include "Vtb___024root.h"
// SYMS CLASS (contains all model state) // SYMS CLASS (contains all model state)
class Vtb__Syms final : public VerilatedSyms { class Vtb__Syms final : public VerilatedSyms {
public: public:
// INTERNAL STATE // INTERNAL STATE
Vtb* const __Vm_modelp; Vtb* const __Vm_modelp;
bool __Vm_didInit = false; bool __Vm_didInit = false;
// MODULE INSTANCE STATE // MODULE INSTANCE STATE
Vtb___024root TOP; Vtb___024root TOP;
// CONSTRUCTORS // CONSTRUCTORS
Vtb__Syms(VerilatedContext* contextp, const char* namep, Vtb* modelp); Vtb__Syms(VerilatedContext* contextp, const char* namep, Vtb* modelp);
~Vtb__Syms(); ~Vtb__Syms();
// METHODS // METHODS
const char* name() { return TOP.name(); } const char* name() { return TOP.name(); }
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); } VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
#endif // guard #endif // guard

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@ -1,52 +1,52 @@
// Verilated -*- C++ -*- // Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header // DESCRIPTION: Verilator output: Design internal header
// See Vtb.h for the primary calling header // See Vtb.h for the primary calling header
#ifndef VERILATED_VTB___024ROOT_H_ #ifndef VERILATED_VTB___024ROOT_H_
#define VERILATED_VTB___024ROOT_H_ // guard #define VERILATED_VTB___024ROOT_H_ // guard
#include "verilated.h" #include "verilated.h"
#include "verilated_timing.h" #include "verilated_timing.h"
class Vtb__Syms; class Vtb__Syms;
class Vtb___024root final : public VerilatedModule { class Vtb___024root final : public VerilatedModule {
public: public:
// DESIGN SPECIFIC STATE // DESIGN SPECIFIC STATE
CData/*0:0*/ tb__DOT__clk; CData/*0:0*/ tb__DOT__clk;
CData/*0:0*/ tb__DOT__bitti_mi; CData/*0:0*/ tb__DOT__bitti_mi;
CData/*2:0*/ tb__DOT__parca; CData/*2:0*/ tb__DOT__parca;
CData/*4:0*/ tb__DOT__yukseklik; CData/*4:0*/ tb__DOT__yukseklik;
CData/*4:0*/ tb__DOT__cevrim; CData/*4:0*/ tb__DOT__cevrim;
CData/*4:0*/ tb__DOT__uut__DOT__cevrim_r; CData/*4:0*/ tb__DOT__uut__DOT__cevrim_r;
CData/*4:0*/ tb__DOT__uut__DOT__y_0; CData/*4:0*/ tb__DOT__uut__DOT__y_0;
CData/*4:0*/ tb__DOT__uut__DOT__y_1; CData/*4:0*/ tb__DOT__uut__DOT__y_1;
CData/*4:0*/ tb__DOT__uut__DOT__y_2; CData/*4:0*/ tb__DOT__uut__DOT__y_2;
CData/*4:0*/ __Vdly__tb__DOT__uut__DOT__y_0; CData/*4:0*/ __Vdly__tb__DOT__uut__DOT__y_0;
CData/*4:0*/ __Vdly__tb__DOT__uut__DOT__y_1; CData/*4:0*/ __Vdly__tb__DOT__uut__DOT__y_1;
CData/*4:0*/ __Vdly__tb__DOT__uut__DOT__y_2; CData/*4:0*/ __Vdly__tb__DOT__uut__DOT__y_2;
CData/*0:0*/ __Vtrigrprev__TOP__tb__DOT__clk; CData/*0:0*/ __Vtrigrprev__TOP__tb__DOT__clk;
CData/*0:0*/ __Vtrigrprev__TOP__tb__DOT__bitti_mi; CData/*0:0*/ __Vtrigrprev__TOP__tb__DOT__bitti_mi;
CData/*0:0*/ __VactContinue; CData/*0:0*/ __VactContinue;
IData/*31:0*/ __VstlIterCount; IData/*31:0*/ __VstlIterCount;
IData/*31:0*/ __VactIterCount; IData/*31:0*/ __VactIterCount;
VlDelayScheduler __VdlySched; VlDelayScheduler __VdlySched;
VlTriggerVec<1> __VstlTriggered; VlTriggerVec<1> __VstlTriggered;
VlTriggerVec<3> __VactTriggered; VlTriggerVec<3> __VactTriggered;
VlTriggerVec<3> __VnbaTriggered; VlTriggerVec<3> __VnbaTriggered;
// INTERNAL VARIABLES // INTERNAL VARIABLES
Vtb__Syms* const vlSymsp; Vtb__Syms* const vlSymsp;
// CONSTRUCTORS // CONSTRUCTORS
Vtb___024root(Vtb__Syms* symsp, const char* v__name); Vtb___024root(Vtb__Syms* symsp, const char* v__name);
~Vtb___024root(); ~Vtb___024root();
VL_UNCOPYABLE(Vtb___024root); VL_UNCOPYABLE(Vtb___024root);
// INTERNAL METHODS // INTERNAL METHODS
void __Vconfigure(bool first); void __Vconfigure(bool first);
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); } VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
#endif // guard #endif // guard

402
tetirs/obj_dir/Vtb___024root__DepSet_ha183790c__0.cpp → iverilog/tobb/lab7tetris/obj_dir/Vtb___024root__DepSet_ha183790c__0.cpp
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@ -1,201 +1,201 @@
// Verilated -*- C++ -*- // Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals // DESCRIPTION: Verilator output: Design implementation internals
// See Vtb.h for the primary calling header // See Vtb.h for the primary calling header
#include "verilated.h" #include "verilated.h"
#include "Vtb___024root.h" #include "Vtb___024root.h"
VlCoroutine Vtb___024root___eval_initial__TOP__0(Vtb___024root* vlSelf); VlCoroutine Vtb___024root___eval_initial__TOP__0(Vtb___024root* vlSelf);
void Vtb___024root___eval_initial(Vtb___024root* vlSelf) { void Vtb___024root___eval_initial(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_initial\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_initial\n"); );
// Body // Body
Vtb___024root___eval_initial__TOP__0(vlSelf); Vtb___024root___eval_initial__TOP__0(vlSelf);
vlSelf->__Vtrigrprev__TOP__tb__DOT__clk = vlSelf->tb__DOT__clk; vlSelf->__Vtrigrprev__TOP__tb__DOT__clk = vlSelf->tb__DOT__clk;
vlSelf->__Vtrigrprev__TOP__tb__DOT__bitti_mi = vlSelf->tb__DOT__bitti_mi; vlSelf->__Vtrigrprev__TOP__tb__DOT__bitti_mi = vlSelf->tb__DOT__bitti_mi;
} }
VL_INLINE_OPT VlCoroutine Vtb___024root___eval_initial__TOP__0(Vtb___024root* vlSelf) { VL_INLINE_OPT VlCoroutine Vtb___024root___eval_initial__TOP__0(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_initial__TOP__0\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_initial__TOP__0\n"); );
// Body // Body
while (1U) { while (1U) {
co_await vlSelf->__VdlySched.delay(5U, "tb.v", co_await vlSelf->__VdlySched.delay(5U, "tb.v",
20); 20);
vlSelf->tb__DOT__clk = (1U & (~ (IData)(vlSelf->tb__DOT__clk))); vlSelf->tb__DOT__clk = (1U & (~ (IData)(vlSelf->tb__DOT__clk)));
} }
vlSelf->tb__DOT__parca = 5U; vlSelf->tb__DOT__parca = 5U;
co_await vlSelf->__VdlySched.delay(0xc8U, "tb.v", co_await vlSelf->__VdlySched.delay(0xc8U, "tb.v",
21); 21);
VL_WRITEF("%2#\n%2#\n%1#\n",5,vlSelf->tb__DOT__yukseklik, VL_WRITEF("%2#\n%2#\n%1#\n",5,vlSelf->tb__DOT__yukseklik,
5,(IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r), 5,(IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r),
1,vlSelf->tb__DOT__bitti_mi); 1,vlSelf->tb__DOT__bitti_mi);
VL_FINISH_MT("tb.v", 25, ""); VL_FINISH_MT("tb.v", 25, "");
} }
void Vtb___024root___eval_act(Vtb___024root* vlSelf) { void Vtb___024root___eval_act(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_act\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_act\n"); );
} }
VL_INLINE_OPT void Vtb___024root___nba_sequent__TOP__0(Vtb___024root* vlSelf) { VL_INLINE_OPT void Vtb___024root___nba_sequent__TOP__0(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___nba_sequent__TOP__0\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___nba_sequent__TOP__0\n"); );
// Body // Body
vlSelf->__Vdly__tb__DOT__uut__DOT__y_2 = vlSelf->tb__DOT__uut__DOT__y_2; vlSelf->__Vdly__tb__DOT__uut__DOT__y_2 = vlSelf->tb__DOT__uut__DOT__y_2;
vlSelf->__Vdly__tb__DOT__uut__DOT__y_1 = vlSelf->tb__DOT__uut__DOT__y_1; vlSelf->__Vdly__tb__DOT__uut__DOT__y_1 = vlSelf->tb__DOT__uut__DOT__y_1;
vlSelf->__Vdly__tb__DOT__uut__DOT__y_0 = vlSelf->tb__DOT__uut__DOT__y_0; vlSelf->__Vdly__tb__DOT__uut__DOT__y_0 = vlSelf->tb__DOT__uut__DOT__y_0;
if ((0x10U != (IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r))) { if ((0x10U != (IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r))) {
vlSelf->__Vdly__tb__DOT__uut__DOT__y_2 = (0x1fU vlSelf->__Vdly__tb__DOT__uut__DOT__y_2 = (0x1fU
& ((IData)(vlSelf->tb__DOT__uut__DOT__y_2) & ((IData)(vlSelf->tb__DOT__uut__DOT__y_2)
+ +
(1U (1U
& ((IData)(vlSelf->tb__DOT__parca) & ((IData)(vlSelf->tb__DOT__parca)
>> 2U)))); >> 2U))));
vlSelf->__Vdly__tb__DOT__uut__DOT__y_1 = (0x1fU vlSelf->__Vdly__tb__DOT__uut__DOT__y_1 = (0x1fU
& ((IData)(vlSelf->tb__DOT__uut__DOT__y_1) & ((IData)(vlSelf->tb__DOT__uut__DOT__y_1)
+ +
(1U (1U
& ((IData)(vlSelf->tb__DOT__parca) & ((IData)(vlSelf->tb__DOT__parca)
>> 1U)))); >> 1U))));
vlSelf->__Vdly__tb__DOT__uut__DOT__y_0 = (0x1fU vlSelf->__Vdly__tb__DOT__uut__DOT__y_0 = (0x1fU
& ((IData)(vlSelf->tb__DOT__uut__DOT__y_0) & ((IData)(vlSelf->tb__DOT__uut__DOT__y_0)
+ +
(1U (1U
& (IData)(vlSelf->tb__DOT__parca)))); & (IData)(vlSelf->tb__DOT__parca))));
} }
if ((0x10U != (IData)(vlSelf->tb__DOT__cevrim))) { if ((0x10U != (IData)(vlSelf->tb__DOT__cevrim))) {
vlSelf->tb__DOT__uut__DOT__cevrim_r = (0x1fU vlSelf->tb__DOT__uut__DOT__cevrim_r = (0x1fU
& ((IData)(1U) & ((IData)(1U)
+ (IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r))); + (IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r)));
} }
vlSelf->tb__DOT__cevrim = vlSelf->tb__DOT__uut__DOT__cevrim_r; vlSelf->tb__DOT__cevrim = vlSelf->tb__DOT__uut__DOT__cevrim_r;
vlSelf->tb__DOT__bitti_mi = (0x10U == (IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r)); vlSelf->tb__DOT__bitti_mi = (0x10U == (IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r));
} }
VL_INLINE_OPT void Vtb___024root___nba_sequent__TOP__1(Vtb___024root* vlSelf) { VL_INLINE_OPT void Vtb___024root___nba_sequent__TOP__1(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___nba_sequent__TOP__1\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___nba_sequent__TOP__1\n"); );
// Body // Body
if (((IData)(vlSelf->tb__DOT__uut__DOT__y_0) > (IData)(vlSelf->tb__DOT__uut__DOT__y_1))) { if (((IData)(vlSelf->tb__DOT__uut__DOT__y_0) > (IData)(vlSelf->tb__DOT__uut__DOT__y_1))) {
vlSelf->tb__DOT__yukseklik = (((IData)(vlSelf->tb__DOT__uut__DOT__y_0) vlSelf->tb__DOT__yukseklik = (((IData)(vlSelf->tb__DOT__uut__DOT__y_0)
> (IData)(vlSelf->tb__DOT__uut__DOT__y_2)) > (IData)(vlSelf->tb__DOT__uut__DOT__y_2))
? (IData)(vlSelf->tb__DOT__uut__DOT__y_0) ? (IData)(vlSelf->tb__DOT__uut__DOT__y_0)
: (IData)(vlSelf->tb__DOT__uut__DOT__y_2)); : (IData)(vlSelf->tb__DOT__uut__DOT__y_2));
} else if (((IData)(vlSelf->tb__DOT__uut__DOT__y_0) } else if (((IData)(vlSelf->tb__DOT__uut__DOT__y_0)
> (IData)(vlSelf->tb__DOT__uut__DOT__y_1))) { > (IData)(vlSelf->tb__DOT__uut__DOT__y_1))) {
vlSelf->tb__DOT__yukseklik = (((IData)(vlSelf->tb__DOT__uut__DOT__y_1) vlSelf->tb__DOT__yukseklik = (((IData)(vlSelf->tb__DOT__uut__DOT__y_1)
> (IData)(vlSelf->tb__DOT__uut__DOT__y_2)) > (IData)(vlSelf->tb__DOT__uut__DOT__y_2))
? (IData)(vlSelf->tb__DOT__uut__DOT__y_1) ? (IData)(vlSelf->tb__DOT__uut__DOT__y_1)
: (IData)(vlSelf->tb__DOT__uut__DOT__y_2)); : (IData)(vlSelf->tb__DOT__uut__DOT__y_2));
} }
} }
VL_INLINE_OPT void Vtb___024root___nba_sequent__TOP__2(Vtb___024root* vlSelf) { VL_INLINE_OPT void Vtb___024root___nba_sequent__TOP__2(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___nba_sequent__TOP__2\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___nba_sequent__TOP__2\n"); );
// Body // Body
vlSelf->tb__DOT__uut__DOT__y_0 = vlSelf->__Vdly__tb__DOT__uut__DOT__y_0; vlSelf->tb__DOT__uut__DOT__y_0 = vlSelf->__Vdly__tb__DOT__uut__DOT__y_0;
vlSelf->tb__DOT__uut__DOT__y_1 = vlSelf->__Vdly__tb__DOT__uut__DOT__y_1; vlSelf->tb__DOT__uut__DOT__y_1 = vlSelf->__Vdly__tb__DOT__uut__DOT__y_1;
vlSelf->tb__DOT__uut__DOT__y_2 = vlSelf->__Vdly__tb__DOT__uut__DOT__y_2; vlSelf->tb__DOT__uut__DOT__y_2 = vlSelf->__Vdly__tb__DOT__uut__DOT__y_2;
} }
void Vtb___024root___eval_nba(Vtb___024root* vlSelf) { void Vtb___024root___eval_nba(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_nba\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_nba\n"); );
// Body // Body
if (vlSelf->__VnbaTriggered.at(0U)) { if (vlSelf->__VnbaTriggered.at(0U)) {
Vtb___024root___nba_sequent__TOP__0(vlSelf); Vtb___024root___nba_sequent__TOP__0(vlSelf);
} }
if (vlSelf->__VnbaTriggered.at(1U)) { if (vlSelf->__VnbaTriggered.at(1U)) {
Vtb___024root___nba_sequent__TOP__1(vlSelf); Vtb___024root___nba_sequent__TOP__1(vlSelf);
} }
if (vlSelf->__VnbaTriggered.at(0U)) { if (vlSelf->__VnbaTriggered.at(0U)) {
Vtb___024root___nba_sequent__TOP__2(vlSelf); Vtb___024root___nba_sequent__TOP__2(vlSelf);
} }
} }
void Vtb___024root___eval_triggers__act(Vtb___024root* vlSelf); void Vtb___024root___eval_triggers__act(Vtb___024root* vlSelf);
#ifdef VL_DEBUG #ifdef VL_DEBUG
VL_ATTR_COLD void Vtb___024root___dump_triggers__act(Vtb___024root* vlSelf); VL_ATTR_COLD void Vtb___024root___dump_triggers__act(Vtb___024root* vlSelf);
#endif // VL_DEBUG #endif // VL_DEBUG
void Vtb___024root___timing_resume(Vtb___024root* vlSelf); void Vtb___024root___timing_resume(Vtb___024root* vlSelf);
#ifdef VL_DEBUG #ifdef VL_DEBUG
VL_ATTR_COLD void Vtb___024root___dump_triggers__nba(Vtb___024root* vlSelf); VL_ATTR_COLD void Vtb___024root___dump_triggers__nba(Vtb___024root* vlSelf);
#endif // VL_DEBUG #endif // VL_DEBUG
void Vtb___024root___eval(Vtb___024root* vlSelf) { void Vtb___024root___eval(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval\n"); );
// Init // Init
VlTriggerVec<3> __VpreTriggered; VlTriggerVec<3> __VpreTriggered;
IData/*31:0*/ __VnbaIterCount; IData/*31:0*/ __VnbaIterCount;
CData/*0:0*/ __VnbaContinue; CData/*0:0*/ __VnbaContinue;
// Body // Body
__VnbaIterCount = 0U; __VnbaIterCount = 0U;
__VnbaContinue = 1U; __VnbaContinue = 1U;
while (__VnbaContinue) { while (__VnbaContinue) {
__VnbaContinue = 0U; __VnbaContinue = 0U;
vlSelf->__VnbaTriggered.clear(); vlSelf->__VnbaTriggered.clear();
vlSelf->__VactIterCount = 0U; vlSelf->__VactIterCount = 0U;
vlSelf->__VactContinue = 1U; vlSelf->__VactContinue = 1U;
while (vlSelf->__VactContinue) { while (vlSelf->__VactContinue) {
vlSelf->__VactContinue = 0U; vlSelf->__VactContinue = 0U;
Vtb___024root___eval_triggers__act(vlSelf); Vtb___024root___eval_triggers__act(vlSelf);
if (vlSelf->__VactTriggered.any()) { if (vlSelf->__VactTriggered.any()) {
vlSelf->__VactContinue = 1U; vlSelf->__VactContinue = 1U;
if (VL_UNLIKELY((0x64U < vlSelf->__VactIterCount))) { if (VL_UNLIKELY((0x64U < vlSelf->__VactIterCount))) {
#ifdef VL_DEBUG #ifdef VL_DEBUG
Vtb___024root___dump_triggers__act(vlSelf); Vtb___024root___dump_triggers__act(vlSelf);
#endif #endif
VL_FATAL_MT("tb.v", 1, "", "Active region did not converge."); VL_FATAL_MT("tb.v", 1, "", "Active region did not converge.");
} }
vlSelf->__VactIterCount = ((IData)(1U) vlSelf->__VactIterCount = ((IData)(1U)
+ vlSelf->__VactIterCount); + vlSelf->__VactIterCount);
__VpreTriggered.andNot(vlSelf->__VactTriggered, vlSelf->__VnbaTriggered); __VpreTriggered.andNot(vlSelf->__VactTriggered, vlSelf->__VnbaTriggered);
vlSelf->__VnbaTriggered.set(vlSelf->__VactTriggered); vlSelf->__VnbaTriggered.set(vlSelf->__VactTriggered);
Vtb___024root___timing_resume(vlSelf); Vtb___024root___timing_resume(vlSelf);
Vtb___024root___eval_act(vlSelf); Vtb___024root___eval_act(vlSelf);
} }
} }
if (vlSelf->__VnbaTriggered.any()) { if (vlSelf->__VnbaTriggered.any()) {
__VnbaContinue = 1U; __VnbaContinue = 1U;
if (VL_UNLIKELY((0x64U < __VnbaIterCount))) { if (VL_UNLIKELY((0x64U < __VnbaIterCount))) {
#ifdef VL_DEBUG #ifdef VL_DEBUG
Vtb___024root___dump_triggers__nba(vlSelf); Vtb___024root___dump_triggers__nba(vlSelf);
#endif #endif
VL_FATAL_MT("tb.v", 1, "", "NBA region did not converge."); VL_FATAL_MT("tb.v", 1, "", "NBA region did not converge.");
} }
__VnbaIterCount = ((IData)(1U) + __VnbaIterCount); __VnbaIterCount = ((IData)(1U) + __VnbaIterCount);
Vtb___024root___eval_nba(vlSelf); Vtb___024root___eval_nba(vlSelf);
} }
} }
} }
void Vtb___024root___timing_resume(Vtb___024root* vlSelf) { void Vtb___024root___timing_resume(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___timing_resume\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___timing_resume\n"); );
// Body // Body
if (vlSelf->__VactTriggered.at(2U)) { if (vlSelf->__VactTriggered.at(2U)) {
vlSelf->__VdlySched.resume(); vlSelf->__VdlySched.resume();
} }
} }
#ifdef VL_DEBUG #ifdef VL_DEBUG
void Vtb___024root___eval_debug_assertions(Vtb___024root* vlSelf) { void Vtb___024root___eval_debug_assertions(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_debug_assertions\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_debug_assertions\n"); );
} }
#endif // VL_DEBUG #endif // VL_DEBUG

330
tetirs/obj_dir/Vtb___024root__DepSet_ha183790c__0__Slow.cpp → iverilog/tobb/lab7tetris/obj_dir/Vtb___024root__DepSet_ha183790c__0__Slow.cpp
View File

@ -1,165 +1,165 @@
// Verilated -*- C++ -*- // Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals // DESCRIPTION: Verilator output: Design implementation internals
// See Vtb.h for the primary calling header // See Vtb.h for the primary calling header
#include "verilated.h" #include "verilated.h"
#include "Vtb___024root.h" #include "Vtb___024root.h"
VL_ATTR_COLD void Vtb___024root___eval_static__TOP(Vtb___024root* vlSelf); VL_ATTR_COLD void Vtb___024root___eval_static__TOP(Vtb___024root* vlSelf);
VL_ATTR_COLD void Vtb___024root___eval_static(Vtb___024root* vlSelf) { VL_ATTR_COLD void Vtb___024root___eval_static(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_static\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_static\n"); );
// Body // Body
Vtb___024root___eval_static__TOP(vlSelf); Vtb___024root___eval_static__TOP(vlSelf);
} }
VL_ATTR_COLD void Vtb___024root___eval_static__TOP(Vtb___024root* vlSelf) { VL_ATTR_COLD void Vtb___024root___eval_static__TOP(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_static__TOP\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_static__TOP\n"); );
// Body // Body
vlSelf->tb__DOT__clk = 0U; vlSelf->tb__DOT__clk = 0U;
vlSelf->tb__DOT__uut__DOT__cevrim_r = 0U; vlSelf->tb__DOT__uut__DOT__cevrim_r = 0U;
vlSelf->tb__DOT__uut__DOT__y_0 = 0U; vlSelf->tb__DOT__uut__DOT__y_0 = 0U;
vlSelf->tb__DOT__uut__DOT__y_1 = 0U; vlSelf->tb__DOT__uut__DOT__y_1 = 0U;
vlSelf->tb__DOT__uut__DOT__y_2 = 0U; vlSelf->tb__DOT__uut__DOT__y_2 = 0U;
} }
VL_ATTR_COLD void Vtb___024root___eval_final(Vtb___024root* vlSelf) { VL_ATTR_COLD void Vtb___024root___eval_final(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_final\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_final\n"); );
} }
VL_ATTR_COLD void Vtb___024root___eval_triggers__stl(Vtb___024root* vlSelf); VL_ATTR_COLD void Vtb___024root___eval_triggers__stl(Vtb___024root* vlSelf);
#ifdef VL_DEBUG #ifdef VL_DEBUG
VL_ATTR_COLD void Vtb___024root___dump_triggers__stl(Vtb___024root* vlSelf); VL_ATTR_COLD void Vtb___024root___dump_triggers__stl(Vtb___024root* vlSelf);
#endif // VL_DEBUG #endif // VL_DEBUG
VL_ATTR_COLD void Vtb___024root___eval_stl(Vtb___024root* vlSelf); VL_ATTR_COLD void Vtb___024root___eval_stl(Vtb___024root* vlSelf);
VL_ATTR_COLD void Vtb___024root___eval_settle(Vtb___024root* vlSelf) { VL_ATTR_COLD void Vtb___024root___eval_settle(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_settle\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_settle\n"); );
// Init // Init
CData/*0:0*/ __VstlContinue; CData/*0:0*/ __VstlContinue;
// Body // Body
vlSelf->__VstlIterCount = 0U; vlSelf->__VstlIterCount = 0U;
__VstlContinue = 1U; __VstlContinue = 1U;
while (__VstlContinue) { while (__VstlContinue) {
__VstlContinue = 0U; __VstlContinue = 0U;
Vtb___024root___eval_triggers__stl(vlSelf); Vtb___024root___eval_triggers__stl(vlSelf);
if (vlSelf->__VstlTriggered.any()) { if (vlSelf->__VstlTriggered.any()) {
__VstlContinue = 1U; __VstlContinue = 1U;
if (VL_UNLIKELY((0x64U < vlSelf->__VstlIterCount))) { if (VL_UNLIKELY((0x64U < vlSelf->__VstlIterCount))) {
#ifdef VL_DEBUG #ifdef VL_DEBUG
Vtb___024root___dump_triggers__stl(vlSelf); Vtb___024root___dump_triggers__stl(vlSelf);
#endif #endif
VL_FATAL_MT("tb.v", 1, "", "Settle region did not converge."); VL_FATAL_MT("tb.v", 1, "", "Settle region did not converge.");
} }
vlSelf->__VstlIterCount = ((IData)(1U) vlSelf->__VstlIterCount = ((IData)(1U)
+ vlSelf->__VstlIterCount); + vlSelf->__VstlIterCount);
Vtb___024root___eval_stl(vlSelf); Vtb___024root___eval_stl(vlSelf);
} }
} }
} }
#ifdef VL_DEBUG #ifdef VL_DEBUG
VL_ATTR_COLD void Vtb___024root___dump_triggers__stl(Vtb___024root* vlSelf) { VL_ATTR_COLD void Vtb___024root___dump_triggers__stl(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___dump_triggers__stl\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___dump_triggers__stl\n"); );
// Body // Body
if ((1U & (~ (IData)(vlSelf->__VstlTriggered.any())))) { if ((1U & (~ (IData)(vlSelf->__VstlTriggered.any())))) {
VL_DBG_MSGF(" No triggers active\n"); VL_DBG_MSGF(" No triggers active\n");
} }
if (vlSelf->__VstlTriggered.at(0U)) { if (vlSelf->__VstlTriggered.at(0U)) {
VL_DBG_MSGF(" 'stl' region trigger index 0 is active: Internal 'stl' trigger - first iteration\n"); VL_DBG_MSGF(" 'stl' region trigger index 0 is active: Internal 'stl' trigger - first iteration\n");
} }
} }
#endif // VL_DEBUG #endif // VL_DEBUG
VL_ATTR_COLD void Vtb___024root___stl_sequent__TOP__0(Vtb___024root* vlSelf) { VL_ATTR_COLD void Vtb___024root___stl_sequent__TOP__0(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___stl_sequent__TOP__0\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___stl_sequent__TOP__0\n"); );
// Body // Body
vlSelf->tb__DOT__cevrim = vlSelf->tb__DOT__uut__DOT__cevrim_r; vlSelf->tb__DOT__cevrim = vlSelf->tb__DOT__uut__DOT__cevrim_r;
vlSelf->tb__DOT__bitti_mi = (0x10U == (IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r)); vlSelf->tb__DOT__bitti_mi = (0x10U == (IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r));
} }
VL_ATTR_COLD void Vtb___024root___eval_stl(Vtb___024root* vlSelf) { VL_ATTR_COLD void Vtb___024root___eval_stl(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_stl\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_stl\n"); );
// Body // Body
if (vlSelf->__VstlTriggered.at(0U)) { if (vlSelf->__VstlTriggered.at(0U)) {
Vtb___024root___stl_sequent__TOP__0(vlSelf); Vtb___024root___stl_sequent__TOP__0(vlSelf);
} }
} }
#ifdef VL_DEBUG #ifdef VL_DEBUG
VL_ATTR_COLD void Vtb___024root___dump_triggers__act(Vtb___024root* vlSelf) { VL_ATTR_COLD void Vtb___024root___dump_triggers__act(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___dump_triggers__act\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___dump_triggers__act\n"); );
// Body // Body
if ((1U & (~ (IData)(vlSelf->__VactTriggered.any())))) { if ((1U & (~ (IData)(vlSelf->__VactTriggered.any())))) {
VL_DBG_MSGF(" No triggers active\n"); VL_DBG_MSGF(" No triggers active\n");
} }
if (vlSelf->__VactTriggered.at(0U)) { if (vlSelf->__VactTriggered.at(0U)) {
VL_DBG_MSGF(" 'act' region trigger index 0 is active: @(posedge tb.clk)\n"); VL_DBG_MSGF(" 'act' region trigger index 0 is active: @(posedge tb.clk)\n");
} }
if (vlSelf->__VactTriggered.at(1U)) { if (vlSelf->__VactTriggered.at(1U)) {
VL_DBG_MSGF(" 'act' region trigger index 1 is active: @(posedge tb.bitti_mi)\n"); VL_DBG_MSGF(" 'act' region trigger index 1 is active: @(posedge tb.bitti_mi)\n");
} }
if (vlSelf->__VactTriggered.at(2U)) { if (vlSelf->__VactTriggered.at(2U)) {
VL_DBG_MSGF(" 'act' region trigger index 2 is active: @([true] __VdlySched.awaitingCurrentTime())\n"); VL_DBG_MSGF(" 'act' region trigger index 2 is active: @([true] __VdlySched.awaitingCurrentTime())\n");
} }
} }
#endif // VL_DEBUG #endif // VL_DEBUG
#ifdef VL_DEBUG #ifdef VL_DEBUG
VL_ATTR_COLD void Vtb___024root___dump_triggers__nba(Vtb___024root* vlSelf) { VL_ATTR_COLD void Vtb___024root___dump_triggers__nba(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___dump_triggers__nba\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___dump_triggers__nba\n"); );
// Body // Body
if ((1U & (~ (IData)(vlSelf->__VnbaTriggered.any())))) { if ((1U & (~ (IData)(vlSelf->__VnbaTriggered.any())))) {
VL_DBG_MSGF(" No triggers active\n"); VL_DBG_MSGF(" No triggers active\n");
} }
if (vlSelf->__VnbaTriggered.at(0U)) { if (vlSelf->__VnbaTriggered.at(0U)) {
VL_DBG_MSGF(" 'nba' region trigger index 0 is active: @(posedge tb.clk)\n"); VL_DBG_MSGF(" 'nba' region trigger index 0 is active: @(posedge tb.clk)\n");
} }
if (vlSelf->__VnbaTriggered.at(1U)) { if (vlSelf->__VnbaTriggered.at(1U)) {
VL_DBG_MSGF(" 'nba' region trigger index 1 is active: @(posedge tb.bitti_mi)\n"); VL_DBG_MSGF(" 'nba' region trigger index 1 is active: @(posedge tb.bitti_mi)\n");
} }
if (vlSelf->__VnbaTriggered.at(2U)) { if (vlSelf->__VnbaTriggered.at(2U)) {
VL_DBG_MSGF(" 'nba' region trigger index 2 is active: @([true] __VdlySched.awaitingCurrentTime())\n"); VL_DBG_MSGF(" 'nba' region trigger index 2 is active: @([true] __VdlySched.awaitingCurrentTime())\n");
} }
} }
#endif // VL_DEBUG #endif // VL_DEBUG
VL_ATTR_COLD void Vtb___024root___ctor_var_reset(Vtb___024root* vlSelf) { VL_ATTR_COLD void Vtb___024root___ctor_var_reset(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___ctor_var_reset\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___ctor_var_reset\n"); );
// Body // Body
vlSelf->tb__DOT__parca = VL_RAND_RESET_I(3); vlSelf->tb__DOT__parca = VL_RAND_RESET_I(3);
vlSelf->tb__DOT__clk = VL_RAND_RESET_I(1); vlSelf->tb__DOT__clk = VL_RAND_RESET_I(1);
vlSelf->tb__DOT__yukseklik = VL_RAND_RESET_I(5); vlSelf->tb__DOT__yukseklik = VL_RAND_RESET_I(5);
vlSelf->tb__DOT__cevrim = VL_RAND_RESET_I(5); vlSelf->tb__DOT__cevrim = VL_RAND_RESET_I(5);
vlSelf->tb__DOT__bitti_mi = VL_RAND_RESET_I(1); vlSelf->tb__DOT__bitti_mi = VL_RAND_RESET_I(1);
vlSelf->tb__DOT__uut__DOT__cevrim_r = VL_RAND_RESET_I(5); vlSelf->tb__DOT__uut__DOT__cevrim_r = VL_RAND_RESET_I(5);
vlSelf->tb__DOT__uut__DOT__y_0 = VL_RAND_RESET_I(5); vlSelf->tb__DOT__uut__DOT__y_0 = VL_RAND_RESET_I(5);
vlSelf->tb__DOT__uut__DOT__y_1 = VL_RAND_RESET_I(5); vlSelf->tb__DOT__uut__DOT__y_1 = VL_RAND_RESET_I(5);
vlSelf->tb__DOT__uut__DOT__y_2 = VL_RAND_RESET_I(5); vlSelf->tb__DOT__uut__DOT__y_2 = VL_RAND_RESET_I(5);
vlSelf->__Vdly__tb__DOT__uut__DOT__y_0 = VL_RAND_RESET_I(5); vlSelf->__Vdly__tb__DOT__uut__DOT__y_0 = VL_RAND_RESET_I(5);
vlSelf->__Vdly__tb__DOT__uut__DOT__y_1 = VL_RAND_RESET_I(5); vlSelf->__Vdly__tb__DOT__uut__DOT__y_1 = VL_RAND_RESET_I(5);
vlSelf->__Vdly__tb__DOT__uut__DOT__y_2 = VL_RAND_RESET_I(5); vlSelf->__Vdly__tb__DOT__uut__DOT__y_2 = VL_RAND_RESET_I(5);
vlSelf->__Vtrigrprev__TOP__tb__DOT__clk = VL_RAND_RESET_I(1); vlSelf->__Vtrigrprev__TOP__tb__DOT__clk = VL_RAND_RESET_I(1);
vlSelf->__Vtrigrprev__TOP__tb__DOT__bitti_mi = VL_RAND_RESET_I(1); vlSelf->__Vtrigrprev__TOP__tb__DOT__bitti_mi = VL_RAND_RESET_I(1);
} }

62
tetirs/obj_dir/Vtb___024root__DepSet_hfe20aad3__0.cpp → iverilog/tobb/lab7tetris/obj_dir/Vtb___024root__DepSet_hfe20aad3__0.cpp
View File

@ -1,31 +1,31 @@
// Verilated -*- C++ -*- // Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals // DESCRIPTION: Verilator output: Design implementation internals
// See Vtb.h for the primary calling header // See Vtb.h for the primary calling header
#include "verilated.h" #include "verilated.h"
#include "Vtb__Syms.h" #include "Vtb__Syms.h"
#include "Vtb___024root.h" #include "Vtb___024root.h"
#ifdef VL_DEBUG #ifdef VL_DEBUG
VL_ATTR_COLD void Vtb___024root___dump_triggers__act(Vtb___024root* vlSelf); VL_ATTR_COLD void Vtb___024root___dump_triggers__act(Vtb___024root* vlSelf);
#endif // VL_DEBUG #endif // VL_DEBUG
void Vtb___024root___eval_triggers__act(Vtb___024root* vlSelf) { void Vtb___024root___eval_triggers__act(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_triggers__act\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_triggers__act\n"); );
// Body // Body
vlSelf->__VactTriggered.at(0U) = ((IData)(vlSelf->tb__DOT__clk) vlSelf->__VactTriggered.at(0U) = ((IData)(vlSelf->tb__DOT__clk)
& (~ (IData)(vlSelf->__Vtrigrprev__TOP__tb__DOT__clk))); & (~ (IData)(vlSelf->__Vtrigrprev__TOP__tb__DOT__clk)));
vlSelf->__VactTriggered.at(1U) = ((IData)(vlSelf->tb__DOT__bitti_mi) vlSelf->__VactTriggered.at(1U) = ((IData)(vlSelf->tb__DOT__bitti_mi)
& (~ (IData)(vlSelf->__Vtrigrprev__TOP__tb__DOT__bitti_mi))); & (~ (IData)(vlSelf->__Vtrigrprev__TOP__tb__DOT__bitti_mi)));
vlSelf->__VactTriggered.at(2U) = vlSelf->__VdlySched.awaitingCurrentTime(); vlSelf->__VactTriggered.at(2U) = vlSelf->__VdlySched.awaitingCurrentTime();
vlSelf->__Vtrigrprev__TOP__tb__DOT__clk = vlSelf->tb__DOT__clk; vlSelf->__Vtrigrprev__TOP__tb__DOT__clk = vlSelf->tb__DOT__clk;
vlSelf->__Vtrigrprev__TOP__tb__DOT__bitti_mi = vlSelf->tb__DOT__bitti_mi; vlSelf->__Vtrigrprev__TOP__tb__DOT__bitti_mi = vlSelf->tb__DOT__bitti_mi;
#ifdef VL_DEBUG #ifdef VL_DEBUG
if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) { if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {
Vtb___024root___dump_triggers__act(vlSelf); Vtb___024root___dump_triggers__act(vlSelf);
} }
#endif #endif
} }

50
tetirs/obj_dir/Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp → iverilog/tobb/lab7tetris/obj_dir/Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp
View File

@ -1,25 +1,25 @@
// Verilated -*- C++ -*- // Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals // DESCRIPTION: Verilator output: Design implementation internals
// See Vtb.h for the primary calling header // See Vtb.h for the primary calling header
#include "verilated.h" #include "verilated.h"
#include "Vtb__Syms.h" #include "Vtb__Syms.h"
#include "Vtb___024root.h" #include "Vtb___024root.h"
#ifdef VL_DEBUG #ifdef VL_DEBUG
VL_ATTR_COLD void Vtb___024root___dump_triggers__stl(Vtb___024root* vlSelf); VL_ATTR_COLD void Vtb___024root___dump_triggers__stl(Vtb___024root* vlSelf);
#endif // VL_DEBUG #endif // VL_DEBUG
VL_ATTR_COLD void Vtb___024root___eval_triggers__stl(Vtb___024root* vlSelf) { VL_ATTR_COLD void Vtb___024root___eval_triggers__stl(Vtb___024root* vlSelf) {
if (false && vlSelf) {} // Prevent unused if (false && vlSelf) {} // Prevent unused
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_triggers__stl\n"); ); VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_triggers__stl\n"); );
// Body // Body
vlSelf->__VstlTriggered.at(0U) = (0U == vlSelf->__VstlIterCount); vlSelf->__VstlTriggered.at(0U) = (0U == vlSelf->__VstlIterCount);
#ifdef VL_DEBUG #ifdef VL_DEBUG
if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) { if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {
Vtb___024root___dump_triggers__stl(vlSelf); Vtb___024root___dump_triggers__stl(vlSelf);
} }
#endif #endif
} }

52
tetirs/obj_dir/Vtb___024root__Slow.cpp → iverilog/tobb/lab7tetris/obj_dir/Vtb___024root__Slow.cpp
View File

@ -1,26 +1,26 @@
// Verilated -*- C++ -*- // Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals // DESCRIPTION: Verilator output: Design implementation internals
// See Vtb.h for the primary calling header // See Vtb.h for the primary calling header
#include "verilated.h" #include "verilated.h"
#include "Vtb__Syms.h" #include "Vtb__Syms.h"
#include "Vtb___024root.h" #include "Vtb___024root.h"
void Vtb___024root___ctor_var_reset(Vtb___024root* vlSelf); void Vtb___024root___ctor_var_reset(Vtb___024root* vlSelf);
Vtb___024root::Vtb___024root(Vtb__Syms* symsp, const char* v__name) Vtb___024root::Vtb___024root(Vtb__Syms* symsp, const char* v__name)
: VerilatedModule{v__name} : VerilatedModule{v__name}
, __VdlySched{*symsp->_vm_contextp__} , __VdlySched{*symsp->_vm_contextp__}
, vlSymsp{symsp} , vlSymsp{symsp}
{ {
// Reset structure values // Reset structure values
Vtb___024root___ctor_var_reset(this); Vtb___024root___ctor_var_reset(this);
} }
void Vtb___024root::__Vconfigure(bool first) { void Vtb___024root::__Vconfigure(bool first) {
if (false && first) {} // Prevent unused if (false && first) {} // Prevent unused
} }
Vtb___024root::~Vtb___024root() { Vtb___024root::~Vtb___024root() {
} }

68
tetirs/obj_dir/Vtb__main.cpp → iverilog/tobb/lab7tetris/obj_dir/Vtb__main.cpp
View File

@ -1,34 +1,34 @@
// Verilated -*- C++ -*- // Verilated -*- C++ -*-
// DESCRIPTION: main() calling loop, created with Verilator --main // DESCRIPTION: main() calling loop, created with Verilator --main
#include "verilated.h" #include "verilated.h"
#include "Vtb.h" #include "Vtb.h"
//====================== //======================
int main(int argc, char** argv, char**) { int main(int argc, char** argv, char**) {
// Setup context, defaults, and parse command line // Setup context, defaults, and parse command line
Verilated::debug(0); Verilated::debug(0);
const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext}; const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
contextp->commandArgs(argc, argv); contextp->commandArgs(argc, argv);
// Construct the Verilated model, from Vtop.h generated from Verilating // Construct the Verilated model, from Vtop.h generated from Verilating
const std::unique_ptr<Vtb> topp{new Vtb{contextp.get()}}; const std::unique_ptr<Vtb> topp{new Vtb{contextp.get()}};
// Simulate until $finish // Simulate until $finish
while (!contextp->gotFinish()) { while (!contextp->gotFinish()) {
// Evaluate model // Evaluate model
topp->eval(); topp->eval();
// Advance time // Advance time
if (!topp->eventsPending()) break; if (!topp->eventsPending()) break;
contextp->time(topp->nextTimeSlot()); contextp->time(topp->nextTimeSlot());
} }
if (!contextp->gotFinish()) { if (!contextp->gotFinish()) {
VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n");); VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n"););
} }
// Final model cleanup // Final model cleanup
topp->final(); topp->final();
return 0; return 0;
} }

2
tetirs/obj_dir/Vtb__ver.d → iverilog/tobb/lab7tetris/obj_dir/Vtb__ver.d
View File

@ -1 +1 @@
obj_dir/Vtb.cpp obj_dir/Vtb.h obj_dir/Vtb.mk obj_dir/Vtb__Syms.cpp obj_dir/Vtb__Syms.h obj_dir/Vtb___024root.h obj_dir/Vtb___024root__DepSet_ha183790c__0.cpp obj_dir/Vtb___024root__DepSet_ha183790c__0__Slow.cpp obj_dir/Vtb___024root__DepSet_hfe20aad3__0.cpp obj_dir/Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp obj_dir/Vtb___024root__Slow.cpp obj_dir/Vtb__main.cpp obj_dir/Vtb__ver.d obj_dir/Vtb_classes.mk : /usr/bin/verilator_bin /usr/bin/verilator_bin tb.v tetris.v obj_dir/Vtb.cpp obj_dir/Vtb.h obj_dir/Vtb.mk obj_dir/Vtb__Syms.cpp obj_dir/Vtb__Syms.h obj_dir/Vtb___024root.h obj_dir/Vtb___024root__DepSet_ha183790c__0.cpp obj_dir/Vtb___024root__DepSet_ha183790c__0__Slow.cpp obj_dir/Vtb___024root__DepSet_hfe20aad3__0.cpp obj_dir/Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp obj_dir/Vtb___024root__Slow.cpp obj_dir/Vtb__main.cpp obj_dir/Vtb__ver.d obj_dir/Vtb_classes.mk : /usr/bin/verilator_bin /usr/bin/verilator_bin tb.v tetris.v

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