13 lines
242 B
Verilog
13 lines
242 B
Verilog
module fullAdder (
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input A,
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input B,
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input Cin,
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output S,
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output Cout
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);
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wire AxB, AnB1, AnB2;
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halfadder h1(A, B, AxB, AnB2);
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halfadder h2(AxB, Cin, S, AnB1);
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or o1(Cout, AnB1, AnB2);
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endmodule |