30 lines
1.6 KiB
Plaintext
30 lines
1.6 KiB
Plaintext
Reading netlist file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg"
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Parsing netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg" completed
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Processing netlist completed
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Reading constraint file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fpga_project.cst"
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Physical Constraint parsed completed
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Running placement......
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[10%] Placement Phase 0 completed
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[20%] Placement Phase 1 completed
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[30%] Placement Phase 2 completed
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[50%] Placement Phase 3 completed
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Running routing......
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[60%] Routing Phase 0 completed
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[70%] Routing Phase 1 completed
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[80%] Routing Phase 2 completed
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[90%] Routing Phase 3 completed
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Running timing analysis......
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[95%] Timing analysis completed
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Placement and routing completed
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Bitstream generation in progress......
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Bitstream generation completed
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Running power analysis......
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[100%] Power analysis completed
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Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.power.html" completed
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Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.pin.html" completed
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Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.rpt.html" completed
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Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.rpt.txt" completed
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Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.tr.html" completed
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Fri Jul 5 01:48:07 2024
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