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• c34a3aa203 fixed main k0rrluna 2025-01-23 07:57:10 +03:00
• d4d35b4983 gowin impl removed because f# k0rrluna 2025-01-23 07:56:15 +03:00
• 91280fbab2 small fix k0rrluna 2025-01-23 07:51:49 +03:00
• f233866913 small fix kaltinsoy 2025-01-23 07:51:05 +03:00
• 0659f966b8 small fix k0rrluna 2025-01-23 07:34:36 +03:00
• 806d09692f small fix k0rrluna 2025-01-23 07:26:34 +03:00
• 2cf2de94d9 small changes k0rrluna 2025-01-23 07:22:58 +03:00
• 6080927957 small changes k0rrluna 2025-01-23 07:16:59 +03:00
• 5b3ff5bf91 Fix Verilog syntax highlighting k0rrluna 2025-01-23 07:15:21 +03:00
• 4cae830727 github language k0rrluna 2025-01-23 07:10:16 +03:00
• 9315033686 Fix Verilog file syntax highlighting k0rrluna 2025-01-23 07:09:08 +03:00
• 7194531692 Fix Verilog file syntax highlighting k0rrluna 2025-01-23 07:06:17 +03:00
• 3947f28bb5 Update README.md k0rrluna 2025-01-23 07:03:14 +03:00
• 8f854d046b initial commit k0rrluna 2025-01-23 06:58:05 +03:00
• 8579de5ebc Initial commit kaltinsoy 2025-01-23 03:06:06 +03:00