small changes

2025-01-23 07:16:59 +03:00
parent 5b3ff5bf91
commit 6080927957
62 changed files with 0 additions and 124 deletions
--- a/logisim/subraction.circZone.Identifier
+++ b/logisim/subraction.circZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/!NOTUSE!overflowDetect.vZone.Identifier
+++ b/verilog/ALU0.2/!NOTUSE!overflowDetect.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/!NOTUSE!selector.vZone.Identifier
+++ b/verilog/ALU0.2/!NOTUSE!selector.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/ALU.vcdZone.Identifier
+++ b/verilog/ALU0.2/ALU.vcdZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/ALU.vZone.Identifier
+++ b/verilog/ALU0.2/ALU.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/ALUTB.vZone.Identifier
+++ b/verilog/ALU0.2/ALUTB.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/ALUZone.Identifier
+++ b/verilog/ALU0.2/ALUZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/BinaryToBCD.vcdZone.Identifier
+++ b/verilog/ALU0.2/BinaryToBCD.vcdZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/BinaryToBCD.vZone.Identifier
+++ b/verilog/ALU0.2/BinaryToBCD.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/BinaryToBCDTB.vZone.Identifier
+++ b/verilog/ALU0.2/BinaryToBCDTB.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/addition.vZone.Identifier
+++ b/verilog/ALU0.2/addition.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/arithmeticUnit.vZone.Identifier
+++ b/verilog/ALU0.2/arithmeticUnit.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/binarytobcdZone.Identifier
+++ b/verilog/ALU0.2/binarytobcdZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/dabble.vZone.Identifier
+++ b/verilog/ALU0.2/dabble.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/dabbleZone.Identifier
+++ b/verilog/ALU0.2/dabbleZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/divider.vZone.Identifier
+++ b/verilog/ALU0.2/divider.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/fulladder.vZone.Identifier
+++ b/verilog/ALU0.2/fulladder.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/fullsubtraction.vZone.Identifier
+++ b/verilog/ALU0.2/fullsubtraction.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/halfadder.vZone.Identifier
+++ b/verilog/ALU0.2/halfadder.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/halfsubtraction.vZone.Identifier
+++ b/verilog/ALU0.2/halfsubtraction.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/logicUnit.vcdZone.Identifier
+++ b/verilog/ALU0.2/logicUnit.vcdZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/logicUnit.vZone.Identifier
+++ b/verilog/ALU0.2/logicUnit.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/logicUnitTB.vZone.Identifier
+++ b/verilog/ALU0.2/logicUnitTB.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/logicUnitZone.Identifier
+++ b/verilog/ALU0.2/logicUnitZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/multiplier.vcdZone.Identifier
+++ b/verilog/ALU0.2/multiplier.vcdZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/multiplier.vZone.Identifier
+++ b/verilog/ALU0.2/multiplier.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/multiplierTB.vZone.Identifier
+++ b/verilog/ALU0.2/multiplierTB.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/multiplierZone.Identifier
+++ b/verilog/ALU0.2/multiplierZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/opCode.vcdZone.Identifier
+++ b/verilog/ALU0.2/opCode.vcdZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/opCode.vZone.Identifier
+++ b/verilog/ALU0.2/opCode.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/opCodeTB.vZone.Identifier
+++ b/verilog/ALU0.2/opCodeTB.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/opCodeZone.Identifier
+++ b/verilog/ALU0.2/opCodeZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/selectorTB.vZone.Identifier
+++ b/verilog/ALU0.2/selectorTB.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/subtraction.vcdZone.Identifier
+++ b/verilog/ALU0.2/subtraction.vcdZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/subtraction.vZone.Identifier
+++ b/verilog/ALU0.2/subtraction.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/subtractionTB.vZone.Identifier
+++ b/verilog/ALU0.2/subtractionTB.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALU0.2/subtractionZone.Identifier
+++ b/verilog/ALU0.2/subtractionZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/ALU.vcdZone.Identifier
+++ b/verilog/ALUTangTest/ALU.vcdZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/ALU.vZone.Identifier
+++ b/verilog/ALUTangTest/ALU.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/ALUtb.vZone.Identifier
+++ b/verilog/ALUTangTest/ALUtb.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/ALUZone.Identifier
+++ b/verilog/ALUTangTest/ALUZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/BinaryToBCD.vZone.Identifier
+++ b/verilog/ALUTangTest/BinaryToBCD.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/addition.vZone.Identifier
+++ b/verilog/ALUTangTest/addition.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/arithmeticUnit.vZone.Identifier
+++ b/verilog/ALUTangTest/arithmeticUnit.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/compile.shZone.Identifier
+++ b/verilog/ALUTangTest/compile.shZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/dabble.vZone.Identifier
+++ b/verilog/ALUTangTest/dabble.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/fulladder.vZone.Identifier
+++ b/verilog/ALUTangTest/fulladder.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/fullsubtraction.vZone.Identifier
+++ b/verilog/ALUTangTest/fullsubtraction.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/halfadder.vZone.Identifier
+++ b/verilog/ALUTangTest/halfadder.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/halfsubtraction.vZone.Identifier
+++ b/verilog/ALUTangTest/halfsubtraction.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/logicUnit.vZone.Identifier
+++ b/verilog/ALUTangTest/logicUnit.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/mult.vcdZone.Identifier
+++ b/verilog/ALUTangTest/mult.vcdZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/multTB.vZone.Identifier
+++ b/verilog/ALUTangTest/multTB.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/multiplier.vZone.Identifier
+++ b/verilog/ALUTangTest/multiplier.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/multZone.Identifier
+++ b/verilog/ALUTangTest/multZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/opCode.vZone.Identifier
+++ b/verilog/ALUTangTest/opCode.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/selector.vZone.Identifier
+++ b/verilog/ALUTangTest/selector.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/subtraction.vZone.Identifier
+++ b/verilog/ALUTangTest/subtraction.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/top.vcdZone.Identifier
+++ b/verilog/ALUTangTest/top.vcdZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/top.vZone.Identifier
+++ b/verilog/ALUTangTest/top.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/topTB.vZone.Identifier
+++ b/verilog/ALUTangTest/topTB.vZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3
--- a/verilog/ALUTangTest/topZone.Identifier
+++ b/verilog/ALUTangTest/topZone.Identifier
@ -1,2 +0,0 @@
-[ZoneTransfer]
-ZoneId=3