kaltinsoy/4-bit-ALU
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Fix Verilog syntax highlighting

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k0rrluna 2025-01-23 07:15:21 +03:00
parent 4cae830727
commit 5b3ff5bf91
1 changed files with 3 additions and 1 deletions
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4
.gitattributes vendored
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@ -1 +1,3 @@
*.v linguist-language=verilog
*.v linguist-language=Verilog
*.sv linguist-language=SystemVerilog