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Author	SHA1	Message	Date
k0rrluna	9315033686	Fix Verilog file syntax highlighting	2025-01-23 07:09:08 +03:00
k0rrluna	7194531692	Fix Verilog file syntax highlighting	2025-01-23 07:06:17 +03:00
k0rrluna	3947f28bb5	Update README.md	2025-01-23 07:03:14 +03:00
k0rrluna	8f854d046b	initial commit	2025-01-23 06:58:05 +03:00
kaltinsoy	8579de5ebc	Initial commit	2025-01-23 03:06:06 +03:00