kaltinsoy/4-bit-ALU
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
7 Commits 1 Branch 0 Tags
Commit Graph

3 Commits

Author SHA1 Message Date
k0rrluna
5b3ff5bf91 Fix Verilog syntax highlighting 2025-01-23 07:15:21 +03:00
k0rrluna
9315033686 Fix Verilog file syntax highlighting 2025-01-23 07:09:08 +03:00
k0rrluna
7194531692 Fix Verilog file syntax highlighting 2025-01-23 07:06:17 +03:00