14 lines
200 B
Verilog
14 lines
200 B
Verilog
module adder3bit(
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input [2:0] A,
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input [2:0] B,
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output [3:0] C
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);
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wire c1, c2, c3, c4;
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ha a0(A[0], B[0], C[0], c1);
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fa a1(A[1], B[1], c1, C[1], c2);
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fa a2(A[2], B[2], c2, C[2], C[3]);
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endmodule
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