formatter test

iverilog/nand2tetris/nands/andGateTB.v

@@ -1,29 +1,29 @@
 module andGateTB ();
-  reg A, B;
+   reg A, B;
-  wire Y;
+   wire Y;
 
-  andGate uut (
+   andGate uut (
-      .A(A),
+       .A(A),
-      .B(B),
+       .B(B),
-      .Y(Y)
+       .Y(Y)
-  );
+   );
 
-  initial begin
+   initial begin
-    $dumpfile("andGate.vcd");
+      $dumpfile("andGate.vcd");
-    $dumpvars;
+      $dumpvars;
-    A = 1'b0;
+      A = 1'b0;
-    B = 1'b0;
+      B = 1'b0;
-    #10;
+      #10;
-    A = 1'b0;
+      A = 1'b0;
-    B = 1'b1;
+      B = 1'b1;
-    #10;
+      #10;
-    A = 1'b1;
+      A = 1'b1;
-    B = 1'b0;
+      B = 1'b0;
-    #10;
+      #10;
-    A = 1'b1;
+      A = 1'b1;
-    B = 1'b1;
+      B = 1'b1;
-    #10;
+      #10;
-    $finish;
+      $finish;
-  end
+   end
 
 endmodule

iverilog/nand2tetris/nands/notGate.v

@@ -1,5 +1,7 @@
-module notGate (input A,
+module notGate (
-                output B);
+    input  A,
-    
+    output B
-    nand nand1 (B, A, A);
+);
+
+   nand nand1 (B, A, A);
 endmodule

iverilog/nand2tetris/nands/notGateTB.v

@@ -1,20 +1,20 @@
 module notGateTB ();
 
-  reg  A;
+   reg  A;
-  wire B;
+   wire B;
 
-  notGate uut (
+   notGate uut (
-      .A(A),
+       .A(A),
-      .B(B)
+       .B(B)
-  );
+   );
 
-  initial begin
+   initial begin
-    $dumpfile("notGate.vcd");
+      $dumpfile("notGate.vcd");
-    $dumpvars;
+      $dumpvars;
-    A = 1'b0;
+      A = 1'b0;
-    #10;
+      #10;
-    A = 1'b1;
+      A = 1'b1;
-    #10;
+      #10;
-    $finish;
+      $finish;
-  end
+   end
 endmodule