21 lines
248 B
Verilog
21 lines
248 B
Verilog
module notGateTB ();
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reg A;
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wire B;
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notGate uut (
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.A(A),
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.B(B)
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);
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initial begin
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$dumpfile("notGate.vcd");
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$dumpvars;
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A = 1'b0;
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#10;
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A = 1'b1;
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#10;
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$finish;
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end
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endmodule
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