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formatter test

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This commit is contained in:
k0rrluna
2024-12-02 02:42:36 +03:00
parent 1cb96c9f9a
commit f0551ce34f
3 changed files with 45 additions and 43 deletions
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48
iverilog/nand2tetris/nands/andGateTB.v
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@@ -1,29 +1,29 @@
module andGateTB (); module andGateTB ();
reg A, B; reg A, B;
wire Y; wire Y;
andGate uut ( andGate uut (
.A(A), .A(A),
.B(B), .B(B),
.Y(Y) .Y(Y)
); );
initial begin initial begin
$dumpfile("andGate.vcd"); $dumpfile("andGate.vcd");
$dumpvars; $dumpvars;
A = 1'b0; A = 1'b0;
B = 1'b0; B = 1'b0;
#10; #10;
A = 1'b0; A = 1'b0;
B = 1'b1; B = 1'b1;
#10; #10;
A = 1'b1; A = 1'b1;
B = 1'b0; B = 1'b0;
#10; #10;
A = 1'b1; A = 1'b1;
B = 1'b1; B = 1'b1;
#10; #10;
$finish; $finish;
end end
endmodule endmodule

8
iverilog/nand2tetris/nands/notGate.v
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@@ -1,5 +1,7 @@
module notGate (input A, module notGate (
output B); input A,
output B
);
nand nand1 (B, A, A); nand nand1 (B, A, A);
endmodule endmodule

30
iverilog/nand2tetris/nands/notGateTB.v
View File

@@ -1,20 +1,20 @@
module notGateTB (); module notGateTB ();
reg A; reg A;
wire B; wire B;
notGate uut ( notGate uut (
.A(A), .A(A),
.B(B) .B(B)
); );
initial begin initial begin
$dumpfile("notGate.vcd"); $dumpfile("notGate.vcd");
$dumpvars; $dumpvars;
A = 1'b0; A = 1'b0;
#10; #10;
A = 1'b1; A = 1'b1;
#10; #10;
$finish; $finish;
end end
endmodule endmodule