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verilog

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k0rrluna
2024-04-13 05:48:55 +03:00
commit ed465dd690
61 changed files with 2719 additions and 0 deletions
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lab3/impl/temp/rtl_parser.result Normal file
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[
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
"InstLine" : 1,
"InstName" : "Adder3Bit",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
"ModuleLine" : 1,
"ModuleName" : "Adder3Bit"
}
]