kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nand2tetris

Browse Source
This commit is contained in:
k0rrluna
2024-12-10 01:25:05 +03:00
parent 2acbfd9d8d
commit c1d75786ef
31 changed files with 1058 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
iverilog/nand2tetris/nands/not/notGate.vcd Normal file
View File

@ -0,0 +1,27 @@
$date
Mon Dec 9 22:38:49 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module notGateTB $end
$var wire 1 ! B_o $end
$var reg 1 " A_i $end
$scope module uut $end
$var wire 1 " A_i $end
$var wire 1 ! B_o $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0"
1!
$end
#10
0!
1"
#20