kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nand2tetris

Browse Source
This commit is contained in:
k0rrluna
2024-12-10 01:25:05 +03:00
parent 2acbfd9d8d
commit c1d75786ef
31 changed files with 1058 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
iverilog/nand2tetris/nands/and16/andSixTGateTB.v Normal file
View File

@ -0,0 +1,26 @@
module andSixTGateTB();
reg [15:0] A_i;
reg [15:0] B_i;
wire [15:0] Y_o;
andSixTGate uut(
.A_i(A_i),
.B_i(B_i),
.Y_o(Y_o)
);
initial begin
$dumpfile("andSixTGate.vcd");
$dumpvars;
A_i = 16'b0000_0000_0000_0000; B_i = 16'b0000_0000_0000_0000; #10;
A_i = 16'b0000_0000_0000_0000; B_i = 16'b0000_0000_0000_0001; #10;
A_i = 16'b0000_0000_0000_0001; B_i = 16'b0000_0000_0000_0001; #10;
A_i = 16'b0000_0000_0100_0000; B_i = 16'b0000_0000_0000_0000; #10;
A_i = 16'b0000_0000_0100_0000; B_i = 16'b0000_0000_0100_0000; #10;
A_i = 16'b0000_0000_0000_0000; B_i = 16'b0000_0010_0000_0000; #10;
A_i = 16'b0000_0010_0000_0000; B_i = 16'b0000_0010_0000_0000; #10;
A_i = 16'b1111_1111_1111_1111; B_i = 16'b1111_1111_1111_1111; #10;
$finish;
end
endmodule