nand2tetris

iverilog/nand2tetris/nands/and16/andSixTGate.vcd

@@ -0,0 +1,309 @@
+$date
+	Tue Dec 10 00:39:27 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module andSixTGateTB $end
+$var wire 16 ! Y_o [15:0] $end
+$var reg 16 " A_i [15:0] $end
+$var reg 16 # B_i [15:0] $end
+$scope module uut $end
+$var wire 16 $ A_i [15:0] $end
+$var wire 16 % B_i [15:0] $end
+$var wire 16 & Y_o [15:0] $end
+$scope module a0 $end
+$var wire 1 ' A_i $end
+$var wire 1 ( B_i $end
+$var wire 1 ) Y_o $end
+$var wire 1 * nand_out $end
+$upscope $end
+$scope module a1 $end
+$var wire 1 + A_i $end
+$var wire 1 , B_i $end
+$var wire 1 - Y_o $end
+$var wire 1 . nand_out $end
+$upscope $end
+$scope module a10 $end
+$var wire 1 / A_i $end
+$var wire 1 0 B_i $end
+$var wire 1 1 Y_o $end
+$var wire 1 2 nand_out $end
+$upscope $end
+$scope module a11 $end
+$var wire 1 3 A_i $end
+$var wire 1 4 B_i $end
+$var wire 1 5 Y_o $end
+$var wire 1 6 nand_out $end
+$upscope $end
+$scope module a12 $end
+$var wire 1 7 A_i $end
+$var wire 1 8 B_i $end
+$var wire 1 9 Y_o $end
+$var wire 1 : nand_out $end
+$upscope $end
+$scope module a13 $end
+$var wire 1 ; A_i $end
+$var wire 1 < B_i $end
+$var wire 1 = Y_o $end
+$var wire 1 > nand_out $end
+$upscope $end
+$scope module a14 $end
+$var wire 1 ? A_i $end
+$var wire 1 @ B_i $end
+$var wire 1 A Y_o $end
+$var wire 1 B nand_out $end
+$upscope $end
+$scope module a15 $end
+$var wire 1 C A_i $end
+$var wire 1 D B_i $end
+$var wire 1 E Y_o $end
+$var wire 1 F nand_out $end
+$upscope $end
+$scope module a2 $end
+$var wire 1 G A_i $end
+$var wire 1 H B_i $end
+$var wire 1 I Y_o $end
+$var wire 1 J nand_out $end
+$upscope $end
+$scope module a3 $end
+$var wire 1 K A_i $end
+$var wire 1 L B_i $end
+$var wire 1 M Y_o $end
+$var wire 1 N nand_out $end
+$upscope $end
+$scope module a4 $end
+$var wire 1 O A_i $end
+$var wire 1 P B_i $end
+$var wire 1 Q Y_o $end
+$var wire 1 R nand_out $end
+$upscope $end
+$scope module a5 $end
+$var wire 1 S A_i $end
+$var wire 1 T B_i $end
+$var wire 1 U Y_o $end
+$var wire 1 V nand_out $end
+$upscope $end
+$scope module a6 $end
+$var wire 1 W A_i $end
+$var wire 1 X B_i $end
+$var wire 1 Y Y_o $end
+$var wire 1 Z nand_out $end
+$upscope $end
+$scope module a7 $end
+$var wire 1 [ A_i $end
+$var wire 1 \ B_i $end
+$var wire 1 ] Y_o $end
+$var wire 1 ^ nand_out $end
+$upscope $end
+$scope module a8 $end
+$var wire 1 _ A_i $end
+$var wire 1 ` B_i $end
+$var wire 1 a Y_o $end
+$var wire 1 b nand_out $end
+$upscope $end
+$scope module a9 $end
+$var wire 1 c A_i $end
+$var wire 1 d B_i $end
+$var wire 1 e Y_o $end
+$var wire 1 f nand_out $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
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+#80