fpga
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							| @@ -17,7 +17,7 @@ | ||||
| //SecureMode: OFF | ||||
| //JTAGAsRegularIO: OFF | ||||
| //MultiBootSPIAddr: 0x00000000 | ||||
| //Created Time: Mon Jan 20 18:31:01 2025 | ||||
| //Created Time: Tue Jan 21 15:29:08 2025 | ||||
| 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 | ||||
| 1111111111111111 | ||||
| 1010010111000011 | ||||
|   | ||||
| @@ -25,5 +25,5 @@ Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pn | ||||
| Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.rpt.html" completed | ||||
| Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.rpt.txt" completed | ||||
| Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.tr.html" completed | ||||
| Mon Jan 20 18:31:08 2025 | ||||
| Tue Jan 21 15:29:17 2025 | ||||
|  | ||||
|   | ||||
| @@ -78,7 +78,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; } | ||||
| </tr> | ||||
| <tr> | ||||
| <td class="label">Created Time</td> | ||||
| <td>Mon Jan 20 18:31:05 2025 | ||||
| <td>Tue Jan 21 15:29:12 2025 | ||||
| </td> | ||||
| </tr> | ||||
| <tr> | ||||
|   | ||||
| @@ -89,7 +89,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; } | ||||
| </tr> | ||||
| <tr> | ||||
| <td class="label">Created Time</td> | ||||
| <td>Mon Jan 20 18:31:05 2025 | ||||
| <td>Tue Jan 21 15:29:12 2025 | ||||
| </td> | ||||
| </tr> | ||||
| <tr> | ||||
|   | ||||
| @@ -83,7 +83,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; } | ||||
| </tr> | ||||
| <tr> | ||||
| <td class="label">Created Time</td> | ||||
| <td>Mon Jan 20 18:31:06 2025 | ||||
| <td>Tue Jan 21 15:29:14 2025 | ||||
| </td> | ||||
| </tr> | ||||
| <tr> | ||||
| @@ -97,24 +97,24 @@ table.detail_table th.label {  min-width: 8%; width: 8%; } | ||||
| <tr> | ||||
| <td class="label">Place & Route Process</td> | ||||
| <td>Running placement: | ||||
|    Placement Phase 0: CPU time = 0h 0m 0.025s, Elapsed time = 0h 0m 0.025s | ||||
|    Placement Phase 1: CPU time = 0h 0m 0.346s, Elapsed time = 0h 0m 0.345s | ||||
|    Placement Phase 2: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.008s | ||||
|    Placement Phase 0: CPU time = 0h 0m 0.131s, Elapsed time = 0h 0m 0.131s | ||||
|    Placement Phase 1: CPU time = 0h 0m 0.403s, Elapsed time = 0h 0m 0.402s | ||||
|    Placement Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s | ||||
|    Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s | ||||
|    Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s | ||||
| Running routing: | ||||
|    Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s | ||||
|    Routing Phase 1: CPU time = 0h 0m 0.178s, Elapsed time = 0h 0m 0.177s | ||||
|    Routing Phase 2: CPU time = 0h 0m 0.228s, Elapsed time = 0h 0m 0.228s | ||||
|    Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.001s | ||||
|    Routing Phase 1: CPU time = 0h 0m 0.21s, Elapsed time = 0h 0m 0.21s | ||||
|    Routing Phase 2: CPU time = 0h 0m 0.263s, Elapsed time = 0h 0m 0.264s | ||||
|    Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s | ||||
|    Total Routing: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.405s | ||||
|    Total Routing: CPU time = 0h 0m 0.475s, Elapsed time = 0h 0m 0.475s | ||||
| Generate output files: | ||||
|    CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s | ||||
|    CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s | ||||
| </td> | ||||
| </tr> | ||||
| <tr> | ||||
| <td class="label">Total Time and Memory Usage</td> | ||||
| <td>CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 433MB</td> | ||||
| <td>CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 413MB</td> | ||||
| </tr> | ||||
| </table> | ||||
| <br/> | ||||
|   | ||||
| @@ -12,27 +12,27 @@ | ||||
|   <Part Number>: GW2A-LV18PG256C8/I7 | ||||
|   <Device>: GW2A-18 | ||||
|   <Device Version>: C | ||||
|   <Created Time>:Mon Jan 20 18:31:08 2025 | ||||
|   <Created Time>:Tue Jan 21 15:29:16 2025 | ||||
|  | ||||
|  | ||||
| 2. PnR Details | ||||
|  | ||||
|   Running placement: | ||||
|     Placement Phase 0: CPU time = 0h 0m 0.025s, Elapsed time = 0h 0m 0.025s | ||||
|     Placement Phase 1: CPU time = 0h 0m 0.346s, Elapsed time = 0h 0m 0.345s | ||||
|     Placement Phase 2: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.008s | ||||
|     Placement Phase 0: CPU time = 0h 0m 0.131s, Elapsed time = 0h 0m 0.131s | ||||
|     Placement Phase 1: CPU time = 0h 0m 0.403s, Elapsed time = 0h 0m 0.402s | ||||
|     Placement Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s | ||||
|     Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s | ||||
|     Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s | ||||
|  Running routing: | ||||
|     Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s | ||||
|     Routing Phase 1: CPU time = 0h 0m 0.178s, Elapsed time = 0h 0m 0.177s | ||||
|     Routing Phase 2: CPU time = 0h 0m 0.228s, Elapsed time = 0h 0m 0.228s | ||||
|     Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.001s | ||||
|     Routing Phase 1: CPU time = 0h 0m 0.21s, Elapsed time = 0h 0m 0.21s | ||||
|     Routing Phase 2: CPU time = 0h 0m 0.263s, Elapsed time = 0h 0m 0.264s | ||||
|     Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s | ||||
|     Total Routing: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.405s | ||||
|     Total Routing: CPU time = 0h 0m 0.475s, Elapsed time = 0h 0m 0.475s | ||||
|  Generate output files: | ||||
|     CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s | ||||
|     CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s | ||||
|  | ||||
|  Total Time and Memory Usage: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 433MB | ||||
|  Total Time and Memory Usage: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 413MB | ||||
|  | ||||
|  | ||||
| 3. Resource Usage Summary | ||||
|   | ||||
| @@ -55,7 +55,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; } | ||||
| </tr> | ||||
| <tr> | ||||
| <td class="label">Created Time</td> | ||||
| <td>Mon Jan 20 18:31:08 2025 | ||||
| <td>Tue Jan 21 15:29:17 2025 | ||||
| </td> | ||||
| </tr> | ||||
| <tr> | ||||
|   | ||||
| @@ -5,6 +5,7 @@ set READY regular_io = false | ||||
| set DONE regular_io = false | ||||
| set I2C regular_io = false | ||||
| set RECONFIG_N regular_io = false | ||||
| set unused_pin = default | ||||
| set CRC_check = true | ||||
| set compress = false | ||||
| set encryption = false | ||||
| @@ -18,4 +19,3 @@ set format = binary | ||||
| set power_on_reset_monitor = true | ||||
| set multiboot_spi_flash_address = 0x00000000 | ||||
| set vccx = 3.3 | ||||
| set unused_pin = default | ||||
|   | ||||
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