verilog

2024-07-09 20:53:40 +03:00
parent 60e4f65988
commit 610e059b8a
20 changed files with 809 additions and 0 deletions
--- a/tests/test2.v
+++ b/tests/test2.v
@ -0,0 +1,8 @@
+module test2 (
+    input [3:0] a,
+    output [6:0] b
+);
+
+assign b = (1 << (a + 1)) - 2;
+
+endmodule