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lab7

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k0rrluna
2025-01-30 07:23:51 +03:00
parent 85dbb22740
commit 57c2935e1c
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iverilog/tobb/lab7/bib3A Normal file
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x5574a61fa040 .scope module, "bib3AdvancedTB" "bib3AdvancedTB" 2 1;
.timescale 0 0;
v0x5574a62143c0_0 .var "basla", 0 0;
v0x5574a6214480_0 .net "bitti", 0 0, v0x5574a6213cf0_0; 1 drivers
v0x5574a6214550_0 .var "buyruk", 8 0;
v0x5574a6214650_0 .var "clk", 0 0;
v0x5574a6214720_0 .var/i "i", 31 0;
v0x5574a62147c0 .array "memory", 0 15, 8 0;
v0x5574a6214860_0 .net "sonuc", 3 0, v0x5574a6214240_0; 1 drivers
S_0x5574a61fa1d0 .scope module, "uut" "bib3Advanced" 2 10, 3 1 0, S_0x5574a61fa040;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "basla";
.port_info 2 /INPUT 9 "buyruk";
.port_info 3 /OUTPUT 4 "sonuc";
.port_info 4 /OUTPUT 1 "bitti";
v0x5574a61bac00_0 .var/i "a", 31 0;
v0x5574a6213b70_0 .var/i "b", 31 0;
v0x5574a6213c50_0 .net "basla", 0 0, v0x5574a62143c0_0; 1 drivers
v0x5574a6213cf0_0 .var "bitti", 0 0;
v0x5574a6213db0_0 .net "buyruk", 8 0, v0x5574a6214550_0; 1 drivers
v0x5574a6213ee0_0 .var/i "c", 31 0;
v0x5574a6213fc0_0 .net "clk", 0 0, v0x5574a6214650_0; 1 drivers
v0x5574a6214080_0 .var/i "count", 31 0;
v0x5574a6214160_0 .var/i "i", 31 0;
v0x5574a6214240_0 .var "sonuc", 3 0;
E_0x5574a61f2a20 .event posedge, v0x5574a6213fc0_0;
.scope S_0x5574a61fa1d0;
T_0 ;
%wait E_0x5574a61f2a20;
%load/vec4 v0x5574a6213c50_0;
%flag_set/vec4 8;
%jmp/0xz T_0.0, 8;
%load/vec4 v0x5574a6213db0_0;
%parti/s 3, 6, 4;
%dup/vec4;
%pushi/vec4 0, 0, 3;
%cmp/u;
%jmp/1 T_0.3, 6;
%dup/vec4;
%pushi/vec4 1, 0, 3;
%cmp/u;
%jmp/1 T_0.4, 6;
%dup/vec4;
%pushi/vec4 2, 0, 3;
%cmp/u;
%jmp/1 T_0.5, 6;
%dup/vec4;
%pushi/vec4 3, 0, 3;
%cmp/u;
%jmp/1 T_0.6, 6;
%dup/vec4;
%pushi/vec4 4, 0, 3;
%cmp/u;
%jmp/1 T_0.7, 6;
%dup/vec4;
%pushi/vec4 5, 0, 3;
%cmp/u;
%jmp/1 T_0.8, 6;
%dup/vec4;
%pushi/vec4 6, 0, 3;
%cmp/u;
%jmp/1 T_0.9, 6;
%dup/vec4;
%pushi/vec4 7, 0, 3;
%cmp/u;
%jmp/1 T_0.10, 6;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x5574a6214240_0, 0;
%jmp T_0.11;
T_0.3 ;
%load/vec4 v0x5574a6213db0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x5574a6213db0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%add;
%assign/vec4 v0x5574a6214240_0, 0;
%jmp T_0.11;
T_0.4 ;
%load/vec4 v0x5574a6213db0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x5574a6213db0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%sub;
%assign/vec4 v0x5574a6214240_0, 0;
%jmp T_0.11;
T_0.5 ;
%load/vec4 v0x5574a6213db0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x5574a6213db0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%and;
%assign/vec4 v0x5574a6214240_0, 0;
%jmp T_0.11;
T_0.6 ;
%load/vec4 v0x5574a6213db0_0;
%parti/s 3, 3, 3;
%pad/u 4;
%load/vec4 v0x5574a6213db0_0;
%parti/s 3, 0, 2;
%pad/u 4;
%or;
%assign/vec4 v0x5574a6214240_0, 0;
%jmp T_0.11;
T_0.7 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x5574a6214160_0, 0, 32;
T_0.12 ;
%load/vec4 v0x5574a6214160_0;
%cmpi/s 4, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.13, 5;
%load/vec4 v0x5574a6213db0_0;
%load/vec4 v0x5574a6214160_0;
%part/s 1;
%load/vec4 v0x5574a6213db0_0;
%load/vec4 v0x5574a6214160_0;
%addi 1, 0, 32;
%part/s 1;
%cmp/e;
%jmp/0xz T_0.14, 4;
%pushi/vec4 15, 0, 4;
%assign/vec4 v0x5574a6214240_0, 0;
%jmp T_0.15;
T_0.14 ;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x5574a6214240_0, 0;
T_0.15 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x5574a6214160_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x5574a6214160_0, 0, 32;
%jmp T_0.12;
T_0.13 ;
%jmp T_0.11;
T_0.8 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x5574a61bac00_0, 0, 32;
T_0.16 ;
%load/vec4 v0x5574a61bac00_0;
%cmpi/s 5, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.17, 5;
%load/vec4 v0x5574a6213db0_0;
%load/vec4 v0x5574a61bac00_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.18, 4;
%pushi/vec4 15, 0, 4;
%assign/vec4 v0x5574a6214240_0, 0;
%jmp T_0.19;
T_0.18 ;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x5574a6214240_0, 0;
T_0.19 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x5574a61bac00_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x5574a61bac00_0, 0, 32;
%jmp T_0.16;
T_0.17 ;
%jmp T_0.11;
T_0.9 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x5574a6214080_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x5574a6213b70_0, 0, 32;
T_0.20 ;
%load/vec4 v0x5574a6213b70_0;
%cmpi/s 5, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.21, 5;
%load/vec4 v0x5574a6213db0_0;
%load/vec4 v0x5574a6213b70_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.22, 4;
%load/vec4 v0x5574a6214080_0;
%addi 1, 0, 32;
%store/vec4 v0x5574a6214080_0, 0, 32;
T_0.22 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x5574a6213b70_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x5574a6213b70_0, 0, 32;
%jmp T_0.20;
T_0.21 ;
%load/vec4 v0x5574a6214080_0;
%pushi/vec4 2, 0, 32;
%mod/s;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.24, 4;
%pushi/vec4 15, 0, 4;
%assign/vec4 v0x5574a6214240_0, 0;
%jmp T_0.25;
T_0.24 ;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x5574a6214240_0, 0;
T_0.25 ;
%jmp T_0.11;
T_0.10 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x5574a6214080_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x5574a6213ee0_0, 0, 32;
T_0.26 ;
%load/vec4 v0x5574a6213ee0_0;
%cmpi/s 5, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_0.27, 5;
%load/vec4 v0x5574a6213db0_0;
%load/vec4 v0x5574a6213ee0_0;
%part/s 1;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_0.28, 4;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x5574a6214080_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x5574a6214080_0, 0, 32;
T_0.28 ;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x5574a6213ee0_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x5574a6213ee0_0, 0, 32;
%jmp T_0.26;
T_0.27 ;
%load/vec4 v0x5574a6214080_0;
%pushi/vec4 2, 0, 32;
%mod/s;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.30, 4;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x5574a6214240_0, 0;
%jmp T_0.31;
T_0.30 ;
%pushi/vec4 15, 0, 4;
%assign/vec4 v0x5574a6214240_0, 0;
T_0.31 ;
%jmp T_0.11;
T_0.11 ;
%pop/vec4 1;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x5574a6213cf0_0, 0;
T_0.0 ;
%jmp T_0;
.thread T_0;
.scope S_0x5574a61fa040;
T_1 ;
%load/vec4 v0x5574a6214650_0;
%inv;
%store/vec4 v0x5574a6214650_0, 0, 1;
%delay 5, 0;
%jmp T_1;
.thread T_1;
.scope S_0x5574a61fa040;
T_2 ;
%vpi_call 2 25 "$dumpfile", "bib3Advanced.vcd" {0 0 0};
%vpi_call 2 26 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5574a6214650_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5574a62143c0_0, 0, 1;
%pushi/vec4 0, 0, 9;
%store/vec4 v0x5574a6214550_0, 0, 9;
%vpi_call 2 28 "$readmemb", "memory.mem", v0x5574a62147c0 {0 0 0};
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5574a62143c0_0, 0, 1;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x5574a6214720_0, 0, 32;
T_2.0 ;
%load/vec4 v0x5574a6214720_0;
%cmpi/s 16, 0, 32;
%flag_or 5, 4;
%jmp/0xz T_2.1, 5;
%ix/getv/s 4, v0x5574a6214720_0;
%load/vec4a v0x5574a62147c0, 4;
%store/vec4 v0x5574a6214550_0, 0, 9;
%delay 10, 0;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x5574a6214720_0;
%pushi/vec4 1, 0, 32;
%add;
%store/vec4 v0x5574a6214720_0, 0, 32;
%jmp T_2.0;
T_2.1 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5574a62143c0_0, 0, 1;
%delay 10, 0;
%vpi_call 2 36 "$finish" {0 0 0};
%end;
.thread T_2;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"bib3AdvancedTB.v";
"bib3Advanced.v";

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iverilog/tobb/lab7/bib3Advanced.v Normal file
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module bib3Advanced (
input clk,
input basla,
input [8:0] buyruk,
output reg [3:0] sonuc,
output reg bitti
);
integer i, a, b, c, count;
always@(posedge clk) begin
if(basla) begin
case (buyruk[8:6])
default: sonuc <= 4'b0000;
3'b000: sonuc <= buyruk[5:3] + buyruk[2:0];
3'b001: sonuc <= buyruk[5:3] - buyruk[2:0];
3'b010: sonuc <= buyruk[5:3] & buyruk[2:0];
3'b011: sonuc <= buyruk[5:3] | buyruk[2:0];
3'b100: begin
for (i = 0; i <= 4; i++)
if (buyruk[i] == buyruk[i+1])
sonuc <= 4'b1111;
else
sonuc <= 4'b0000;
end
3'b101: for (a = 0; a <= 5; a++) begin
if (buyruk[a] == 1)
sonuc <= 4'b1111;
else
sonuc <= 4'b0000;
end
3'b110: begin
count = 0;
for (b = 0; b <= 5; b++) begin
if (buyruk[b] == 1)
count = count + 1;
end
if (count % 2 == 0)
sonuc <= 4'b1111;
else
sonuc <= 4'b0000;
end
3'b111: begin
count = 0;
for (c = 0; c <= 5; c++)
if (buyruk[c] == 1)
count++;
if (count % 2 == 0)
sonuc <= 4'b0000;
else
sonuc <= 4'b1111;
end
endcase
bitti <= 1'b1;
end
end
endmodule

219
iverilog/tobb/lab7/bib3Advanced.vcd Normal file
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$date
Thu Jan 30 07:20:34 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module bib3AdvancedTB $end
$var wire 4 ! sonuc [3:0] $end
$var wire 1 " bitti $end
$var reg 1 # basla $end
$var reg 9 $ buyruk [8:0] $end
$var reg 1 % clk $end
$var integer 32 & i [31:0] $end
$scope module uut $end
$var wire 1 # basla $end
$var wire 9 ' buyruk [8:0] $end
$var wire 1 % clk $end
$var reg 1 " bitti $end
$var reg 4 ( sonuc [3:0] $end
$var integer 32 ) a [31:0] $end
$var integer 32 * b [31:0] $end
$var integer 32 + c [31:0] $end
$var integer 32 , count [31:0] $end
$var integer 32 - i [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx -
bx ,
bx +
bx *
bx )
bx (
b0 '
bx &
0%
b0 $
0#
x"
bx !
$end
#5
1%
#10
0%
b1001 $
b1001 '
b0 &
1#
#15
1"
b10 !
b10 (
1%
#20
0%
b1100001 $
b1100001 '
b1 &
#25
b11 !
b11 (
1%
#30
0%
b10100101 $
b10100101 '
b10 &
#35
b100 !
b100 (
1%
#40
0%
b11100011 $
b11100011 '
b11 &
#45
b111 !
b111 (
1%
#50
0%
b100111111 $
b100111111 '
b100 &
#55
b1111 !
b1111 (
b101 -
1%
#60
0%
b100100001 $
b100100001 '
b101 &
#65
b0 !
b0 (
b101 -
1%
#70
0%
b101100001 $
b101100001 '
b110 &
#75
b1111 !
b1111 (
b110 )
1%
#80
0%
b110100001 $
b110100001 '
b111 &
#85
b110 *
b10 ,
1%
#90
0%
b111100001 $
b111100001 '
b1000 &
#95
b0 !
b0 (
b110 +
b10 ,
1%
#100
0%
b1001 $
b1001 '
b1001 &
#105
b10 !
b10 (
1%
#110
0%
b1100001 $
b1100001 '
b1010 &
#115
b11 !
b11 (
1%
#120
0%
b10100101 $
b10100101 '
b1011 &
#125
b100 !
b100 (
1%
#130
0%
b11100011 $
b11100011 '
b1100 &
#135
b111 !
b111 (
1%
#140
0%
b100111111 $
b100111111 '
b1101 &
#145
b1111 !
b1111 (
b101 -
1%
#150
0%
b100100001 $
b100100001 '
b1110 &
#155
b0 !
b0 (
b101 -
1%
#160
0%
b101100001 $
b101100001 '
b1111 &
#165
b1111 !
b1111 (
b110 )
1%
#170
0%
bx $
bx '
b10000 &
#175
b0 !
b0 (
1%
#180
0%
0#
b10001 &
#185
1%
#190
0%

39
iverilog/tobb/lab7/bib3AdvancedTB.v Normal file
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module bib3AdvancedTB();
reg clk;
reg basla;
reg [8:0] buyruk;
reg [8:0] memory [15:0];
wire [3:0] sonuc;
wire bitti;
bib3Advanced uut (
.clk(clk),
.basla(basla),
.buyruk(buyruk),
.sonuc(sonuc),
.bitti(bitti)
);
always begin
clk = ~clk; #5;
end
integer i;
initial begin
$dumpfile("bib3Advanced.vcd");
$dumpvars;
clk = 0; basla = 0; buyruk = 9'b0_0000_0000;
$readmemb("memory.mem", memory); #10;
basla = 1'b1;
for(i = 0; i <= 16; i++) begin
buyruk = memory[i]; #10;
end
basla = 1'b0; #10;
$finish;
end
endmodule

16
iverilog/tobb/lab7/memory.mem Normal file
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@@ -0,0 +1,16 @@
000001001
001100001
010100101
011100011
100111111
100100001
101100001
110100001
111100001
000001001
001100001
010100101
011100011
100111111
100100001
101100001