40 lines
639 B
Verilog
40 lines
639 B
Verilog
module bib3AdvancedTB();
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reg clk;
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reg basla;
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reg [8:0] buyruk;
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reg [8:0] memory [15:0];
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wire [3:0] sonuc;
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wire bitti;
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bib3Advanced uut (
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.clk(clk),
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.basla(basla),
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.buyruk(buyruk),
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.sonuc(sonuc),
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.bitti(bitti)
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);
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always begin
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clk = ~clk; #5;
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end
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integer i;
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initial begin
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$dumpfile("bib3Advanced.vcd");
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$dumpvars;
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clk = 0; basla = 0; buyruk = 9'b0_0000_0000;
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$readmemb("memory.mem", memory); #10;
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basla = 1'b1;
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for(i = 0; i <= 16; i++) begin
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buyruk = memory[i]; #10;
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end
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basla = 1'b0; #10;
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$finish;
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end
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endmodule
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