56 lines
1.6 KiB
Verilog
56 lines
1.6 KiB
Verilog
module bib3Advanced (
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input clk,
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input basla,
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input [8:0] buyruk,
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output reg [3:0] sonuc,
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output reg bitti
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);
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integer i, a, b, c, count;
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always@(posedge clk) begin
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if(basla) begin
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case (buyruk[8:6])
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default: sonuc <= 4'b0000;
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3'b000: sonuc <= buyruk[5:3] + buyruk[2:0];
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3'b001: sonuc <= buyruk[5:3] - buyruk[2:0];
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3'b010: sonuc <= buyruk[5:3] & buyruk[2:0];
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3'b011: sonuc <= buyruk[5:3] | buyruk[2:0];
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3'b100: begin
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for (i = 0; i <= 4; i++)
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if (buyruk[i] == buyruk[i+1])
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sonuc <= 4'b1111;
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else
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sonuc <= 4'b0000;
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end
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3'b101: for (a = 0; a <= 5; a++) begin
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if (buyruk[a] == 1)
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sonuc <= 4'b1111;
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else
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sonuc <= 4'b0000;
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end
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3'b110: begin
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count = 0;
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for (b = 0; b <= 5; b++) begin
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if (buyruk[b] == 1)
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count = count + 1;
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end
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if (count % 2 == 0)
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sonuc <= 4'b1111;
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else
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sonuc <= 4'b0000;
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end
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3'b111: begin
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count = 0;
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for (c = 0; c <= 5; c++)
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if (buyruk[c] == 1)
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count++;
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if (count % 2 == 0)
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sonuc <= 4'b0000;
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else
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sonuc <= 4'b1111;
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end
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endcase
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bitti <= 1'b1;
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end
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end
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endmodule
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