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subtraction & multiplier

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k0rrluna
2024-12-20 21:28:15 +03:00
parent 8d4ec38521
commit 4363a50662
299 changed files with 6627 additions and 55786 deletions
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38
iverilog/tobb/lab2/HammingDistance/ham.vcd
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@ -1,38 +0,0 @@
$date
Wed Nov 6 15:42:14 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module htb $end
$var wire 4 ! hammingValue [3:0] $end
$var reg 8 " value1 [7:0] $end
$var reg 8 # value2 [7:0] $end
$scope module uut $end
$var wire 8 $ value1 [7:0] $end
$var wire 8 % value2 [7:0] $end
$var reg 4 & hammingValue [3:0] $end
$var integer 32 ' i [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b1000 '
b100 &
b10111111 %
b10110000 $
b10111111 #
b10110000 "
b100 !
$end
#10
b1000 '
b0 !
b0 &
b10111111 "
b10111111 $
#20

83
iverilog/tobb/lab2/HammingDistance/hamming
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@ -1,83 +0,0 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55be1d5c3f90 .scope module, "htb" "htb" 2 1;
.timescale 0 0;
v0x55be1d5d5ae0_0 .net "hammingValue", 3 0, v0x55be1d58ab00_0; 1 drivers
v0x55be1d5d5bd0_0 .var "value1", 7 0;
v0x55be1d5d5ca0_0 .var "value2", 7 0;
S_0x55be1d5c4120 .scope module, "uut" "hamming" 2 7, 3 1 0, S_0x55be1d5c3f90;
.timescale 0 0;
.port_info 0 /INPUT 8 "value1";
.port_info 1 /INPUT 8 "value2";
.port_info 2 /OUTPUT 4 "hammingValue";
v0x55be1d58ab00_0 .var "hammingValue", 3 0;
v0x55be1d58af10_0 .var/i "i", 31 0;
v0x55be1d5d58c0_0 .net "value1", 7 0, v0x55be1d5d5bd0_0; 1 drivers
v0x55be1d5d5980_0 .net "value2", 7 0, v0x55be1d5d5ca0_0; 1 drivers
E_0x55be1d589690 .event edge, v0x55be1d5d58c0_0, v0x55be1d5d5980_0, v0x55be1d58ab00_0;
.scope S_0x55be1d5c4120;
T_0 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55be1d58af10_0, 0, 32;
%end;
.thread T_0;
.scope S_0x55be1d5c4120;
T_1 ;
%wait E_0x55be1d589690;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55be1d58ab00_0, 0, 4;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55be1d58af10_0, 0, 32;
T_1.0 ;
%load/vec4 v0x55be1d58af10_0;
%cmpi/s 8, 0, 32;
%jmp/0xz T_1.1, 5;
%load/vec4 v0x55be1d5d58c0_0;
%load/vec4 v0x55be1d58af10_0;
%part/s 1;
%load/vec4 v0x55be1d5d5980_0;
%load/vec4 v0x55be1d58af10_0;
%part/s 1;
%cmp/ne;
%jmp/0xz T_1.2, 4;
%load/vec4 v0x55be1d58ab00_0;
%addi 1, 0, 4;
%store/vec4 v0x55be1d58ab00_0, 0, 4;
T_1.2 ;
%load/vec4 v0x55be1d58af10_0;
%addi 1, 0, 32;
%store/vec4 v0x55be1d58af10_0, 0, 32;
%jmp T_1.0;
T_1.1 ;
%jmp T_1;
.thread T_1, $push;
.scope S_0x55be1d5c3f90;
T_2 ;
%vpi_call 2 14 "$dumpfile", "ham.vcd" {0 0 0};
%vpi_call 2 15 "$dumpvars" {0 0 0};
%pushi/vec4 176, 0, 8;
%store/vec4 v0x55be1d5d5bd0_0, 0, 8;
%pushi/vec4 191, 0, 8;
%store/vec4 v0x55be1d5d5ca0_0, 0, 8;
%delay 10, 0;
%pushi/vec4 191, 0, 8;
%store/vec4 v0x55be1d5d5bd0_0, 0, 8;
%pushi/vec4 191, 0, 8;
%store/vec4 v0x55be1d5d5ca0_0, 0, 8;
%delay 10, 0;
%vpi_call 2 18 "$display", v0x55be1d5d5ae0_0 {0 0 0};
%end;
.thread T_2;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"htb.v";
"hamming.v";

17
iverilog/tobb/lab2/HammingDistance/hamming.v
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@ -1,17 +0,0 @@
module hamming (
input[7:0] value1,
input[7:0] value2,
output reg[3:0] hammingValue
);
integer i = 0;
always @(*) begin
hammingValue = 0;
for(i = 0; i < 8; i = i+1) begin
if (value1[i] != value2[i]) begin
hammingValue = hammingValue + 1;
end
end
end
endmodule

20
iverilog/tobb/lab2/HammingDistance/htb.v
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@ -1,20 +0,0 @@
module htb ();
reg [7:0] value1;
reg [7:0] value2;
wire [3:0] hammingValue;
hamming uut (
.value1(value1),
.value2(value2),
.hammingValue(hammingValue)
);
initial begin
$dumpfile("ham.vcd");
$dumpvars;
value1 = 8'hB0; value2 = 8'hBF; #10;
value1 = 8'hBF; value2 = 8'hBF; #10;
$display(hammingValue);
end
endmodule

40
iverilog/tobb/lab2/hadmp.vcd
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@ -1,40 +0,0 @@
$date
Tue Oct 8 10:23:08 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module halfaddertb $end
$var wire 1 ! S $end
$var wire 1 " C $end
$var reg 1 # A $end
$var reg 1 $ B $end
$scope module uut $end
$var wire 1 # A $end
$var wire 1 $ B $end
$var wire 1 " C $end
$var wire 1 ! S $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0$
0#
0"
0!
$end
#10
1!
1$
#20
0$
1#
#30
0!
1"
1$
#40

59
iverilog/tobb/lab2/halfadder
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@ -1,59 +0,0 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x5583f1e33260 .scope module, "halfaddertb" "halfaddertb" 2 1;
.timescale 0 0;
v0x5583f1e44440_0 .var "A", 0 0;
v0x5583f1e44500_0 .var "B", 0 0;
v0x5583f1e445d0_0 .net "C", 0 0, L_0x5583f1e44900; 1 drivers
v0x5583f1e446d0_0 .net "S", 0 0, L_0x5583f1e447a0; 1 drivers
S_0x5583f1e333f0 .scope module, "uut" "halfadder" 2 5, 3 1 0, S_0x5583f1e33260;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x5583f1e447a0 .functor XOR 1, v0x5583f1e44440_0, v0x5583f1e44500_0, C4<0>, C4<0>;
L_0x5583f1e44900 .functor AND 1, v0x5583f1e44440_0, v0x5583f1e44500_0, C4<1>, C4<1>;
v0x5583f1dfbc00_0 .net "A", 0 0, v0x5583f1e44440_0; 1 drivers
v0x5583f1e44140_0 .net "B", 0 0, v0x5583f1e44500_0; 1 drivers
v0x5583f1e44200_0 .net "C", 0 0, L_0x5583f1e44900; alias, 1 drivers
v0x5583f1e442d0_0 .net "S", 0 0, L_0x5583f1e447a0; alias, 1 drivers
.scope S_0x5583f1e33260;
T_0 ;
%vpi_call 2 10 "$dumpfile", "hadmp.vcd" {0 0 0};
%vpi_call 2 11 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5583f1e44440_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5583f1e44500_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5583f1e44440_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5583f1e44500_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5583f1e44440_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x5583f1e44500_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5583f1e44440_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x5583f1e44500_0, 0, 1;
%delay 10, 0;
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"halfaddertb.v";
"halfadder.v";

9
iverilog/tobb/lab2/halfadder.v
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@ -1,9 +0,0 @@
module halfadder (
input A,
input B,
output S,
output C
);
xor x1(S, A, B);
and a1(C, A, B);
endmodule

18
iverilog/tobb/lab2/halfaddertb.v
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@ -1,18 +0,0 @@
module halfaddertb ();
reg A, B;
wire S, C;
halfadder uut(
.A(A), .B(B), .S(S), .C(C)
);
initial begin
$dumpfile("hadmp.vcd");
$dumpvars;
A = 1'b0; B = 1'b0; #10;
A = 1'b0; B = 1'b1; #10;
A = 1'b1; B = 1'b0; #10;
A = 1'b1; B = 1'b1; #10;
end
endmodule