2024-12-01 02:01:08 +03:00

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$date
Wed Nov 6 15:42:14 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module htb $end
$var wire 4 ! hammingValue [3:0] $end
$var reg 8 " value1 [7:0] $end
$var reg 8 # value2 [7:0] $end
$scope module uut $end
$var wire 8 $ value1 [7:0] $end
$var wire 8 % value2 [7:0] $end
$var reg 4 & hammingValue [3:0] $end
$var integer 32 ' i [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b1000 '
b100 &
b10111111 %
b10110000 $
b10111111 #
b10110000 "
b100 !
$end
#10
b1000 '
b0 !
b0 &
b10111111 "
b10111111 $
#20