labs
This commit is contained in:
parent
57c2935e1c
commit
1d5ff13ca1
@ -7,40 +7,42 @@
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
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S_0x5574a61fa040 .scope module, "bib3AdvancedTB" "bib3AdvancedTB" 2 1;
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S_0x55a2c2765ba0 .scope module, "bib3AdvancedTB" "bib3AdvancedTB" 2 1;
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.timescale 0 0;
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v0x5574a62143c0_0 .var "basla", 0 0;
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v0x5574a6214480_0 .net "bitti", 0 0, v0x5574a6213cf0_0; 1 drivers
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v0x5574a6214550_0 .var "buyruk", 8 0;
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v0x5574a6214650_0 .var "clk", 0 0;
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v0x5574a6214720_0 .var/i "i", 31 0;
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v0x5574a62147c0 .array "memory", 0 15, 8 0;
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v0x5574a6214860_0 .net "sonuc", 3 0, v0x5574a6214240_0; 1 drivers
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S_0x5574a61fa1d0 .scope module, "uut" "bib3Advanced" 2 10, 3 1 0, S_0x5574a61fa040;
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v0x55a2c2780cc0_0 .var "basla", 0 0;
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v0x55a2c2780d80_0 .net "bitti", 0 0, v0x55a2c27805f0_0; 1 drivers
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v0x55a2c2780e50_0 .var "buyruk", 8 0;
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v0x55a2c2780f50_0 .var "clk", 0 0;
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v0x55a2c2781020_0 .var/i "i", 31 0;
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v0x55a2c27810c0 .array "memory", 15 0, 8 0;
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v0x55a2c2781160_0 .net "sonuc", 3 0, v0x55a2c2780b40_0; 1 drivers
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S_0x55a2c2765d30 .scope module, "uut" "bib3Advanced" 2 10, 3 1 0, S_0x55a2c2765ba0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "clk";
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.port_info 1 /INPUT 1 "basla";
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.port_info 2 /INPUT 9 "buyruk";
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.port_info 3 /OUTPUT 4 "sonuc";
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.port_info 4 /OUTPUT 1 "bitti";
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v0x5574a61bac00_0 .var/i "a", 31 0;
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v0x5574a6213b70_0 .var/i "b", 31 0;
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v0x5574a6213c50_0 .net "basla", 0 0, v0x5574a62143c0_0; 1 drivers
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v0x5574a6213cf0_0 .var "bitti", 0 0;
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v0x5574a6213db0_0 .net "buyruk", 8 0, v0x5574a6214550_0; 1 drivers
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v0x5574a6213ee0_0 .var/i "c", 31 0;
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v0x5574a6213fc0_0 .net "clk", 0 0, v0x5574a6214650_0; 1 drivers
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v0x5574a6214080_0 .var/i "count", 31 0;
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v0x5574a6214160_0 .var/i "i", 31 0;
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v0x5574a6214240_0 .var "sonuc", 3 0;
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E_0x5574a61f2a20 .event posedge, v0x5574a6213fc0_0;
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.scope S_0x5574a61fa1d0;
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v0x55a2c2723c00_0 .var/i "a", 31 0;
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v0x55a2c2780470_0 .var/i "b", 31 0;
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v0x55a2c2780550_0 .net "basla", 0 0, v0x55a2c2780cc0_0; 1 drivers
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v0x55a2c27805f0_0 .var "bitti", 0 0;
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v0x55a2c27806b0_0 .net "buyruk", 8 0, v0x55a2c2780e50_0; 1 drivers
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v0x55a2c27807e0_0 .var/i "c", 31 0;
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v0x55a2c27808c0_0 .net "clk", 0 0, v0x55a2c2780f50_0; 1 drivers
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v0x55a2c2780980_0 .var/i "count", 31 0;
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v0x55a2c2780a60_0 .var/i "i", 31 0;
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v0x55a2c2780b40_0 .var "sonuc", 3 0;
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E_0x55a2c275ba20 .event posedge, v0x55a2c27808c0_0;
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.scope S_0x55a2c2765d30;
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T_0 ;
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%wait E_0x5574a61f2a20;
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%load/vec4 v0x5574a6213c50_0;
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%wait E_0x55a2c275ba20;
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%load/vec4 v0x55a2c2780550_0;
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%flag_set/vec4 8;
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%jmp/0xz T_0.0, 8;
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%load/vec4 v0x5574a6213db0_0;
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%pushi/vec4 0, 0, 1;
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%assign/vec4 v0x55a2c27805f0_0, 0;
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%load/vec4 v0x55a2c27806b0_0;
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%parti/s 3, 6, 4;
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%dup/vec4;
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%pushi/vec4 0, 0, 3;
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@ -75,240 +77,258 @@ T_0 ;
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%cmp/u;
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%jmp/1 T_0.10, 6;
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%pushi/vec4 0, 0, 4;
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%assign/vec4 v0x5574a6214240_0, 0;
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%assign/vec4 v0x55a2c2780b40_0, 0;
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%jmp T_0.11;
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T_0.3 ;
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%load/vec4 v0x5574a6213db0_0;
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%load/vec4 v0x55a2c27806b0_0;
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%parti/s 3, 3, 3;
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%pad/u 4;
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%load/vec4 v0x5574a6213db0_0;
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%load/vec4 v0x55a2c27806b0_0;
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%parti/s 3, 0, 2;
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%pad/u 4;
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%add;
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%assign/vec4 v0x5574a6214240_0, 0;
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%assign/vec4 v0x55a2c2780b40_0, 0;
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%pushi/vec4 1, 0, 1;
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%assign/vec4 v0x55a2c27805f0_0, 0;
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%jmp T_0.11;
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T_0.4 ;
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%load/vec4 v0x5574a6213db0_0;
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%load/vec4 v0x55a2c27806b0_0;
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%parti/s 3, 3, 3;
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%pad/u 4;
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%load/vec4 v0x5574a6213db0_0;
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%load/vec4 v0x55a2c27806b0_0;
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%parti/s 3, 0, 2;
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%pad/u 4;
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%sub;
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%assign/vec4 v0x5574a6214240_0, 0;
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%assign/vec4 v0x55a2c2780b40_0, 0;
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%pushi/vec4 1, 0, 1;
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%assign/vec4 v0x55a2c27805f0_0, 0;
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%jmp T_0.11;
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T_0.5 ;
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%load/vec4 v0x5574a6213db0_0;
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%load/vec4 v0x55a2c27806b0_0;
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%parti/s 3, 3, 3;
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%pad/u 4;
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%load/vec4 v0x5574a6213db0_0;
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%load/vec4 v0x55a2c27806b0_0;
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%parti/s 3, 0, 2;
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%pad/u 4;
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%and;
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%assign/vec4 v0x5574a6214240_0, 0;
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%assign/vec4 v0x55a2c2780b40_0, 0;
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%pushi/vec4 1, 0, 1;
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%assign/vec4 v0x55a2c27805f0_0, 0;
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%jmp T_0.11;
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T_0.6 ;
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%load/vec4 v0x5574a6213db0_0;
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%load/vec4 v0x55a2c27806b0_0;
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%parti/s 3, 3, 3;
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%pad/u 4;
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%load/vec4 v0x5574a6213db0_0;
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%load/vec4 v0x55a2c27806b0_0;
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%parti/s 3, 0, 2;
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%pad/u 4;
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%or;
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%assign/vec4 v0x5574a6214240_0, 0;
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%assign/vec4 v0x55a2c2780b40_0, 0;
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%pushi/vec4 1, 0, 1;
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%assign/vec4 v0x55a2c27805f0_0, 0;
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%jmp T_0.11;
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T_0.7 ;
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%pushi/vec4 0, 0, 32;
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%store/vec4 v0x5574a6214160_0, 0, 32;
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%store/vec4 v0x55a2c2780a60_0, 0, 32;
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T_0.12 ;
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%load/vec4 v0x5574a6214160_0;
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%load/vec4 v0x55a2c2780a60_0;
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%cmpi/s 4, 0, 32;
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%flag_or 5, 4;
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%jmp/0xz T_0.13, 5;
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%load/vec4 v0x5574a6213db0_0;
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%load/vec4 v0x5574a6214160_0;
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%load/vec4 v0x55a2c27806b0_0;
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%load/vec4 v0x55a2c2780a60_0;
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%part/s 1;
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%load/vec4 v0x5574a6213db0_0;
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%load/vec4 v0x5574a6214160_0;
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%load/vec4 v0x55a2c27806b0_0;
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%load/vec4 v0x55a2c2780a60_0;
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%addi 1, 0, 32;
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%part/s 1;
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%cmp/e;
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%jmp/0xz T_0.14, 4;
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%pushi/vec4 15, 0, 4;
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%assign/vec4 v0x5574a6214240_0, 0;
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%assign/vec4 v0x55a2c2780b40_0, 0;
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%jmp T_0.15;
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T_0.14 ;
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%pushi/vec4 0, 0, 4;
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%assign/vec4 v0x5574a6214240_0, 0;
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%assign/vec4 v0x55a2c2780b40_0, 0;
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T_0.15 ;
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; show_stmt_assign_vector: Get l-value for compressed += operand
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%load/vec4 v0x5574a6214160_0;
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%load/vec4 v0x55a2c2780a60_0;
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%pushi/vec4 1, 0, 32;
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%add;
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%store/vec4 v0x5574a6214160_0, 0, 32;
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%store/vec4 v0x55a2c2780a60_0, 0, 32;
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%jmp T_0.12;
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T_0.13 ;
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%pushi/vec4 1, 0, 1;
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%assign/vec4 v0x55a2c27805f0_0, 0;
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%jmp T_0.11;
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T_0.8 ;
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%pushi/vec4 0, 0, 32;
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%store/vec4 v0x5574a61bac00_0, 0, 32;
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%store/vec4 v0x55a2c2723c00_0, 0, 32;
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T_0.16 ;
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%load/vec4 v0x5574a61bac00_0;
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%load/vec4 v0x55a2c2723c00_0;
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%cmpi/s 5, 0, 32;
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%flag_or 5, 4;
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%jmp/0xz T_0.17, 5;
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%load/vec4 v0x5574a6213db0_0;
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%load/vec4 v0x5574a61bac00_0;
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%load/vec4 v0x55a2c27806b0_0;
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%load/vec4 v0x55a2c2723c00_0;
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%part/s 1;
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%pad/u 32;
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%cmpi/e 1, 0, 32;
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%jmp/0xz T_0.18, 4;
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%pushi/vec4 15, 0, 4;
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%assign/vec4 v0x5574a6214240_0, 0;
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%assign/vec4 v0x55a2c2780b40_0, 0;
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%jmp T_0.19;
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T_0.18 ;
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%pushi/vec4 0, 0, 4;
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%assign/vec4 v0x5574a6214240_0, 0;
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%assign/vec4 v0x55a2c2780b40_0, 0;
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T_0.19 ;
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; show_stmt_assign_vector: Get l-value for compressed += operand
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%load/vec4 v0x5574a61bac00_0;
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%load/vec4 v0x55a2c2723c00_0;
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%pushi/vec4 1, 0, 32;
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%add;
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%store/vec4 v0x5574a61bac00_0, 0, 32;
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%store/vec4 v0x55a2c2723c00_0, 0, 32;
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%jmp T_0.16;
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T_0.17 ;
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%pushi/vec4 1, 0, 1;
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%assign/vec4 v0x55a2c27805f0_0, 0;
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%jmp T_0.11;
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T_0.9 ;
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%pushi/vec4 0, 0, 32;
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%store/vec4 v0x5574a6214080_0, 0, 32;
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%store/vec4 v0x55a2c2780980_0, 0, 32;
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%pushi/vec4 0, 0, 32;
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%store/vec4 v0x5574a6213b70_0, 0, 32;
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%store/vec4 v0x55a2c2780470_0, 0, 32;
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T_0.20 ;
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%load/vec4 v0x5574a6213b70_0;
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%load/vec4 v0x55a2c2780470_0;
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%cmpi/s 5, 0, 32;
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%flag_or 5, 4;
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%jmp/0xz T_0.21, 5;
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%load/vec4 v0x5574a6213db0_0;
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%load/vec4 v0x5574a6213b70_0;
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%load/vec4 v0x55a2c27806b0_0;
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%load/vec4 v0x55a2c2780470_0;
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%part/s 1;
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%pad/u 32;
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%cmpi/e 1, 0, 32;
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%jmp/0xz T_0.22, 4;
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%load/vec4 v0x5574a6214080_0;
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%load/vec4 v0x55a2c2780980_0;
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%addi 1, 0, 32;
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%store/vec4 v0x5574a6214080_0, 0, 32;
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%store/vec4 v0x55a2c2780980_0, 0, 32;
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T_0.22 ;
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; show_stmt_assign_vector: Get l-value for compressed += operand
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%load/vec4 v0x5574a6213b70_0;
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%load/vec4 v0x55a2c2780470_0;
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%pushi/vec4 1, 0, 32;
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%add;
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%store/vec4 v0x5574a6213b70_0, 0, 32;
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%store/vec4 v0x55a2c2780470_0, 0, 32;
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%jmp T_0.20;
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T_0.21 ;
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%load/vec4 v0x5574a6214080_0;
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%load/vec4 v0x55a2c2780980_0;
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%pushi/vec4 2, 0, 32;
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%mod/s;
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%cmpi/e 0, 0, 32;
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%jmp/0xz T_0.24, 4;
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%pushi/vec4 15, 0, 4;
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%assign/vec4 v0x5574a6214240_0, 0;
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%assign/vec4 v0x55a2c2780b40_0, 0;
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%jmp T_0.25;
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T_0.24 ;
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%pushi/vec4 0, 0, 4;
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%assign/vec4 v0x5574a6214240_0, 0;
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%assign/vec4 v0x55a2c2780b40_0, 0;
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T_0.25 ;
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%pushi/vec4 1, 0, 1;
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%assign/vec4 v0x55a2c27805f0_0, 0;
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%jmp T_0.11;
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T_0.10 ;
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%pushi/vec4 0, 0, 32;
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%store/vec4 v0x5574a6214080_0, 0, 32;
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||||
%store/vec4 v0x55a2c2780980_0, 0, 32;
|
||||
%pushi/vec4 0, 0, 32;
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||||
%store/vec4 v0x5574a6213ee0_0, 0, 32;
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||||
%store/vec4 v0x55a2c27807e0_0, 0, 32;
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T_0.26 ;
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%load/vec4 v0x5574a6213ee0_0;
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||||
%load/vec4 v0x55a2c27807e0_0;
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||||
%cmpi/s 5, 0, 32;
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||||
%flag_or 5, 4;
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||||
%jmp/0xz T_0.27, 5;
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||||
%load/vec4 v0x5574a6213db0_0;
|
||||
%load/vec4 v0x5574a6213ee0_0;
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||||
%load/vec4 v0x55a2c27806b0_0;
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||||
%load/vec4 v0x55a2c27807e0_0;
|
||||
%part/s 1;
|
||||
%pad/u 32;
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||||
%cmpi/e 1, 0, 32;
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||||
%jmp/0xz T_0.28, 4;
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||||
; show_stmt_assign_vector: Get l-value for compressed += operand
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||||
%load/vec4 v0x5574a6214080_0;
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||||
%pushi/vec4 1, 0, 32;
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||||
%add;
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||||
%store/vec4 v0x5574a6214080_0, 0, 32;
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||||
%load/vec4 v0x55a2c2780980_0;
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||||
%addi 1, 0, 32;
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||||
%store/vec4 v0x55a2c2780980_0, 0, 32;
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||||
T_0.28 ;
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; show_stmt_assign_vector: Get l-value for compressed += operand
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||||
%load/vec4 v0x5574a6213ee0_0;
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%load/vec4 v0x55a2c27807e0_0;
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||||
%pushi/vec4 1, 0, 32;
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||||
%add;
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||||
%store/vec4 v0x5574a6213ee0_0, 0, 32;
|
||||
%store/vec4 v0x55a2c27807e0_0, 0, 32;
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||||
%jmp T_0.26;
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||||
T_0.27 ;
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||||
%load/vec4 v0x5574a6214080_0;
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||||
%load/vec4 v0x55a2c2780980_0;
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||||
%pushi/vec4 2, 0, 32;
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||||
%mod/s;
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||||
%cmpi/e 0, 0, 32;
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||||
%jmp/0xz T_0.30, 4;
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||||
%pushi/vec4 0, 0, 4;
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||||
%assign/vec4 v0x5574a6214240_0, 0;
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||||
%assign/vec4 v0x55a2c2780b40_0, 0;
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||||
%jmp T_0.31;
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||||
T_0.30 ;
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||||
%pushi/vec4 15, 0, 4;
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||||
%assign/vec4 v0x5574a6214240_0, 0;
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||||
%assign/vec4 v0x55a2c2780b40_0, 0;
|
||||
T_0.31 ;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v0x55a2c27805f0_0, 0;
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||||
%jmp T_0.11;
|
||||
T_0.11 ;
|
||||
%pop/vec4 1;
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||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v0x5574a6213cf0_0, 0;
|
||||
%jmp T_0.1;
|
||||
T_0.0 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v0x55a2c27805f0_0, 0;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%assign/vec4 v0x55a2c2780b40_0, 0;
|
||||
T_0.1 ;
|
||||
%jmp T_0;
|
||||
.thread T_0;
|
||||
.scope S_0x5574a61fa040;
|
||||
.scope S_0x55a2c2765ba0;
|
||||
T_1 ;
|
||||
%load/vec4 v0x5574a6214650_0;
|
||||
%load/vec4 v0x55a2c2780f50_0;
|
||||
%inv;
|
||||
%store/vec4 v0x5574a6214650_0, 0, 1;
|
||||
%store/vec4 v0x55a2c2780f50_0, 0, 1;
|
||||
%delay 5, 0;
|
||||
%jmp T_1;
|
||||
.thread T_1;
|
||||
.scope S_0x5574a61fa040;
|
||||
.scope S_0x55a2c2765ba0;
|
||||
T_2 ;
|
||||
%vpi_call 2 25 "$dumpfile", "bib3Advanced.vcd" {0 0 0};
|
||||
%vpi_call 2 26 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5574a6214650_0, 0, 1;
|
||||
%store/vec4 v0x55a2c2780f50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5574a62143c0_0, 0, 1;
|
||||
%store/vec4 v0x55a2c2780cc0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 9;
|
||||
%store/vec4 v0x5574a6214550_0, 0, 9;
|
||||
%vpi_call 2 28 "$readmemb", "memory.mem", v0x5574a62147c0 {0 0 0};
|
||||
%store/vec4 v0x55a2c2780e50_0, 0, 9;
|
||||
%vpi_call 2 28 "$readmemb", "memory.mem", v0x55a2c27810c0 {0 0 0};
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5574a62143c0_0, 0, 1;
|
||||
%store/vec4 v0x55a2c2780cc0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%store/vec4 v0x5574a6214720_0, 0, 32;
|
||||
%store/vec4 v0x55a2c2781020_0, 0, 32;
|
||||
T_2.0 ;
|
||||
%load/vec4 v0x5574a6214720_0;
|
||||
%load/vec4 v0x55a2c2781020_0;
|
||||
%cmpi/s 16, 0, 32;
|
||||
%flag_or 5, 4;
|
||||
%jmp/0xz T_2.1, 5;
|
||||
%ix/getv/s 4, v0x5574a6214720_0;
|
||||
%load/vec4a v0x5574a62147c0, 4;
|
||||
%store/vec4 v0x5574a6214550_0, 0, 9;
|
||||
%ix/getv/s 4, v0x55a2c2781020_0;
|
||||
%load/vec4a v0x55a2c27810c0, 4;
|
||||
%store/vec4 v0x55a2c2780e50_0, 0, 9;
|
||||
%delay 10, 0;
|
||||
; show_stmt_assign_vector: Get l-value for compressed += operand
|
||||
%load/vec4 v0x5574a6214720_0;
|
||||
%load/vec4 v0x55a2c2781020_0;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%add;
|
||||
%store/vec4 v0x5574a6214720_0, 0, 32;
|
||||
%store/vec4 v0x55a2c2781020_0, 0, 32;
|
||||
%jmp T_2.0;
|
||||
T_2.1 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5574a62143c0_0, 0, 1;
|
||||
%store/vec4 v0x55a2c2780cc0_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 36 "$finish" {0 0 0};
|
||||
%end;
|
||||
|
||||
@ -8,25 +8,45 @@ module bib3Advanced (
|
||||
integer i, a, b, c, count;
|
||||
always@(posedge clk) begin
|
||||
if(basla) begin
|
||||
bitti <= 1'b0;
|
||||
case (buyruk[8:6])
|
||||
default: sonuc <= 4'b0000;
|
||||
3'b000: sonuc <= buyruk[5:3] + buyruk[2:0];
|
||||
3'b001: sonuc <= buyruk[5:3] - buyruk[2:0];
|
||||
3'b010: sonuc <= buyruk[5:3] & buyruk[2:0];
|
||||
3'b011: sonuc <= buyruk[5:3] | buyruk[2:0];
|
||||
default: begin
|
||||
sonuc <= 4'b0000;
|
||||
end
|
||||
3'b000: begin
|
||||
sonuc <= buyruk[5:3] + buyruk[2:0];
|
||||
bitti <= 1'b1;
|
||||
end
|
||||
3'b001: begin
|
||||
sonuc <= buyruk[5:3] - buyruk[2:0];
|
||||
bitti <= 1'b1;
|
||||
end
|
||||
3'b010: begin
|
||||
sonuc <= buyruk[5:3] & buyruk[2:0];
|
||||
bitti <= 1'b1;
|
||||
end
|
||||
3'b011: begin
|
||||
sonuc <= buyruk[5:3] | buyruk[2:0];
|
||||
bitti <= 1'b1;
|
||||
end
|
||||
3'b100: begin
|
||||
for (i = 0; i <= 4; i++)
|
||||
for (i = 0; i <= 4; i++) begin
|
||||
if (buyruk[i] == buyruk[i+1])
|
||||
sonuc <= 4'b1111;
|
||||
else
|
||||
sonuc <= 4'b0000;
|
||||
end
|
||||
3'b101: for (a = 0; a <= 5; a++) begin
|
||||
bitti <= 1'b1;
|
||||
end
|
||||
3'b101: begin
|
||||
for (a = 0; a <= 5; a++) begin
|
||||
if (buyruk[a] == 1)
|
||||
sonuc <= 4'b1111;
|
||||
else
|
||||
sonuc <= 4'b0000;
|
||||
end
|
||||
bitti <= 1'b1;
|
||||
end
|
||||
3'b110: begin
|
||||
count = 0;
|
||||
for (b = 0; b <= 5; b++) begin
|
||||
@ -37,19 +57,24 @@ module bib3Advanced (
|
||||
sonuc <= 4'b1111;
|
||||
else
|
||||
sonuc <= 4'b0000;
|
||||
bitti <= 1'b1;
|
||||
end
|
||||
3'b111: begin
|
||||
count = 0;
|
||||
for (c = 0; c <= 5; c++)
|
||||
if (buyruk[c] == 1)
|
||||
count++;
|
||||
count = count + 1;
|
||||
if (count % 2 == 0)
|
||||
sonuc <= 4'b0000;
|
||||
else
|
||||
sonuc <= 4'b1111;
|
||||
bitti <= 1'b1;
|
||||
end
|
||||
endcase
|
||||
bitti <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
bitti <= 1'b0;
|
||||
sonuc <= 4'b0000;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
$date
|
||||
Thu Jan 30 07:20:34 2025
|
||||
Thu Jan 30 07:38:04 2025
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
@ -45,6 +45,9 @@ x"
|
||||
bx !
|
||||
$end
|
||||
#5
|
||||
b0 !
|
||||
b0 (
|
||||
0"
|
||||
1%
|
||||
#10
|
||||
0%
|
||||
@ -65,6 +68,7 @@ b1 &
|
||||
#25
|
||||
b11 !
|
||||
b11 (
|
||||
1"
|
||||
1%
|
||||
#30
|
||||
0%
|
||||
@ -74,6 +78,7 @@ b10 &
|
||||
#35
|
||||
b100 !
|
||||
b100 (
|
||||
1"
|
||||
1%
|
||||
#40
|
||||
0%
|
||||
@ -83,6 +88,7 @@ b11 &
|
||||
#45
|
||||
b111 !
|
||||
b111 (
|
||||
1"
|
||||
1%
|
||||
#50
|
||||
0%
|
||||
@ -92,6 +98,7 @@ b100 &
|
||||
#55
|
||||
b1111 !
|
||||
b1111 (
|
||||
1"
|
||||
b101 -
|
||||
1%
|
||||
#60
|
||||
@ -102,6 +109,7 @@ b101 &
|
||||
#65
|
||||
b0 !
|
||||
b0 (
|
||||
1"
|
||||
b101 -
|
||||
1%
|
||||
#70
|
||||
@ -112,6 +120,7 @@ b110 &
|
||||
#75
|
||||
b1111 !
|
||||
b1111 (
|
||||
1"
|
||||
b110 )
|
||||
1%
|
||||
#80
|
||||
@ -120,6 +129,7 @@ b110100001 $
|
||||
b110100001 '
|
||||
b111 &
|
||||
#85
|
||||
1"
|
||||
b110 *
|
||||
b10 ,
|
||||
1%
|
||||
@ -131,6 +141,7 @@ b1000 &
|
||||
#95
|
||||
b0 !
|
||||
b0 (
|
||||
1"
|
||||
b110 +
|
||||
b10 ,
|
||||
1%
|
||||
@ -142,6 +153,7 @@ b1001 &
|
||||
#105
|
||||
b10 !
|
||||
b10 (
|
||||
1"
|
||||
1%
|
||||
#110
|
||||
0%
|
||||
@ -151,6 +163,7 @@ b1010 &
|
||||
#115
|
||||
b11 !
|
||||
b11 (
|
||||
1"
|
||||
1%
|
||||
#120
|
||||
0%
|
||||
@ -160,6 +173,7 @@ b1011 &
|
||||
#125
|
||||
b100 !
|
||||
b100 (
|
||||
1"
|
||||
1%
|
||||
#130
|
||||
0%
|
||||
@ -169,6 +183,7 @@ b1100 &
|
||||
#135
|
||||
b111 !
|
||||
b111 (
|
||||
1"
|
||||
1%
|
||||
#140
|
||||
0%
|
||||
@ -178,6 +193,7 @@ b1101 &
|
||||
#145
|
||||
b1111 !
|
||||
b1111 (
|
||||
1"
|
||||
b101 -
|
||||
1%
|
||||
#150
|
||||
@ -188,6 +204,7 @@ b1110 &
|
||||
#155
|
||||
b0 !
|
||||
b0 (
|
||||
1"
|
||||
b101 -
|
||||
1%
|
||||
#160
|
||||
@ -198,6 +215,7 @@ b1111 &
|
||||
#165
|
||||
b1111 !
|
||||
b1111 (
|
||||
1"
|
||||
b110 )
|
||||
1%
|
||||
#170
|
||||
@ -208,6 +226,7 @@ b10000 &
|
||||
#175
|
||||
b0 !
|
||||
b0 (
|
||||
0"
|
||||
1%
|
||||
#180
|
||||
0%
|
||||
|
||||
@ -3,7 +3,7 @@ module bib3AdvancedTB();
|
||||
reg clk;
|
||||
reg basla;
|
||||
reg [8:0] buyruk;
|
||||
reg [8:0] memory [15:0];
|
||||
reg [8:0] memory [0:15];
|
||||
wire [3:0] sonuc;
|
||||
wire bitti;
|
||||
|
||||
|
||||
0
iverilog/tobb/lab7/bib3_gelismis.v
Normal file
0
iverilog/tobb/lab7/bib3_gelismis.v
Normal file
12
iverilog/tobb/lab7/paramBib3Advanced.v
Normal file
12
iverilog/tobb/lab7/paramBib3Advanced.v
Normal file
@ -0,0 +1,12 @@
|
||||
module paramBib3Advanced #(parameter N = 3) (
|
||||
input clk,
|
||||
input basla,
|
||||
input [(N*2)+2:0] buyruk,
|
||||
output reg [N:0] sonuc,
|
||||
output reg bitti
|
||||
);
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < N)
|
||||
endgenerate
|
||||
Loading…
x
Reference in New Issue
Block a user