239 lines
1.8 KiB
Plaintext
239 lines
1.8 KiB
Plaintext
$date
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Thu Jan 30 07:38:04 2025
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module bib3AdvancedTB $end
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$var wire 4 ! sonuc [3:0] $end
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$var wire 1 " bitti $end
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$var reg 1 # basla $end
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$var reg 9 $ buyruk [8:0] $end
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$var reg 1 % clk $end
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$var integer 32 & i [31:0] $end
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$scope module uut $end
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$var wire 1 # basla $end
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$var wire 9 ' buyruk [8:0] $end
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$var wire 1 % clk $end
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$var reg 1 " bitti $end
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$var reg 4 ( sonuc [3:0] $end
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$var integer 32 ) a [31:0] $end
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$var integer 32 * b [31:0] $end
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$var integer 32 + c [31:0] $end
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$var integer 32 , count [31:0] $end
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$var integer 32 - i [31:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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bx -
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bx ,
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bx +
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bx *
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bx )
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bx (
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b0 '
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bx &
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0%
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b0 $
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0#
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x"
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bx !
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$end
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#5
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b0 !
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b0 (
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0"
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1%
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#10
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0%
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b1001 $
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b1001 '
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#15
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1"
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b10 !
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b10 (
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#20
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0%
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b1100001 $
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b1100001 '
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b1 &
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#25
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b11 !
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b11 (
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1"
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1%
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#30
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0%
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b10100101 $
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b10100101 '
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b10 &
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#35
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b100 !
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b100 (
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1"
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1%
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#40
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0%
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b11100011 $
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b11100011 '
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b11 &
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#45
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b111 !
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b111 (
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1"
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#50
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0%
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b100111111 $
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b100111111 '
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b100 &
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#55
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b1111 !
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b1111 (
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1"
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b101 -
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#60
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0%
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b100100001 $
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b100100001 '
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b101 &
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#65
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b0 !
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b0 (
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1"
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b101 -
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#70
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b101100001 $
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b101100001 '
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b110 &
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#75
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b1111 !
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b1111 (
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1"
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b110 )
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#80
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0%
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b110100001 $
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b110100001 '
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b111 &
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#85
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1"
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b110 *
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b10 ,
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1%
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#90
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0%
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b111100001 $
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b111100001 '
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b1000 &
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#95
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b0 !
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b0 (
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1"
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b110 +
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b10 ,
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1%
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#100
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0%
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b1001 $
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b1001 '
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b1001 &
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#105
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b10 !
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b10 (
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1"
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1%
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#110
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0%
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b1100001 $
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b1100001 '
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b1010 &
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#115
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b11 !
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b11 (
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1"
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1%
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#120
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0%
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b10100101 $
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b1011 &
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#125
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b100 !
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b100 (
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1"
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1%
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#130
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0%
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b11100011 $
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b1100 &
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#135
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b111 !
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b111 (
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1"
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1%
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#140
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0%
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b100111111 $
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b100111111 '
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b1101 &
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#145
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b1111 !
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b1111 (
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1"
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b101 -
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#150
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0%
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b100100001 $
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b100100001 '
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b1110 &
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#155
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b0 !
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b0 (
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1"
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b101 -
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#160
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0%
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b101100001 $
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b1111 &
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#165
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b1111 !
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b1111 (
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1"
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b110 )
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1%
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#170
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0%
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bx $
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bx '
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b10000 &
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#175
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b0 !
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b0 (
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0"
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1%
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#180
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0%
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0#
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b10001 &
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#185
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1%
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#190
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0%
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