verible

2024-12-02 22:30:36 +03:00 · 2024-12-02 22:30:36 +03:00 · 4415081e03
commit 4415081e03
25 changed files with 7 additions and 0 deletions
--- a/bin/.Formatter.swp
+++ b/bin/.Formatter.swp
--- a/bin/.Here’s.swp
+++ b/bin/.Here’s.swp
--- a/bin/.Verible.swp
+++ b/bin/.Verible.swp
--- a/bin/.Verilog.swp
+++ b/bin/.Verilog.swp
--- a/bin/.a.swp
+++ b/bin/.a.swp
--- a/bin/.align.swp
+++ b/bin/.align.swp
--- a/bin/.configuration.swp
+++ b/bin/.configuration.swp
--- a/bin/.file.swp
+++ b/bin/.file.swp
--- a/bin/.for.swp
+++ b/bin/.for.swp
--- a/bin/.from.swp
+++ b/bin/.from.swp
--- a/bin/.project,.swp
+++ b/bin/.project,.swp
--- a/bin/.tailored.swp
+++ b/bin/.tailored.swp
--- a/bin/.the.swp
+++ b/bin/.the.swp
--- a/bin/.to.swp
+++ b/bin/.to.swp
--- a/bin/.verible-verilog-format.properties
+++ b/bin/.verible-verilog-format.properties
@ -0,0 +1,7 @@
 --indentation_spaces=3
 --column_limit=100
 --assignment_statement_alignment=align
 --case_items_alignment=align
 --port_declarations_alignment=align
 --struct_union_members_alignment=align
 --wrap_end_else_clauses=false
--- a/bin/.with.swp
+++ b/bin/.with.swp
--- a/bin/verible-verilog-diff
+++ b/bin/verible-verilog-diff
--- a/bin/verible-verilog-format
+++ b/bin/verible-verilog-format
--- a/bin/verible-verilog-kythe-extractor
+++ b/bin/verible-verilog-kythe-extractor
--- a/bin/verible-verilog-lint
+++ b/bin/verible-verilog-lint
--- a/bin/verible-verilog-ls
+++ b/bin/verible-verilog-ls
--- a/bin/verible-verilog-obfuscate
+++ b/bin/verible-verilog-obfuscate
--- a/bin/verible-verilog-preprocessor
+++ b/bin/verible-verilog-preprocessor
--- a/bin/verible-verilog-project
+++ b/bin/verible-verilog-project
--- a/bin/verible-verilog-syntax
+++ b/bin/verible-verilog-syntax