verible/bin/.verible-verilog-format.properties
2024-12-02 22:30:36 +03:00

8 lines
215 B
INI

--indentation_spaces=3
--column_limit=100
--assignment_statement_alignment=align
--case_items_alignment=align
--port_declarations_alignment=align
--struct_union_members_alignment=align
--wrap_end_else_clauses=false