commit 4415081e03ef01035c42b292d4a21f926b25a6d0
Author: kaltinsoy <koray@anilkoray.tr>
Date:   Mon Dec 2 22:30:36 2024 +0300

    verible

diff --git a/bin/.Formatter.swp b/bin/.Formatter.swp
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diff --git a/bin/.Verilog.swp b/bin/.Verilog.swp
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diff --git a/bin/.verible-verilog-format.properties b/bin/.verible-verilog-format.properties
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+--indentation_spaces=3
+--column_limit=100
+--assignment_statement_alignment=align
+--case_items_alignment=align
+--port_declarations_alignment=align
+--struct_union_members_alignment=align
+--wrap_end_else_clauses=false
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