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4-bit-ALU/verilog/ALUTangTest
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k0rrluna 6080927957 small changes
2025-01-23 07:16:59 +03:00
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addition.v
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ALU
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ALU.v
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ALU.vcd
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ALUtb.v
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arithmeticUnit.v
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BinaryToBCD.v
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compile.sh
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dabble.v
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fulladder.v
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fullsubtraction.v
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halfadder.v
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halfsubtraction.v
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logicUnit.v
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mult
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mult.vcd
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multiplier.v
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multTB.v
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opCode.v
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selector.v
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subtraction.v
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top
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top.v
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top.vcd
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topTB.v
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