21 lines
572 B
Verilog
21 lines
572 B
Verilog
module selector (
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input [3:0] A,
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input [3:0] B,
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input [2:0] opCodeA,
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input [1:0] select,
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input [11:0] ALUY,
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output reg [11:0] Y
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);
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always @(*) begin
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case (select)
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2'b00: Y = {8'b00000000, A}; // Zero-extend A to 8 bits
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2'b01: Y = {8'b00000000, B}; // Zero-extend B to 8 bits
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2'b10: Y = {9'b000000000, opCodeA}; // Zero-extend opCodeA to 8 bits
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2'b11: Y = ALUY; // Directly assign ALUY
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default: Y = ALUY; // Default case for safety
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endcase
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end
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endmodule
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