gowin impl removed because f#
This commit is contained in:
parent
91280fbab2
commit
d4d35b4983
@ -1,130 +0,0 @@
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GowinSynthesis start
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Running parser ...
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\addition.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\ALU.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\dabble.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\fulladder.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\halfadder.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\halfsubtraction.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\logicUnit.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\multiplier.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\opCode.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\selector.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\subtraction.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\top.v'
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Compiling module 'top'("C:\Users\koray\Documents\gowin\ALU\src\top.v":1)
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Compiling module 'ALU'("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":1)
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Compiling module 'opCode'("C:\Users\koray\Documents\gowin\ALU\src\opCode.v":1)
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Compiling module 'arithmeticUnit'("C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v":1)
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Compiling module 'addition'("C:\Users\koray\Documents\gowin\ALU\src\addition.v":1)
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Compiling module 'fulladder'("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":1)
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Compiling module 'halfadder'("C:\Users\koray\Documents\gowin\ALU\src\halfadder.v":1)
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Compiling module 'subtraction'("C:\Users\koray\Documents\gowin\ALU\src\subtraction.v":1)
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Compiling module 'fullsubtraction'("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":1)
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Compiling module 'halfsubtraction'("C:\Users\koray\Documents\gowin\ALU\src\halfsubtraction.v":1)
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Compiling module 'logicUnit'("C:\Users\koray\Documents\gowin\ALU\src\logicUnit.v":1)
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Compiling module 'multiplier'("C:\Users\koray\Documents\gowin\ALU\src\multiplier.v":1)
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Compiling module 'BinaryToBCD'("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":1)
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Compiling module 'dabble'("C:\Users\koray\Documents\gowin\ALU\src\dabble.v":1)
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Compiling module 'selector'("C:\Users\koray\Documents\gowin\ALU\src\selector.v":1)
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NOTE (EX0101) : Current top module is "top"
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[5%] Running netlist conversion ...
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Running device independent optimization ...
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[10%] Optimizing Phase 0 completed
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[15%] Optimizing Phase 1 completed
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[25%] Optimizing Phase 2 completed
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Running inference ...
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[30%] Inferring Phase 0 completed
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[40%] Inferring Phase 1 completed
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[50%] Inferring Phase 2 completed
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[55%] Inferring Phase 3 completed
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Running technical mapping ...
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[60%] Tech-Mapping Phase 0 completed
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[65%] Tech-Mapping Phase 1 completed
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[75%] Tech-Mapping Phase 2 completed
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[80%] Tech-Mapping Phase 3 completed
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[90%] Tech-Mapping Phase 4 completed
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WARN (NL0002) : The module "ALU" instantiated to "a1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\top.v":13)
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WARN (NL0002) : The module "arithmeticUnit" instantiated to "aU" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":20)
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WARN (NL0002) : The module "addition" instantiated to "a1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v":13)
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WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":11)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":12)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":13)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":14)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "subtraction" instantiated to "s1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v":14)
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WARN (NL0002) : The module "fullsubtraction" instantiated to "f0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\subtraction.v":11)
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WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":8)
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WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":9)
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WARN (NL0002) : The module "fullsubtraction" instantiated to "f1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\subtraction.v":12)
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WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":8)
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WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":9)
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WARN (NL0002) : The module "fullsubtraction" instantiated to "f2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\subtraction.v":13)
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WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":8)
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WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":9)
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WARN (NL0002) : The module "fullsubtraction" instantiated to "f3" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\subtraction.v":14)
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WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":8)
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WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":9)
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WARN (NL0002) : The module "BinaryToBCD" instantiated to "btod1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":76)
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WARN (NL0002) : The module "dabble" instantiated to "d1t" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":21)
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WARN (NL0002) : The module "dabble" instantiated to "d2u" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":30)
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WARN (NL0002) : The module "dabble" instantiated to "d3v" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":39)
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WARN (NL0002) : The module "dabble" instantiated to "d4w" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":48)
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WARN (NL0002) : The module "dabble" instantiated to "d5x" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":57)
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WARN (NL0002) : The module "dabble" instantiated to "d6y" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":66)
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WARN (NL0002) : The module "dabble" instantiated to "d7z" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":75)
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WARN (NL0002) : The module "logicUnit" instantiated to "lU" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":21)
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WARN (NL0002) : The module "multiplier" instantiated to "mU" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":22)
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WARN (NL0002) : The module "addition" instantiated to "add0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\multiplier.v":33)
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WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":11)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":12)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":13)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":14)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "addition" instantiated to "add1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\multiplier.v":49)
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WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":11)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":12)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":13)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":14)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "addition" instantiated to "add2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\multiplier.v":65)
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WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":11)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":12)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":13)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":14)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "opCode" instantiated to "opCd" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":18)
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[95%] Generate netlist file "C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg" completed
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[100%] Generate report file "C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU_syn.rpt.html" completed
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GowinSynthesis finish
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@ -1,35 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE gowin-synthesis-project>
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<Project>
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<Version>beta</Version>
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<Device id="GW2A-18" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
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<FileList>
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<File path="C:\Users\koray\Documents\gowin\ALU\src\addition.v" type="verilog"/>
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<File path="C:\Users\koray\Documents\gowin\ALU\src\ALU.v" type="verilog"/>
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<File path="C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v" type="verilog"/>
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<File path="C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v" type="verilog"/>
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<File path="C:\Users\koray\Documents\gowin\ALU\src\dabble.v" type="verilog"/>
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<File path="C:\Users\koray\Documents\gowin\ALU\src\fulladder.v" type="verilog"/>
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<File path="C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v" type="verilog"/>
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<File path="C:\Users\koray\Documents\gowin\ALU\src\halfadder.v" type="verilog"/>
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<File path="C:\Users\koray\Documents\gowin\ALU\src\halfsubtraction.v" type="verilog"/>
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<File path="C:\Users\koray\Documents\gowin\ALU\src\logicUnit.v" type="verilog"/>
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<File path="C:\Users\koray\Documents\gowin\ALU\src\multiplier.v" type="verilog"/>
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<File path="C:\Users\koray\Documents\gowin\ALU\src\opCode.v" type="verilog"/>
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<File path="C:\Users\koray\Documents\gowin\ALU\src\selector.v" type="verilog"/>
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<File path="C:\Users\koray\Documents\gowin\ALU\src\subtraction.v" type="verilog"/>
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<File path="C:\Users\koray\Documents\gowin\ALU\src\top.v" type="verilog"/>
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</FileList>
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<OptionList>
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<Option type="disable_insert_pad" value="0"/>
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<Option type="global_freq" value="100.000"/>
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<Option type="looplimit" value="2000"/>
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<Option type="output_file" value="C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg"/>
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<Option type="print_all_synthesis_warning" value="0"/>
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<Option type="ram_rw_check" value="0"/>
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<Option type="vcc" value="1.0"/>
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<Option type="vccx" value="3.3"/>
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<Option type="verilog_language" value="verilog-2001"/>
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<Option type="vhdl_language" value="vhdl-1993"/>
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</OptionList>
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</Project>
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File diff suppressed because it is too large
Load Diff
@ -1,185 +0,0 @@
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<html>
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<head>
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<title>synthesis Report</title>
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<style type="text/css">
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body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
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div#main_wrapper{ width: 100%; }
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div#content { margin-left: 350px; margin-right: 30px; }
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div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
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div#catalog ul { list-style-type: none; }
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div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
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div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
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div#catalog a:visited { color: #0084ff; }
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div#catalog a:hover { color: #fff; background: #0084ff; }
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hr { margin-top: 30px; margin-bottom: 30px; }
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h1, h3 { text-align: center; }
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h1 {margin-top: 50px; }
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table, th, td { border: 1px solid #aaa; }
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table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
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th, td { padding: 5px 5px 5px 5px; }
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th { color: #fff; font-weight: bold; background-color: #0084ff; }
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table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
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table.detail_table td.label { min-width: 100px; width: 8%;}
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</style>
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</head>
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<body>
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<div id="main_wrapper">
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<div id="catalog_wrapper">
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<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
|
||||
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
|
||||
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
|
||||
<ul>
|
||||
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
|
||||
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="about">Synthesis Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>GowinSynthesis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\Users\koray\Documents\gowin\ALU\src\addition.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\ALU.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\dabble.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\fulladder.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\halfadder.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\halfsubtraction.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\logicUnit.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\multiplier.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\opCode.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\selector.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\subtraction.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\top.v<br>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">GowinSynthesis Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.10.03 (64-bit)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Thu Jan 23 05:43:09 2025
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="summary">Synthesis Details</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Top Level Module</td>
|
||||
<td>top</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Synthesis Process</td>
|
||||
<td>Running parser:<br/> CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 402.914MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 402.914MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 402.914MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 402.914MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 402.914MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 402.914MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 402.914MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 402.914MB<br/>Generate output files:<br/> CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 402.914MB<br/></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 402.914MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="resource">Resource</a></h1>
|
||||
<h2><a name="usage">Resource Usage Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Port </b></td>
|
||||
<td>28</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Buf </b></td>
|
||||
<td>28</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    IBUF</td>
|
||||
<td>14</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    OBUF</td>
|
||||
<td>14</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>LUT </b></td>
|
||||
<td>141</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT2</td>
|
||||
<td>16</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT3</td>
|
||||
<td>36</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT4</td>
|
||||
<td>89</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
<td><b>Utilization</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>141(141 LUT, 0 ALU) / 20736</td>
|
||||
<td><1%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as Latch</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as FF</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BSRAM</td>
|
||||
<td>0 / 46</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
@ -1,56 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Hierarchy Module Resource</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
h1 {text-align: center; }
|
||||
h1 {margin-top: 36px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { align = "center"; padding: 5px 2px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="content">
|
||||
<h1>Hierarchy Module Resource</h1>
|
||||
<table>
|
||||
<tr>
|
||||
<th class="label">MODULE NAME</th>
|
||||
<th class="label">REG NUMBER</th>
|
||||
<th class="label">ALU NUMBER</th>
|
||||
<th class="label">LUT NUMBER</th>
|
||||
<th class="label">DSP NUMBER</th>
|
||||
<th class="label">BSRAM NUMBER</th>
|
||||
<th class="label">SSRAM NUMBER</th>
|
||||
<th class="label">ROM16 NUMBER</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">top (C:/Users/koray/Documents/gowin/ALU/src/top.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">13</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
<td class="label">    |--s1
|
||||
(C:/Users/koray/Documents/gowin/ALU/src/top.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">128</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
@ -1,4 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="top" Lut="13" T_Lut="141(13)">
|
||||
<SubModule name="s1" Lut="128" T_Lut="128(128)"/>
|
||||
</Module>
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -1,29 +0,0 @@
|
||||
Reading netlist file: "C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg"
|
||||
Parsing netlist file "C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg" completed
|
||||
Processing netlist completed
|
||||
Reading constraint file: "C:\Users\koray\Documents\gowin\ALU\src\top.cst"
|
||||
Physical Constraint parsed completed
|
||||
Running placement......
|
||||
[10%] Placement Phase 0 completed
|
||||
[20%] Placement Phase 1 completed
|
||||
[30%] Placement Phase 2 completed
|
||||
[50%] Placement Phase 3 completed
|
||||
Running routing......
|
||||
[60%] Routing Phase 0 completed
|
||||
[70%] Routing Phase 1 completed
|
||||
[80%] Routing Phase 2 completed
|
||||
[90%] Routing Phase 3 completed
|
||||
Running timing analysis......
|
||||
[95%] Timing analysis completed
|
||||
Placement and routing completed
|
||||
Bitstream generation in progress......
|
||||
Bitstream generation completed
|
||||
Running power analysis......
|
||||
[100%] Power analysis completed
|
||||
Generate file "C:\Users\koray\Documents\gowin\ALU\impl\pnr\ALU.power.html" completed
|
||||
Generate file "C:\Users\koray\Documents\gowin\ALU\impl\pnr\ALU.pin.html" completed
|
||||
Generate file "C:\Users\koray\Documents\gowin\ALU\impl\pnr\ALU.rpt.html" completed
|
||||
Generate file "C:\Users\koray\Documents\gowin\ALU\impl\pnr\ALU.rpt.txt" completed
|
||||
Generate file "C:\Users\koray\Documents\gowin\ALU\impl\pnr\ALU.tr.html" completed
|
||||
Thu Jan 23 05:43:13 2025
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,265 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Power Analysis Report</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#main_wrapper { width: 100%; }
|
||||
div#content { margin-left: 350px; margin-right: 30px; }
|
||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
||||
div#catalog ul { list-style-type: none; }
|
||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td {white-space:pre; border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
|
||||
<ul>
|
||||
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
|
||||
<ul>
|
||||
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
|
||||
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
|
||||
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
|
||||
<ul>
|
||||
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
|
||||
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
|
||||
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="Message">Power Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>Power Analysis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Physical Constraints File</td>
|
||||
<td>C:\Users\koray\Documents\gowin\ALU\src\top.cst</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Timing Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.10.03 (64-bit)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Thu Jan 23 05:43:13 2025
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Configure_Info">Configure Information:</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Grade</td>
|
||||
<td>Commercial</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Process</td>
|
||||
<td>Typical</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Ambient Temperature</td>
|
||||
<td>25.000
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Use Custom Theta JA</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Heat Sink</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Air Flow</td>
|
||||
<td>LFM_0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Use Custom Theta SA</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Board Thermal Model</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Use Custom Theta JB</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Related Vcd File</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Related Saif File</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Filter Glitches</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Default IO Toggle Rate</td>
|
||||
<td>0.125</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Default Remain Toggle Rate</td>
|
||||
<td>0.125</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="Summary">Power Summary</a></h1>
|
||||
<h2><a name="Power_Info">Power Information:</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Total Power (mW)</td>
|
||||
<td>124.522</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Quiescent Power (mW)</td>
|
||||
<td>121.169</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Dynamic Power (mW)</td>
|
||||
<td>3.353</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Thermal_Info">Thermal Information:</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Junction Temperature</td>
|
||||
<td>28.987</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Theta JA</td>
|
||||
<td>32.020</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Max Allowed Ambient Temperature</td>
|
||||
<td>81.013</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Supply_Summary">Supply Information:</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<th class="label">Voltage Source</th>
|
||||
<th class="label">Voltage</th>
|
||||
<th class="label">Dynamic Current(mA)</th>
|
||||
<th class="label">Quiescent Current(mA)</th>
|
||||
<th class="label">Power(mW)</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>VCC</td>
|
||||
<td>1.000</td>
|
||||
<td>0.552</td>
|
||||
<td>69.981</td>
|
||||
<td>70.533</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>VCCX</td>
|
||||
<td>3.300</td>
|
||||
<td>0.552</td>
|
||||
<td>15.000</td>
|
||||
<td>51.322</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>VCCIO18</td>
|
||||
<td>1.800</td>
|
||||
<td>0.544</td>
|
||||
<td>0.938</td>
|
||||
<td>2.668</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="Detail">Power Details</a></h1>
|
||||
<h2><a name="By_Block_Type">Power By Block Type:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Block Type</th>
|
||||
<th class="label">Total Power(mW)</th>
|
||||
<th class="label">Static Power(mW)</th>
|
||||
<th class="label">Average Toggle Rate(millions of transitions/sec)</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>IO</td>
|
||||
<td>8.544
|
||||
<td>5.191
|
||||
<td>6.250
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Hierarchy Entity</th>
|
||||
<th class="label">Total Power(mW)</th>
|
||||
<th class="label">Block Dynamic Power(mW)</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>top</td>
|
||||
<td>0.000</td>
|
||||
<td>0.000(0.000)</td>
|
||||
<tr>
|
||||
<td>top/s1/</td>
|
||||
<td>0.000</td>
|
||||
<td>0.000(0.000)</td>
|
||||
</table>
|
||||
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Clock Domain</th>
|
||||
<th class="label">Clock Frequency(Mhz)</th>
|
||||
<th class="label">Total Dynamic Power(mW)</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>NO CLOCK DOMAIN</td>
|
||||
<td>0.000</td>
|
||||
<td>0.000</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
File diff suppressed because it is too large
Load Diff
351
gowin/ALU/impl/pnr/ALU.rpt.txt
vendored
351
gowin/ALU/impl/pnr/ALU.rpt.txt
vendored
@ -1,351 +0,0 @@
|
||||
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
|
||||
//All rights reserved.
|
||||
|
||||
|
||||
1. PnR Messages
|
||||
|
||||
<Report Title>: PnR Report
|
||||
<Design File>: C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg
|
||||
<Physical Constraints File>: C:\Users\koray\Documents\gowin\ALU\src\top.cst
|
||||
<Timing Constraints File>: ---
|
||||
<Tool Version>: V1.9.10.03 (64-bit)
|
||||
<Part Number>: GW2A-LV18PG256C8/I7
|
||||
<Device>: GW2A-18
|
||||
<Created Time>:Thu Jan 23 05:43:13 2025
|
||||
|
||||
|
||||
2. PnR Details
|
||||
|
||||
Running placement:
|
||||
Placement Phase 0: CPU time = 0h 0m 0.017s, Elapsed time = 0h 0m 0.017s
|
||||
Placement Phase 1: CPU time = 0h 0m 0.344s, Elapsed time = 0h 0m 0.344s
|
||||
Placement Phase 2: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.008s
|
||||
Placement Phase 3: CPU time = 0h 0m 0.847s, Elapsed time = 0h 0m 0.847s
|
||||
Total Placement: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
|
||||
Running routing:
|
||||
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
|
||||
Routing Phase 1: CPU time = 0h 0m 0.149s, Elapsed time = 0h 0m 0.149s
|
||||
Routing Phase 2: CPU time = 0h 0m 0.202s, Elapsed time = 0h 0m 0.202s
|
||||
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
|
||||
Total Routing: CPU time = 0h 0m 0.351s, Elapsed time = 0h 0m 0.351s
|
||||
Generate output files:
|
||||
CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
|
||||
|
||||
Total Time and Memory Usage: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 444MB
|
||||
|
||||
|
||||
3. Resource Usage Summary
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Resources | Usage | Utilization
|
||||
--------------------------------------------------------------------------------
|
||||
Logic | 141/20736 | <1%
|
||||
--LUT,ALU,ROM16 | 141(141 LUT, 0 ALU, 0 ROM16) | -
|
||||
--SSRAM(RAM16) | 0 | -
|
||||
Register | 0/16173 | 0%
|
||||
--Logic Register as Latch | 0/15552 | 0%
|
||||
--Logic Register as FF | 0/15552 | 0%
|
||||
--I/O Register as Latch | 0/621 | 0%
|
||||
--I/O Register as FF | 0/621 | 0%
|
||||
CLS | 77/10368 | <1%
|
||||
I/O Port | 28/207 | 14%
|
||||
I/O Buf | 28 | -
|
||||
--Input Buf | 14 | -
|
||||
--Output Buf | 14 | -
|
||||
--Inout Buf | 0 | -
|
||||
================================================================================
|
||||
|
||||
|
||||
|
||||
4. I/O Bank Usage Summary
|
||||
|
||||
--------------------------------------
|
||||
I/O Bank | Usage | Utilization
|
||||
--------------------------------------
|
||||
bank 0 | 1/29 | 4%
|
||||
bank 1 | 5/20 | 25%
|
||||
bank 2 | 2/20 | 10%
|
||||
bank 3 | 8/32 | 25%
|
||||
bank 4 | 2/36 | 6%
|
||||
bank 5 | 0/36 | 0%
|
||||
bank 6 | 2/18 | 12%
|
||||
bank 7 | 8/16 | 50%
|
||||
======================================
|
||||
|
||||
|
||||
5. Clock Resource Usage Summary
|
||||
|
||||
------------------------------------------
|
||||
Clock Resource| Usage | Utilization
|
||||
------------------------------------------
|
||||
PRIMARY | 0/8 | 0%
|
||||
LW | 0/8 | 0%
|
||||
GCLK_PIN | 1/8 | 13%
|
||||
==========================================
|
||||
|
||||
|
||||
6. Global Clock Signals
|
||||
|
||||
-------------------------------------------
|
||||
Signal | Global Clock | Location
|
||||
-------------------------------------------
|
||||
===========================================
|
||||
|
||||
|
||||
7. Pinout by Port Name
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio
|
||||
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
A[0] | - | A11/7 | Y | in | IOL15[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
A[1] | - | N6/3 | Y | in | IOR51[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
A[2] | - | E15/1 | Y | in | IOT44[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A[3] | - | L9/3 | Y | in | IOR40[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
B[0] | - | B11/7 | Y | in | IOL13[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
B[1] | - | D11/7 | Y | in | IOL22[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
B[2] | - | N7/3 | Y | in | IOR47[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
B[3] | - | N8/3 | Y | in | IOR40[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
opCodeA[0] | - | T5/4 | Y | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
opCodeA[1] | - | T4/4 | Y | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
opCodeA[2] | - | E8/6 | Y | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
select[0] | - | A15/7 | Y | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
select[1] | - | A14/7 | Y | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
Cin | - | E9/6 | Y | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
leds[0] | - | L16/1 | Y | out | IOT34[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
leds[1] | - | L14/1 | Y | out | IOT34[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
Y[0] | - | P6/3 | Y | out | IOR53[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
Y[1] | - | T7/3 | Y | out | IOR29[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
Y[2] | - | P8/3 | Y | out | IOR42[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
Y[3] | - | P9/3 | Y | out | IOR38[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
Y[4] | - | T11/2 | Y | out | IOR24[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
Y[5] | - | T12/2 | Y | out | IOR17[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
Y[6] | - | M14/1 | Y | out | IOT40[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
Y[7] | - | J14/0 | Y | out | IOT22[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
Y[8] | - | D14/1 | Y | out | IOT44[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
Y[9] | - | B14/7 | Y | out | IOL2[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
Y[10] | - | B13/7 | Y | out | IOL8[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
Y[11] | - | B12/7 | Y | out | IOL7[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
===================================================================================================================================================================================================================
|
||||
|
||||
|
||||
|
||||
|
||||
8. All Package Pins
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
L15/0 | - | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D16/0 | - | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E14/0 | - | in | IOT4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C16/0 | - | in | IOT5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F14/0 | - | in | IOT9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F16/0 | - | in | IOT9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J14/0 | Y[7] | out | IOT22[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H11/0 | - | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L16/1 | leds[0] | out | IOT34[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
L14/1 | leds[1] | out | IOT34[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
K13/1 | - | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M14/1 | Y[6] | out | IOT40[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D14/1 | Y[8] | out | IOT44[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
E15/1 | A[2] | in | IOT44[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N16/1 | - | in | IOT52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N14/1 | - | in | IOT52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T4/4 | opCodeA[1] | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T5/4 | opCodeA[0] | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
B14/7 | Y[9] | out | IOL2[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
A15/7 | select[0] | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
C12/7 | - | in | IOL7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B12/7 | Y[11] | out | IOL7[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
B13/7 | Y[10] | out | IOL8[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
A14/7 | select[1] | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B11/7 | B[0] | in | IOL13[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A11/7 | A[0] | in | IOL15[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D11/7 | B[1] | in | IOL22[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E9/6 | Cin | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E8/6 | opCodeA[2] | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T12/2 | Y[5] | out | IOR17[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T11/2 | Y[4] | out | IOR24[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M11/2 | - | in | IOR27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T7/3 | Y[1] | out | IOR29[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P9/3 | Y[3] | out | IOR38[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N8/3 | B[3] | in | IOR40[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
L9/3 | A[3] | in | IOR40[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
P8/3 | Y[2] | out | IOR42[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N7/3 | B[2] | in | IOR47[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N6/3 | A[1] | in | IOR51[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
P6/3 | Y[0] | out | IOR53[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
========================================================================================================================================================================================
|
||||
|
||||
|
||||
@ -1,10 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
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|
||||
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|
||||
<title>Timing Analysis Report</title>
|
||||
</head>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
</html>
|
||||
@ -1,132 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Timing Report Navigation</title>
|
||||
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|
||||
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||||
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|
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|
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|
||||
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|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<!-- messages begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#Message" target="mainFrame" style=" font-size: 16px;">Timing Messages</a></li>
|
||||
<!-- messages end-->
|
||||
<!-- summaries begin-->
|
||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="ALU_tr_content.html#Summary" style=" font-size: 16px;" target="mainFrame">Timing Summaries</a>
|
||||
<ul>
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#STA_Tool_Run_Summary" style=" font-size: 14px;" target="mainFrame">STA Tool Run Summary</a></li>
|
||||
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|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#Max_Frequency_Report" style=" font-size: 14px;" target="mainFrame">Max Frequency Summary</a></li>
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#Total_Negative_Slack_Report" style=" font-size: 14px;" target="mainFrame">Total Negative Slack Summary</a></li>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="ALU_tr_content.html#Detail" style=" font-size: 16px;" target="mainFrame">Timing Details</a>
|
||||
<ul>
|
||||
<!--All_Path_Slack_Table begin-->
|
||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="ALU_tr_content.html#All_Path_Slack_Table" style=" font-size: 14px;" target="mainFrame">Path Slacks Table</a>
|
||||
<ul>
|
||||
<!--Setup_Slack_Table begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#Setup_Slack_Table" style=" font-size: 13px;" target="mainFrame">Setup Paths Table</a>
|
||||
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|
||||
<!--Setup_Slack_Table end-->
|
||||
<!--Hold_Slack_Table begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#Hold_Slack_Table" style=" font-size: 13px;" target="mainFrame">Hold Paths Table</a>
|
||||
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|
||||
<!--Hold_Slack_Table end-->
|
||||
<!--Recovery_Slack_Table begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#Recovery_Slack_Table" style=" font-size: 13px;" target="mainFrame">Recovery Paths Table</a>
|
||||
</li>
|
||||
<!--Recovery_Slack_Table end-->
|
||||
<!--Removal_Slack_Table begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#Removal_Slack_Table" style=" font-size: 13px;" target="mainFrame">Removal Paths Table</a>
|
||||
</li>
|
||||
<!--Removal_Slack_Table end-->
|
||||
</ul>
|
||||
</li><!--All_Path_Slack_Table end-->
|
||||
<!--MIN_PULSE_WIDTH_TABLE begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#MIN_PULSE_WIDTH_TABLE" style=" font-size: 14px;" target="mainFrame">Minimum Pulse Width Table</a>
|
||||
</li>
|
||||
<!--MIN_PULSE_WIDTH_TABLE end-->
|
||||
<!--Timing_Report_by_Analysis_Type begin-->
|
||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="ALU_tr_content.html#Timing_Report_by_Analysis_Type" style=" font-size: 14px;" target="mainFrame">Timing Report By Analysis Type</a>
|
||||
<ul>
|
||||
<!--Setup_Analysis begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#Setup_Analysis" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
|
||||
</li>
|
||||
<!--Setup_Analysis end-->
|
||||
<!--Hold_Analysis begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#Hold_Analysis" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
|
||||
</li>
|
||||
<!--Hold_Analysis end-->
|
||||
<!--Recovery_Analysis begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#Recovery_Analysis" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
|
||||
</li>
|
||||
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|
||||
<!--Removal_Analysis begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#Removal_Analysis" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
|
||||
</li>
|
||||
<!--Removal_Analysis end-->
|
||||
</ul>
|
||||
</li>
|
||||
<!--Timing_Report_by_Analysis_Type end-->
|
||||
<!--Minimum_Pulse_Width_Report begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#Minimum_Pulse_Width_Report" style=" font-size: 14px;" target="mainFrame">Minimum Pulse Width Report</a>
|
||||
</li>
|
||||
<!--Minimum_Pulse_Width_Report end-->
|
||||
<!--High_Fanout_Nets_Report begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#High_Fanout_Nets_Report" style=" font-size: 14px;" target="mainFrame">High Fanout Nets Report</a></li>
|
||||
<!--High_Fanout_Nets_Report end-->
|
||||
<!--Route_Congestions_Report begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#Route_Congestions_Report" style=" font-size: 14px;" target="mainFrame">Route Congestions Report</a></li>
|
||||
<!--Route_Congestions_Report end-->
|
||||
<!--Timing_Exceptions_Report begin-->
|
||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="ALU_tr_content.html#Timing_Exceptions_Report" style=" font-size: 14px;" target="mainFrame">Timing Exceptions Report</a>
|
||||
<ul>
|
||||
<!--Setup_Analysis_Exceptions begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#Setup_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
|
||||
</li>
|
||||
<!--Setup_Analysis_Exceptions end-->
|
||||
<!--Hold_Analysis_Exceptions begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#Hold_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
|
||||
</li>
|
||||
<!--Hold_Analysis_Exceptions end-->
|
||||
<!--Recovery_Analysis_Exceptions begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#Recovery_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
|
||||
</li>
|
||||
<!--Recovery_Analysis_Exceptions end-->
|
||||
<!--Removal_Analysis_Exceptions begin-->
|
||||
<li><div class="triangle_fake" onclick="onClick(this)"></div><a href="ALU_tr_content.html#Removal_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
|
||||
</li>
|
||||
<!--Removal_Analysis_Exceptions end-->
|
||||
</ul>
|
||||
</li>
|
||||
<!--Timing_Exceptions_Report end-->
|
||||
<!--SDC_Report begin-->
|
||||
<li><div class="triangle_fake"></div><a href="ALU_tr_content.html#SDC_Report" style=" font-size: 14px;" target="mainFrame">Timing Constraints Report</a></li>
|
||||
<!--SDC_Report end-->
|
||||
</ul>
|
||||
</li>
|
||||
<!-- details end-->
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
@ -1,254 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Timing Analysis Report</title>
|
||||
<style type="text/css">
|
||||
@import url(../temp/style.css);
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#content { width: 100%; margin: }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td {white-space:pre; border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="content">
|
||||
<h1><a name="Message">Timing Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>Timing Analysis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Physical Constraints File</td>
|
||||
<td>C:\Users\koray\Documents\gowin\ALU\src\top.cst</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Timing Constraint File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.10.03 (64-bit)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Thu Jan 23 05:43:13 2025
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="Summary">Timing Summaries</a></h1>
|
||||
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Setup Delay Model</td>
|
||||
<td>Slow 0.95V 85C C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Hold Delay Model</td>
|
||||
<td>Fast 1.05V 0C C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Paths Analyzed</td>
|
||||
<td>158</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Endpoints Analyzed</td>
|
||||
<td>14</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Falling Endpoints</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Setup Violated Endpoints</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Hold Violated Endpoints</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Clock_Report">Clock Summary:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">NO.</th>
|
||||
<th class="label">Clock Name</th>
|
||||
<th class="label">Type</th>
|
||||
<th class="label">Period</th>
|
||||
<th class="label">Frequency(MHz)</th>
|
||||
<th class="label">Rise</th>
|
||||
<th class="label">Fall</th>
|
||||
<th class="label">Source</th>
|
||||
<th class="label">Master</th>
|
||||
<th class="label">Objects</th>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
|
||||
<table>
|
||||
<tr>
|
||||
<th>NO.</th>
|
||||
<th>Clock Name</th>
|
||||
<th>Constraint</th>
|
||||
<th>Actual Fmax</th>
|
||||
<th>Logic Level</th>
|
||||
<th>Entity</th>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Clock Name</th>
|
||||
<th class="label">Analysis Type</th>
|
||||
<th class="label">Endpoints TNS</th>
|
||||
<th class="label">Number of Endpoints</th>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="Detail">Timing Details</a></h1>
|
||||
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
|
||||
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
|
||||
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
|
||||
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
|
||||
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
|
||||
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Number</th>
|
||||
<th class="label">Slack</th>
|
||||
<th class="label">Actual Width</th>
|
||||
<th class="label">Required Width</th>
|
||||
<th class="label">Type</th>
|
||||
<th class="label">Clock</th>
|
||||
<th class="label">Objects</th>
|
||||
</tr>
|
||||
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
</table>
|
||||
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
|
||||
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
|
||||
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>No setup paths to report!</h4>
|
||||
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
|
||||
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>No hold paths to report!</h4>
|
||||
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
|
||||
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>No recovery paths to report!</h4>
|
||||
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
|
||||
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>No removal paths to report!</h4>
|
||||
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
|
||||
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
|
||||
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">FANOUT</th>
|
||||
<th class="label">NET NAME</th>
|
||||
<th class="label">WORST SLACK</th>
|
||||
<th class="label">MAX DELAY</th>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
|
||||
<h4>Report Command:report_route_congestion -max_grids 10</h4>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">GRID LOC</th>
|
||||
<th class="label">ROUTE CONGESTIONS</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R29C29</td>
|
||||
<td>51.39%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R27C29</td>
|
||||
<td>36.11%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R27C30</td>
|
||||
<td>36.11%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R29C28</td>
|
||||
<td>33.33%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R29C30</td>
|
||||
<td>30.56%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R26C30</td>
|
||||
<td>30.56%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R27C28</td>
|
||||
<td>29.17%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R30C28</td>
|
||||
<td>27.78%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R26C28</td>
|
||||
<td>27.78%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R26C29</td>
|
||||
<td>27.78%</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
|
||||
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
|
||||
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
|
||||
<h4>No timing exceptions to report!</h4>
|
||||
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
|
||||
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
|
||||
<h4>No timing exceptions to report!</h4>
|
||||
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
|
||||
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
|
||||
<h4>No timing exceptions to report!</h4>
|
||||
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
|
||||
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
|
||||
<h4>No timing exceptions to report!</h4>
|
||||
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">SDC Command Type</th>
|
||||
<th class="label">State</th>
|
||||
<th class="label">Detail Command</th>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</body>
|
||||
</html>
|
||||
@ -1,14 +0,0 @@
|
||||
-d C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg
|
||||
-p GW2A-18-PBGA256-8
|
||||
-pn GW2A-LV18PG256C8/I7
|
||||
-cst C:\Users\koray\Documents\gowin\ALU\src\top.cst
|
||||
-cfg C:\Users\koray\Documents\gowin\ALU\impl\pnr\device.cfg
|
||||
-bit
|
||||
-tr
|
||||
-ph
|
||||
-timing
|
||||
-cst_error
|
||||
-convert_sdp32_36_to_sdp16_18
|
||||
-correct_hold 1
|
||||
-route_maxfan 23
|
||||
-global_freq 100.000
|
||||
@ -1,22 +0,0 @@
|
||||
set JTAG regular_io = false
|
||||
set SSPI regular_io = false
|
||||
set MSPI regular_io = false
|
||||
set READY regular_io = false
|
||||
set DONE regular_io = false
|
||||
set I2C regular_io = false
|
||||
set RECONFIG_N regular_io = false
|
||||
set CRC_check = true
|
||||
set compress = false
|
||||
set encryption = false
|
||||
set security_bit_enable = true
|
||||
set bsram_init_fuse_print = true
|
||||
set background_programming = off
|
||||
set secure_mode = false
|
||||
set program_done_bypass = false
|
||||
set wake_up = 0
|
||||
set format = binary
|
||||
set power_on_reset_monitor = true
|
||||
set multiboot_spi_flash_address = 0x00000000
|
||||
set vccx = 3.3
|
||||
set vcc = 1.0
|
||||
set unused_pin = default
|
||||
@ -1,702 +0,0 @@
|
||||
[
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/top.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "top",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/top.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "top",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/top.v",
|
||||
"InstLine" : 13,
|
||||
"InstName" : "a1",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/ALU.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "ALU",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/ALU.v",
|
||||
"InstLine" : 18,
|
||||
"InstName" : "opCd",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/opCode.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "opCode"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/ALU.v",
|
||||
"InstLine" : 20,
|
||||
"InstName" : "aU",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/arithmeticUnit.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "arithmeticUnit",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/arithmeticUnit.v",
|
||||
"InstLine" : 13,
|
||||
"InstName" : "a1",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/addition.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "addition",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/addition.v",
|
||||
"InstLine" : 11,
|
||||
"InstName" : "f0",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "fulladder",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
|
||||
"InstLine" : 8,
|
||||
"InstName" : "h1",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfadder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfadder"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
|
||||
"InstLine" : 9,
|
||||
"InstName" : "h2",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfadder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfadder"
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/addition.v",
|
||||
"InstLine" : 12,
|
||||
"InstName" : "f1",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "fulladder",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
|
||||
"InstLine" : 8,
|
||||
"InstName" : "h1",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfadder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfadder"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
|
||||
"InstLine" : 9,
|
||||
"InstName" : "h2",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfadder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfadder"
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/addition.v",
|
||||
"InstLine" : 13,
|
||||
"InstName" : "f2",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "fulladder",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
|
||||
"InstLine" : 8,
|
||||
"InstName" : "h1",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfadder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfadder"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
|
||||
"InstLine" : 9,
|
||||
"InstName" : "h2",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfadder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfadder"
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/addition.v",
|
||||
"InstLine" : 14,
|
||||
"InstName" : "f3",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "fulladder",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
|
||||
"InstLine" : 8,
|
||||
"InstName" : "h1",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfadder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfadder"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
|
||||
"InstLine" : 9,
|
||||
"InstName" : "h2",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfadder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfadder"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/arithmeticUnit.v",
|
||||
"InstLine" : 14,
|
||||
"InstName" : "s1",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/subtraction.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "subtraction",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/subtraction.v",
|
||||
"InstLine" : 11,
|
||||
"InstName" : "f0",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/fullsubtraction.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "fullsubtraction",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fullsubtraction.v",
|
||||
"InstLine" : 8,
|
||||
"InstName" : "hf1",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfsubtraction.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfsubtraction"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fullsubtraction.v",
|
||||
"InstLine" : 9,
|
||||
"InstName" : "hf2",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfsubtraction.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfsubtraction"
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/subtraction.v",
|
||||
"InstLine" : 12,
|
||||
"InstName" : "f1",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/fullsubtraction.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "fullsubtraction",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fullsubtraction.v",
|
||||
"InstLine" : 8,
|
||||
"InstName" : "hf1",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfsubtraction.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfsubtraction"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fullsubtraction.v",
|
||||
"InstLine" : 9,
|
||||
"InstName" : "hf2",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfsubtraction.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfsubtraction"
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/subtraction.v",
|
||||
"InstLine" : 13,
|
||||
"InstName" : "f2",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/fullsubtraction.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "fullsubtraction",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fullsubtraction.v",
|
||||
"InstLine" : 8,
|
||||
"InstName" : "hf1",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfsubtraction.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfsubtraction"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fullsubtraction.v",
|
||||
"InstLine" : 9,
|
||||
"InstName" : "hf2",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfsubtraction.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfsubtraction"
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/subtraction.v",
|
||||
"InstLine" : 14,
|
||||
"InstName" : "f3",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/fullsubtraction.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "fullsubtraction",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fullsubtraction.v",
|
||||
"InstLine" : 8,
|
||||
"InstName" : "hf1",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfsubtraction.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfsubtraction"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fullsubtraction.v",
|
||||
"InstLine" : 9,
|
||||
"InstName" : "hf2",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfsubtraction.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfsubtraction"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/ALU.v",
|
||||
"InstLine" : 21,
|
||||
"InstName" : "lU",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/logicUnit.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "logicUnit"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/ALU.v",
|
||||
"InstLine" : 22,
|
||||
"InstName" : "mU",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/multiplier.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "multiplier",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/multiplier.v",
|
||||
"InstLine" : 26,
|
||||
"InstName" : "add0",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/addition.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "addition",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/addition.v",
|
||||
"InstLine" : 11,
|
||||
"InstName" : "f0",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "fulladder",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
|
||||
"InstLine" : 8,
|
||||
"InstName" : "h1",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfadder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfadder"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
|
||||
"InstLine" : 9,
|
||||
"InstName" : "h2",
|
||||
"ModuleFile" : "C:/Users/koray/Documents/gowin/ALU/src/halfadder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfadder"
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
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|
||||
},
|
||||
{
|
||||
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/fullsubtraction.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/halfadder.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/halfsubtraction.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/logicUnit.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/multiplier.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/opCode.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/selector.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/subtraction.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/top.v",
|
||||
"Type" : "verilog"
|
||||
}
|
||||
],
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"LoopLimit" : 2000,
|
||||
"ResultFile" : "C:/Users/koray/Documents/gowin/ALU/impl/temp/rtl_parser.result",
|
||||
"Top" : "",
|
||||
"VerilogStd" : "verilog_2001",
|
||||
"VhdlStd" : "vhdl_93"
|
||||
}
|
||||
Loading…
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Reference in New Issue
Block a user