4-bit-ALU/gowin/ALU/impl/temp/rtl_parser_arg.json
2025-01-23 06:58:05 +03:00

73 lines
1.7 KiB
JSON

{
"Device" : "GW2A-18",
"Files" : [
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/addition.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/ALU.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/arithmeticUnit.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/BinaryToBCD.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/dabble.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/fullsubtraction.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/halfadder.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/halfsubtraction.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/logicUnit.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/multiplier.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/opCode.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/selector.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/subtraction.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/top.v",
"Type" : "verilog"
}
],
"IncludePath" : [
],
"LoopLimit" : 2000,
"ResultFile" : "C:/Users/koray/Documents/gowin/ALU/impl/temp/rtl_parser.result",
"Top" : "",
"VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93"
}