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README.md
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# 4-bit-ALU # 4-Bit Arithmetic Logic Unit (ALU) & 8-Bit Multiplication
Contains 4-bit ALU & 8-bit Multiplier - This project was originally designed for TTL-based implementation but was estimated to require approximately 100 TTL chips.
- Consequently, it is now being revisited for FPGA implementation using the Tang Primer 20k. The circuit also includes a 7-segment display and a 4511 TTL chip for BCD-to-7SD encoding.
- Additionally, old and unused Verilog and Logisim files are being included in the repository.
- Gowin Education v1.9.9.03 & Logisim Evolution v3.9.0
## Circuit Design
- All bits are **unsigned**.
- The circuit uses an 8-input DIP switch for **A** and **B**, a 3-input opcode selector, and a 1-bit CarryIn/BorrowIn input (depending on the opcode).
- The BCD module employs a double dabble algorithm, but the 3rd and 4th bits in the 100s position are not enabled. As a result, the integer "400" cannot be displayed on the 7-segment display.
- The opcode uses a 3-bit decoder with **one-hot encoding** for selection.
- CarryOut/BorrowOut and Overflow are displayed using LEDs.
![Circuit Image1](media/preview1.jpg)
![Circuit Image2](media/preview2.jpg)
### **Inputs:**
- **2-Bit Selector:** Determines which data is displayed on the screen.
- **3-Bit OpCode:** Specifies the operation to be performed.
- **4-Bit Input A:** The first operand.
- **4-Bit Input B:** The second operand.
- **1-Bit CarryIn/BorrowIn:** Input carry for arithmetic operations.
### **Outputs:**
- **11-Bit Result:** The ALU converts the binary result to BCD. This feature can be easily disabled if binary output is preferred.
- **1-Bit CarryOut/BorrowOut:** Indicates carry or borrow in arithmetic operations.
- **1-Bit Overflow:** Indicates an overflow condition during addition.
### Preview
<details>
<summary>Click to expand and view media of the real-life circuit.</summary>
<details>
<summary>opCode</summary>
<video controls>
<source src="media/opCode.mp4" type="video/mp4">
</video>
</details>
<details>
<summary>A&B Input</summary>
A input
![A Input](media/Ainput.jpg)
B input
![B Input](media/Binput.jpg)
</details>
<details>
<summary>Logic Unit</summary>
<details>
<summary>AND Gate</summary>
<video controls>
<source src="media/and.mp4" type="video/mp4">
</video>
</details>
<details>
<summary>OR Gate</summary>
<video controls>
<source src="media/or.mp4" type="video/mp4">
</video>
</details>
<details>
<summary>XOR Gate</summary>
<video controls>
<source src="media/xor.mp4" type="video/mp4">
</video>
</details>
</details>
<details>
<summary>Arithmetic Unit</summary>
<details>
<summary>Addition & Addition with CarryIN</summary>
<video controls>
<source src="media/additionCarryIN.mp4" type="video/mp4">
</video>
</details>
<details>
<summary>Addition & Overflow and CarryOut led</summary>
<video controls>
<source src="media/overflow.mp4" type="video/mp4">
</video>
</details>
<details>
<summary>Subtraction & BorrowOut Led</summary>
<video controls>
<source src="media/borrow.mp4" type="video/mp4">
</video>
</details>
<details>
<summary>8-2 with Borrow In</summary>
<video controls>
<source src="media/borrowin.mp4" type="video/mp4">
</video>
</details>
<details>
<summary>Multiplication</summary>
<video controls>
<source src="media/multiplication.mp4" type="video/mp4">
</video>
</details>
</details>
</details>
## Screen Selector Table
The 2-bit screen selector determines what is displayed on the screen:
| **Screen Selector** | **Displayed Data** |
| ------------------- | ------------------ |
| 00 | Input A |
| 01 | Input B |
| 10 | opCode |
| 11 | Result |
## Opcode Table
The table below describes the operations performed by the ALU based on the 3-bit opcode:
| **Opcode** | **Operation** | **Result Bits** | **Carry/Borrow In/Out Usage** |
| ---------- | -------------- | :-------------: | :--------------------: |
| 000 | Addition | 4 | ✅ |
| 001 | Subtraction | 4 | ✅ |
| 010 | Multiplication | 8 | ❌ |
| 100 | AND | 4 | ❌ |
| 101 | OR | 4 | ❌ |
| 110 | XOR | 4 | ❌ |
| 011 | ❌ | ❌ | ❌ |
| 111 | ❌ | ❌ | ❌ |
<br><br>
# Important NOTE!
## You are free to use this repository as you wish, **but please note that I am not actively maintaining it.** This repository was created for a specific project, and I would like to preserve the original code.
<br>
## Credit
- [**BUR4KBEY**](https://github.com/BUR4KBEY): Honorable mention for resolving DIP switch assignments in the FloorPlanner(Gowin). Also for this readme template.

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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2A-18" pn="GW2A-LV18PG256C8/I7">gw2a18-002</Device>
<FileList>
<File path="src/ALU.v" type="file.verilog" enable="1"/>
<File path="src/BinaryToBCD.v" type="file.verilog" enable="1"/>
<File path="src/addition.v" type="file.verilog" enable="1"/>
<File path="src/arithmeticUnit.v" type="file.verilog" enable="1"/>
<File path="src/dabble.v" type="file.verilog" enable="1"/>
<File path="src/fulladder.v" type="file.verilog" enable="1"/>
<File path="src/fullsubtraction.v" type="file.verilog" enable="1"/>
<File path="src/halfadder.v" type="file.verilog" enable="1"/>
<File path="src/halfsubtraction.v" type="file.verilog" enable="1"/>
<File path="src/logicUnit.v" type="file.verilog" enable="1"/>
<File path="src/multiplier.v" type="file.verilog" enable="1"/>
<File path="src/opCode.v" type="file.verilog" enable="1"/>
<File path="src/selector.v" type="file.verilog" enable="1"/>
<File path="src/subtraction.v" type="file.verilog" enable="1"/>
<File path="src/top.v" type="file.verilog" enable="1"/>
<File path="src/top.cst" type="file.cst" enable="1"/>
</FileList>
</Project>

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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData>
<UserConfig>
<Version>1.0</Version>
<FlowState>
<Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/>
<Process ID="Gvio" State="0"/>
<Process ID="Place" State="2"/>
</FlowState>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/ALU.vg"/>
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/ALU.fs"/>
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/ALU.pin.html"/>
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/ALU.db"/>
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/ALU.power.html"/>
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/ALU.rpt.html"/>
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/ALU.timing_paths"/>
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/ALU.tr.html"/>
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/ALU_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/ALU_syn_rsc.xml"/>
</ResultFileList>
<Ui>000000ff00000001fd00000002000000000000018e0000025dfc0200000001fc000000370000025d0000009301000016fa000000000200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000006200fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000005e00fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000007c00ffffff000000030000078000000145fc0100000001fc0000000000000780000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff000005ee0000025d00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000000000280043006f00720065002e0054006f006f006c006200610072002e00500072006f00630065007300730100000245ffffffff0000000000000000</Ui>
<FpUi></FpUi>
</UserConfig>

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GowinSynthesis start
Running parser ...
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\addition.v'
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\ALU.v'
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v'
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v'
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\dabble.v'
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\fulladder.v'
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v'
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\halfadder.v'
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\halfsubtraction.v'
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\logicUnit.v'
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\multiplier.v'
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\opCode.v'
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\selector.v'
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\subtraction.v'
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\top.v'
Compiling module 'top'("C:\Users\koray\Documents\gowin\ALU\src\top.v":1)
Compiling module 'ALU'("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":1)
Compiling module 'opCode'("C:\Users\koray\Documents\gowin\ALU\src\opCode.v":1)
Compiling module 'arithmeticUnit'("C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v":1)
Compiling module 'addition'("C:\Users\koray\Documents\gowin\ALU\src\addition.v":1)
Compiling module 'fulladder'("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":1)
Compiling module 'halfadder'("C:\Users\koray\Documents\gowin\ALU\src\halfadder.v":1)
Compiling module 'subtraction'("C:\Users\koray\Documents\gowin\ALU\src\subtraction.v":1)
Compiling module 'fullsubtraction'("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":1)
Compiling module 'halfsubtraction'("C:\Users\koray\Documents\gowin\ALU\src\halfsubtraction.v":1)
Compiling module 'logicUnit'("C:\Users\koray\Documents\gowin\ALU\src\logicUnit.v":1)
Compiling module 'multiplier'("C:\Users\koray\Documents\gowin\ALU\src\multiplier.v":1)
Compiling module 'BinaryToBCD'("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":1)
Compiling module 'dabble'("C:\Users\koray\Documents\gowin\ALU\src\dabble.v":1)
Compiling module 'selector'("C:\Users\koray\Documents\gowin\ALU\src\selector.v":1)
NOTE (EX0101) : Current top module is "top"
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "ALU" instantiated to "a1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\top.v":13)
WARN (NL0002) : The module "arithmeticUnit" instantiated to "aU" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":20)
WARN (NL0002) : The module "addition" instantiated to "a1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v":13)
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":12)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":13)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":14)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
WARN (NL0002) : The module "subtraction" instantiated to "s1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v":14)
WARN (NL0002) : The module "fullsubtraction" instantiated to "f0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\subtraction.v":11)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":8)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":9)
WARN (NL0002) : The module "fullsubtraction" instantiated to "f1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\subtraction.v":12)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":8)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":9)
WARN (NL0002) : The module "fullsubtraction" instantiated to "f2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\subtraction.v":13)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":8)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":9)
WARN (NL0002) : The module "fullsubtraction" instantiated to "f3" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\subtraction.v":14)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":8)
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":9)
WARN (NL0002) : The module "BinaryToBCD" instantiated to "btod1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":76)
WARN (NL0002) : The module "dabble" instantiated to "d1t" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":21)
WARN (NL0002) : The module "dabble" instantiated to "d2u" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":30)
WARN (NL0002) : The module "dabble" instantiated to "d3v" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":39)
WARN (NL0002) : The module "dabble" instantiated to "d4w" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":48)
WARN (NL0002) : The module "dabble" instantiated to "d5x" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":57)
WARN (NL0002) : The module "dabble" instantiated to "d6y" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":66)
WARN (NL0002) : The module "dabble" instantiated to "d7z" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":75)
WARN (NL0002) : The module "logicUnit" instantiated to "lU" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":21)
WARN (NL0002) : The module "multiplier" instantiated to "mU" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":22)
WARN (NL0002) : The module "addition" instantiated to "add0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\multiplier.v":33)
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":12)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":13)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":14)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
WARN (NL0002) : The module "addition" instantiated to "add1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\multiplier.v":49)
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":12)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":13)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":14)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
WARN (NL0002) : The module "addition" instantiated to "add2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\multiplier.v":65)
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":11)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":12)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":13)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":14)
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
WARN (NL0002) : The module "opCode" instantiated to "opCd" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":18)
[95%] Generate netlist file "C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg" completed
[100%] Generate report file "C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU_syn.rpt.html" completed
GowinSynthesis finish

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
<Version>beta</Version>
<Device id="GW2A-18" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList>
<File path="C:\Users\koray\Documents\gowin\ALU\src\addition.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\ALU.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\dabble.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\fulladder.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\halfadder.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\halfsubtraction.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\logicUnit.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\multiplier.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\opCode.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\selector.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\subtraction.v" type="verilog"/>
<File path="C:\Users\koray\Documents\gowin\ALU\src\top.v" type="verilog"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="0"/>
<Option type="global_freq" value="100.000"/>
<Option type="looplimit" value="2000"/>
<Option type="output_file" value="C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg"/>
<Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="0"/>
<Option type="vcc" value="1.0"/>
<Option type="vccx" value="3.3"/>
<Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/>
</OptionList>
</Project>

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>synthesis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper{ width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table td.label { min-width: 100px; width: 8%;}
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\koray\Documents\gowin\ALU\src\addition.v<br>
C:\Users\koray\Documents\gowin\ALU\src\ALU.v<br>
C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v<br>
C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v<br>
C:\Users\koray\Documents\gowin\ALU\src\dabble.v<br>
C:\Users\koray\Documents\gowin\ALU\src\fulladder.v<br>
C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v<br>
C:\Users\koray\Documents\gowin\ALU\src\halfadder.v<br>
C:\Users\koray\Documents\gowin\ALU\src\halfsubtraction.v<br>
C:\Users\koray\Documents\gowin\ALU\src\logicUnit.v<br>
C:\Users\koray\Documents\gowin\ALU\src\multiplier.v<br>
C:\Users\koray\Documents\gowin\ALU\src\opCode.v<br>
C:\Users\koray\Documents\gowin\ALU\src\selector.v<br>
C:\Users\koray\Documents\gowin\ALU\src\subtraction.v<br>
C:\Users\koray\Documents\gowin\ALU\src\top.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.10.03 (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu Jan 23 05:43:09 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>top</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 402.914MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 402.914MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 402.914MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 402.914MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 402.914MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 402.914MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 402.914MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 402.914MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 402.914MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 402.914MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>28</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>28</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>14</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>14</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>141</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>16</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>36</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>89</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>141(141 LUT, 0 ALU) / 20736</td>
<td><1%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>0 / 46</td>
<td>0%</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Hierarchy Module Resource</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
div#main_wrapper{ width: 100%; }
h1 {text-align: center; }
h1 {margin-top: 36px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { align = "center"; padding: 5px 2px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="content">
<h1>Hierarchy Module Resource</h1>
<table>
<tr>
<th class="label">MODULE NAME</th>
<th class="label">REG NUMBER</th>
<th class="label">ALU NUMBER</th>
<th class="label">LUT NUMBER</th>
<th class="label">DSP NUMBER</th>
<th class="label">BSRAM NUMBER</th>
<th class="label">SSRAM NUMBER</th>
<th class="label">ROM16 NUMBER</th>
</tr>
<tr>
<td class="label">top (C:/Users/koray/Documents/gowin/ALU/src/top.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">13</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--s1
(C:/Users/koray/Documents/gowin/ALU/src/top.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">128</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<Module name="top" Lut="13" T_Lut="141(13)">
<SubModule name="s1" Lut="128" T_Lut="128(128)"/>
</Module>

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Reading netlist file: "C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg"
Parsing netlist file "C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg" completed
Processing netlist completed
Reading constraint file: "C:\Users\koray\Documents\gowin\ALU\src\top.cst"
Physical Constraint parsed completed
Running placement......
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "C:\Users\koray\Documents\gowin\ALU\impl\pnr\ALU.power.html" completed
Generate file "C:\Users\koray\Documents\gowin\ALU\impl\pnr\ALU.pin.html" completed
Generate file "C:\Users\koray\Documents\gowin\ALU\impl\pnr\ALU.rpt.html" completed
Generate file "C:\Users\koray\Documents\gowin\ALU\impl\pnr\ALU.rpt.txt" completed
Generate file "C:\Users\koray\Documents\gowin\ALU\impl\pnr\ALU.tr.html" completed
Thu Jan 23 05:43:13 2025

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Power Analysis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper { width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td {white-space:pre; border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table th.label { min-width: 8%; width: 8%; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
<ul>
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
</ul>
</li>
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
<ul>
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
</ul>
</li>
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
<ul>
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="Message">Power Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Power Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>C:\Users\koray\Documents\gowin\ALU\src\top.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.10.03 (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu Jan 23 05:43:13 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h2><a name="Configure_Info">Configure Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Grade</td>
<td>Commercial</td>
</tr>
<tr>
<td class="label">Process</td>
<td>Typical</td>
</tr>
<tr>
<td class="label">Ambient Temperature</td>
<td>25.000
</tr>
<tr>
<td class="label">Use Custom Theta JA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Heat Sink</td>
<td>None</td>
</tr>
<tr>
<td class="label">Air Flow</td>
<td>LFM_0</td>
</tr>
<tr>
<td class="label">Use Custom Theta SA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Board Thermal Model</td>
<td>None</td>
</tr>
<tr>
<td class="label">Use Custom Theta JB</td>
<td>false</td>
</tr>
<tr>
<td class="label">Related Vcd File</td>
<td></td>
</tr>
<tr>
<td class="label">Related Saif File</td>
<td></td>
</tr>
<tr>
<td class="label">Filter Glitches</td>
<td>false</td>
</tr>
<tr>
<td class="label">Default IO Toggle Rate</td>
<td>0.125</td>
</tr>
<tr>
<td class="label">Default Remain Toggle Rate</td>
<td>0.125</td>
</tr>
</table>
<h1><a name="Summary">Power Summary</a></h1>
<h2><a name="Power_Info">Power Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Total Power (mW)</td>
<td>124.522</td>
</tr>
<tr>
<td class="label">Quiescent Power (mW)</td>
<td>121.169</td>
</tr>
<tr>
<td class="label">Dynamic Power (mW)</td>
<td>3.353</td>
</tr>
</table>
<h2><a name="Thermal_Info">Thermal Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Junction Temperature</td>
<td>28.987</td>
</tr>
<tr>
<td class="label">Theta JA</td>
<td>32.020</td>
</tr>
<tr>
<td class="label">Max Allowed Ambient Temperature</td>
<td>81.013</td>
</tr>
</table>
<h2><a name="Supply_Summary">Supply Information:</a></h2>
<table class="summary_table">
<tr>
<th class="label">Voltage Source</th>
<th class="label">Voltage</th>
<th class="label">Dynamic Current(mA)</th>
<th class="label">Quiescent Current(mA)</th>
<th class="label">Power(mW)</th>
</tr>
<tr>
<td>VCC</td>
<td>1.000</td>
<td>0.552</td>
<td>69.981</td>
<td>70.533</td>
</tr>
<tr>
<td>VCCX</td>
<td>3.300</td>
<td>0.552</td>
<td>15.000</td>
<td>51.322</td>
</tr>
<tr>
<td>VCCIO18</td>
<td>1.800</td>
<td>0.544</td>
<td>0.938</td>
<td>2.668</td>
</tr>
</table>
<h1><a name="Detail">Power Details</a></h1>
<h2><a name="By_Block_Type">Power By Block Type:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Block Type</th>
<th class="label">Total Power(mW)</th>
<th class="label">Static Power(mW)</th>
<th class="label">Average Toggle Rate(millions of transitions/sec)</th>
</tr>
<tr>
<td>IO</td>
<td>8.544
<td>5.191
<td>6.250
</tr>
</table>
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Hierarchy Entity</th>
<th class="label">Total Power(mW)</th>
<th class="label">Block Dynamic Power(mW)</th>
</tr>
<tr>
<td>top</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/s1/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
</table>
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Domain</th>
<th class="label">Clock Frequency(Mhz)</th>
<th class="label">Total Dynamic Power(mW)</th>
</tr>
<tr>
<td>NO CLOCK DOMAIN</td>
<td>0.000</td>
<td>0.000</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
1. PnR Messages
<Report Title>: PnR Report
<Design File>: C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg
<Physical Constraints File>: C:\Users\koray\Documents\gowin\ALU\src\top.cst
<Timing Constraints File>: ---
<Tool Version>: V1.9.10.03 (64-bit)
<Part Number>: GW2A-LV18PG256C8/I7
<Device>: GW2A-18
<Created Time>:Thu Jan 23 05:43:13 2025
2. PnR Details
Running placement:
Placement Phase 0: CPU time = 0h 0m 0.017s, Elapsed time = 0h 0m 0.017s
Placement Phase 1: CPU time = 0h 0m 0.344s, Elapsed time = 0h 0m 0.344s
Placement Phase 2: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.008s
Placement Phase 3: CPU time = 0h 0m 0.847s, Elapsed time = 0h 0m 0.847s
Total Placement: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Running routing:
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Routing Phase 1: CPU time = 0h 0m 0.149s, Elapsed time = 0h 0m 0.149s
Routing Phase 2: CPU time = 0h 0m 0.202s, Elapsed time = 0h 0m 0.202s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Total Routing: CPU time = 0h 0m 0.351s, Elapsed time = 0h 0m 0.351s
Generate output files:
CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Time and Memory Usage: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 444MB
3. Resource Usage Summary
--------------------------------------------------------------------------------
Resources | Usage | Utilization
--------------------------------------------------------------------------------
Logic | 141/20736 | <1%
--LUT,ALU,ROM16 | 141(141 LUT, 0 ALU, 0 ROM16) | -
--SSRAM(RAM16) | 0 | -
Register | 0/16173 | 0%
--Logic Register as Latch | 0/15552 | 0%
--Logic Register as FF | 0/15552 | 0%
--I/O Register as Latch | 0/621 | 0%
--I/O Register as FF | 0/621 | 0%
CLS | 77/10368 | <1%
I/O Port | 28/207 | 14%
I/O Buf | 28 | -
--Input Buf | 14 | -
--Output Buf | 14 | -
--Inout Buf | 0 | -
================================================================================
4. I/O Bank Usage Summary
--------------------------------------
I/O Bank | Usage | Utilization
--------------------------------------
bank 0 | 1/29 | 4%
bank 1 | 5/20 | 25%
bank 2 | 2/20 | 10%
bank 3 | 8/32 | 25%
bank 4 | 2/36 | 6%
bank 5 | 0/36 | 0%
bank 6 | 2/18 | 12%
bank 7 | 8/16 | 50%
======================================
5. Clock Resource Usage Summary
------------------------------------------
Clock Resource| Usage | Utilization
------------------------------------------
PRIMARY | 0/8 | 0%
LW | 0/8 | 0%
GCLK_PIN | 1/8 | 13%
==========================================
6. Global Clock Signals
-------------------------------------------
Signal | Global Clock | Location
-------------------------------------------
===========================================
7. Pinout by Port Name
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
A[0] | - | A11/7 | Y | in | IOL15[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
A[1] | - | N6/3 | Y | in | IOR51[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
A[2] | - | E15/1 | Y | in | IOT44[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | NA | NA | 1.8
A[3] | - | L9/3 | Y | in | IOR40[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
B[0] | - | B11/7 | Y | in | IOL13[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
B[1] | - | D11/7 | Y | in | IOL22[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
B[2] | - | N7/3 | Y | in | IOR47[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
B[3] | - | N8/3 | Y | in | IOR40[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
opCodeA[0] | - | T5/4 | Y | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
opCodeA[1] | - | T4/4 | Y | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
opCodeA[2] | - | E8/6 | Y | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
select[0] | - | A15/7 | Y | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
select[1] | - | A14/7 | Y | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
Cin | - | E9/6 | Y | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
leds[0] | - | L16/1 | Y | out | IOT34[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
leds[1] | - | L14/1 | Y | out | IOT34[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
Y[0] | - | P6/3 | Y | out | IOR53[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[1] | - | T7/3 | Y | out | IOR29[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[2] | - | P8/3 | Y | out | IOR42[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[3] | - | P9/3 | Y | out | IOR38[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[4] | - | T11/2 | Y | out | IOR24[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[5] | - | T12/2 | Y | out | IOR17[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[6] | - | M14/1 | Y | out | IOT40[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
Y[7] | - | J14/0 | Y | out | IOT22[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
Y[8] | - | D14/1 | Y | out | IOT44[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
Y[9] | - | B14/7 | Y | out | IOL2[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[10] | - | B13/7 | Y | out | IOL8[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
Y[11] | - | B12/7 | Y | out | IOL7[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
===================================================================================================================================================================================================================
8. All Package Pins
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
L15/0 | - | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D16/0 | - | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E14/0 | - | in | IOT4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C16/0 | - | in | IOT5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F14/0 | - | in | IOT9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F16/0 | - | in | IOT9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J14/0 | Y[7] | out | IOT22[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H11/0 | - | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L16/1 | leds[0] | out | IOT34[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
L14/1 | leds[1] | out | IOT34[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
K13/1 | - | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M14/1 | Y[6] | out | IOT40[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D14/1 | Y[8] | out | IOT44[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
E15/1 | A[2] | in | IOT44[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | NA | NA | 1.8
N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N16/1 | - | in | IOT52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N14/1 | - | in | IOT52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T4/4 | opCodeA[1] | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T5/4 | opCodeA[0] | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
B14/7 | Y[9] | out | IOL2[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
A15/7 | select[0] | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
C12/7 | - | in | IOL7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B12/7 | Y[11] | out | IOL7[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
B13/7 | Y[10] | out | IOL8[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
A14/7 | select[1] | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B11/7 | B[0] | in | IOL13[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A11/7 | A[0] | in | IOL15[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D11/7 | B[1] | in | IOL22[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E9/6 | Cin | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E8/6 | opCodeA[2] | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T12/2 | Y[5] | out | IOR17[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T11/2 | Y[4] | out | IOR24[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M11/2 | - | in | IOR27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T7/3 | Y[1] | out | IOR29[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P9/3 | Y[3] | out | IOR38[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N8/3 | B[3] | in | IOR40[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
L9/3 | A[3] | in | IOR40[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
P8/3 | Y[2] | out | IOR42[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N7/3 | B[2] | in | IOR47[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N6/3 | A[1] | in | IOR51[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
P6/3 | Y[0] | out | IOR53[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
========================================================================================================================================================================================

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<body>
<div id="content">
<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>C:\Users\koray\Documents\gowin\ALU\src\top.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.10.03 (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu Jan 23 05:43:13 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.95V 85C C8/I7</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.05V 0C C8/I7</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>158</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>14</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">NO.</th>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
</table>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h4>Nothing to report!</h4>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h4>No setup paths to report!</h4>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h4>No hold paths to report!</h4>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>No recovery paths to report!</h4>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>No removal paths to report!</h4>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h4>Nothing to report!</h4>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R29C29</td>
<td>51.39%</td>
</tr>
<tr>
<td>R27C29</td>
<td>36.11%</td>
</tr>
<tr>
<td>R27C30</td>
<td>36.11%</td>
</tr>
<tr>
<td>R29C28</td>
<td>33.33%</td>
</tr>
<tr>
<td>R29C30</td>
<td>30.56%</td>
</tr>
<tr>
<td>R26C30</td>
<td>30.56%</td>
</tr>
<tr>
<td>R27C28</td>
<td>29.17%</td>
</tr>
<tr>
<td>R30C28</td>
<td>27.78%</td>
</tr>
<tr>
<td>R26C28</td>
<td>27.78%</td>
</tr>
<tr>
<td>R26C29</td>
<td>27.78%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
</div><!-- content -->
</body>
</html>

14
gowin/ALU/impl/pnr/cmd.do Normal file
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@ -0,0 +1,14 @@
-d C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg
-p GW2A-18-PBGA256-8
-pn GW2A-LV18PG256C8/I7
-cst C:\Users\koray\Documents\gowin\ALU\src\top.cst
-cfg C:\Users\koray\Documents\gowin\ALU\impl\pnr\device.cfg
-bit
-tr
-ph
-timing
-cst_error
-convert_sdp32_36_to_sdp16_18
-correct_hold 1
-route_maxfan 23
-global_freq 100.000

22
gowin/ALU/impl/pnr/device.cfg Normal file
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@ -0,0 +1,22 @@
set JTAG regular_io = false
set SSPI regular_io = false
set MSPI regular_io = false
set READY regular_io = false
set DONE regular_io = false
set I2C regular_io = false
set RECONFIG_N regular_io = false
set CRC_check = true
set compress = false
set encryption = false
set security_bit_enable = true
set bsram_init_fuse_print = true
set background_programming = off
set secure_mode = false
set program_done_bypass = false
set wake_up = 0
set format = binary
set power_on_reset_monitor = true
set multiboot_spi_flash_address = 0x00000000
set vccx = 3.3
set vcc = 1.0
set unused_pin = default

702
gowin/ALU/impl/temp/rtl_parser.result Normal file
View File

@ -0,0 +1,702 @@
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]
}
]

73
gowin/ALU/impl/temp/rtl_parser_arg.json Normal file
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@ -0,0 +1,73 @@
{
"Device" : "GW2A-18",
"Files" : [
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/addition.v",
"Type" : "verilog"
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{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/ALU.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/arithmeticUnit.v",
"Type" : "verilog"
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{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/BinaryToBCD.v",
"Type" : "verilog"
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{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/dabble.v",
"Type" : "verilog"
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{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/fulladder.v",
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{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/fullsubtraction.v",
"Type" : "verilog"
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{
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"Type" : "verilog"
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{
"Path" : "C:/Users/koray/Documents/gowin/ALU/src/halfsubtraction.v",
"Type" : "verilog"
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{
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{
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{
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{
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"Top" : "",
"VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93"
}

79
gowin/ALU/src/ALU.v Normal file
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module ALU (
input [3:0] A, B,
input CarryIN,
input [2:0] opCodeA,
output [11:0] bcd,
output CarryOUT, overflow
);
// Supports: ADD[0], SUB[1], MULT[2], AND[4], OR[5], XOR[6]
wire [7:0] opCode8;
wire [3:0] add_Y, sub_Y;
wire [3:0] resultA, resultO, resultX, lUOutput1;
wire [3:0] aUtemp1, aUtemp2, lUOutput2;
wire [3:0] wireY, wireLA;
wire [7:0] opwireM, wireM, Y;
opCode opCd (.A(opCodeA), .opCode(opCode8));
arithmeticUnit aU(.opCode(opCode8[1:0]), .A(A), .B(B), .CarryIN(CarryIN), .add_Y(add_Y), .sub_Y(sub_Y), .CarryOUT(CarryOUT), .overflow(overflow));
logicUnit lU (.opCode(opCode8[6:4]), .A(A), .B(B), .resultA(resultA), .resultO(resultO), .resultX(resultX));
multiplier mU (.A(A), .B(B), .Y(opwireM));
or o01 (lUOutput1[0], resultA[0], resultO[0]);
or o02 (lUOutput1[1], resultA[1], resultO[1]);
or o03 (lUOutput1[2], resultA[2], resultO[2]);
or o04 (lUOutput1[3], resultA[3], resultO[3]);
or o11 (lUOutput2[0], lUOutput1[0], resultX[0]);
or o12 (lUOutput2[1], lUOutput1[1], resultX[1]);
or o13 (lUOutput2[2], lUOutput1[2], resultX[2]);
or o14 (lUOutput2[3], lUOutput1[3], resultX[3]);
and a01 (aUtemp1[0], opCode8[0], add_Y[0]);
and a02 (aUtemp1[1], opCode8[0], add_Y[1]);
and a03 (aUtemp1[2], opCode8[0], add_Y[2]);
and a04 (aUtemp1[3], opCode8[0], add_Y[3]);
and a11 (aUtemp2[0], opCode8[1], sub_Y[0]);
and a12 (aUtemp2[1], opCode8[1], sub_Y[1]);
and a13 (aUtemp2[2], opCode8[1], sub_Y[2]);
and a14 (aUtemp2[3], opCode8[1], sub_Y[3]);
and a21 (wireM[0], opCode8[2], opwireM[0]);
and a22 (wireM[1], opCode8[2], opwireM[1]);
and a23 (wireM[2], opCode8[2], opwireM[2]);
and a24 (wireM[3], opCode8[2], opwireM[3]);
and a25 (wireM[4], opCode8[2], opwireM[4]);
and a26 (wireM[5], opCode8[2], opwireM[5]);
and a27 (wireM[6], opCode8[2], opwireM[6]);
and a28 (wireM[7], opCode8[2], opwireM[7]);
or o21 (wireY[0], aUtemp1[0], aUtemp2[0]);
or o22 (wireY[1], aUtemp1[1], aUtemp2[1]);
or o23 (wireY[2], aUtemp1[2], aUtemp2[2]);
or o24 (wireY[3], aUtemp1[3], aUtemp2[3]);
or o1 (wireLA[0], lUOutput2[0], wireY[0]);
or o2 (wireLA[1], lUOutput2[1], wireY[1]);
or o3 (wireLA[2], lUOutput2[2], wireY[2]);
or o4 (wireLA[3], lUOutput2[3], wireY[3]);
or o31 (Y[0], wireLA[0], wireM[0]);
or o32 (Y[1], wireLA[1], wireM[1]);
or o33 (Y[2], wireLA[2], wireM[2]);
or o34 (Y[3], wireLA[3], wireM[3]);
or o35 (Y[4], 1'b0, wireM[4]);
or o36 (Y[5], 1'b0, wireM[5]);
or o37 (Y[6], 1'b0, wireM[6]);
or o38 (Y[7], 1'b0, wireM[7]);
BinaryToBCD btod1(.binary(Y), .bcd(bcd)); // WIRE Y BINARY!!!!
endmodule

79
gowin/ALU/src/BinaryToBCD.v Normal file
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module BinaryToBCD (
input [7:0] binary,
output [11:0] bcd
);
wire empty1, empty2;
wire [3:0] dab1, dab2, dab3, dab4, dab5;
and a111 (empty1, 1'b0, 1'b0);
and a000 (empty2, 1'b0, 1'b0);
and a222 (bcd[11], 1'b0, 1'b0);
and a223 (bcd[10], 1'b0, 1'b0);
dabble d1t (.A((empty1)),
.B(binary[7]),
.C(binary[6]),
.D(binary[5]),
.X(dab1[0]),
.Y(dab1[1]),
.Z(dab1[2]),
.E(dab1[3]));
dabble d2u (.A((dab1[1])),
.B(dab1[2]),
.C(dab1[3]),
.D(binary[4]),
.X(dab2[0]),
.Y(dab2[1]),
.Z(dab2[2]),
.E(dab2[3]));
dabble d3v (.A((dab2[1])),
.B(dab2[2]),
.C(dab2[3]),
.D(binary[3]),
.X(dab3[0]),
.Y(dab3[1]),
.Z(dab3[2]),
.E(dab3[3]));
dabble d4w (.A((empty2)),
.B(dab1[0]),
.C(dab2[0]),
.D(dab3[0]),
.X(bcd[9]),
.Y(dab4[1]),
.Z(dab4[2]),
.E(dab4[3]));
dabble d5x (.A((dab3[1])),
.B(dab3[2]),
.C(dab3[3]),
.D(binary[2]),
.X(dab5[0]),
.Y(dab5[1]),
.Z(dab5[2]),
.E(dab5[3]));
dabble d6y (.A((dab4[1])),
.B(dab4[2]),
.C(dab4[3]),
.D(dab5[0]),
.X(bcd[8]),
.Y(bcd[7]),
.Z(bcd[6]),
.E(bcd[5]));
dabble d7z (.A((dab5[1])),
.B(dab5[2]),
.C(dab5[3]),
.D(binary[1]),
.X(bcd[4]),
.Y(bcd[3]),
.Z(bcd[2]),
.E(bcd[1]));
or o1 (bcd[0], binary[0], 1'b0);
endmodule

20
gowin/ALU/src/addition.v Normal file
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module addition (
input [3:0] A, B,
input CarryIN,
output [3:0] Y,
output CarryOUT,
output overflow
);
wire [2:0] Carry4;
fulladder f0(.A(A[0]), .B(B[0]), .Carry(CarryIN), .Sum(Y[0]), .CarryO(Carry4[0]));
fulladder f1(.A(A[1]), .B(B[1]), .Carry(Carry4[0]), .Sum(Y[1]), .CarryO(Carry4[1]));
fulladder f2(.A(A[2]), .B(B[2]), .Carry(Carry4[1]), .Sum(Y[2]), .CarryO(Carry4[2]));
fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(CarryOUT));
//overflowDetect od1 (.opCode(2'b01), .A(A), .B(B), .Y(Y), .CarryOUT(CarryOUT), .overflowDetect(overflow)); (KULLANILMAYACAK!!!!)
xor ov1 (overflow, Carry4[2], CarryOUT);
endmodule

33
gowin/ALU/src/arithmeticUnit.v Normal file
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module arithmeticUnit (
input [1:0] opCode,
input [3:0] A, B,
input CarryIN,
output [3:0] add_Y, sub_Y,
output CarryOUT,
output overflow
);
wire [3:0] addY, subY;
wire CarryOUTADD, CarryOUTSUB, tempCAdd, tempCSub, tempoverflow;
addition a1(.A(A), .B(B), .CarryIN(CarryIN), .Y(addY), .CarryOUT(CarryOUTADD), .overflow(tempoverflow));
subtraction s1(.A(A), .B(B), .BorrowIN(CarryIN), .Y(subY), .BorrowOUT(CarryOUTSUB));
and add1 (add_Y[0], opCode[0], addY[0]);
and add2 (add_Y[1], opCode[0], addY[1]);
and add3 (add_Y[2], opCode[0], addY[2]);
and add4 (add_Y[3], opCode[0], addY[3]);
and sub1 (sub_Y[0], opCode[1], subY[0]);
and sub2 (sub_Y[1], opCode[1], subY[1]);
and sub3 (sub_Y[2], opCode[1], subY[2]);
and sub4 (sub_Y[3], opCode[1], subY[3]);
// or or1 (CarryOUT, CarryOUTADD, CarryOUTSUB); (OLD!!!)
and and10 (tempCSub, CarryOUTSUB, opCode[1]);
and and11 (tempCAdd, CarryOUTADD, opCode[0]);
or or4 (CarryOUT, tempCAdd, tempCSub);
and add12 (overflow, opCode[0], tempoverflow);
endmodule

22
gowin/ALU/src/dabble.v Normal file
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module dabble (
input A, B, C, D,
output X, Y, Z, E
);
wire xor1, nor1, xor2, nor2, nor3, or1;
xor xo1 (xor1, A, D);
nor no1 (nor1, A, B);
xor xo2 (xor2, A, C);
nor no2 (nor2, xor1, xor2);
nor no3 (nor3, nor2, nor1);
buf bu1 (X, nor3);
or o1 (or1, xor1, nor1);
nor no4 (Y, or1, C);
and an1 (Z, or1, xor2);
xor xo3 (E, nor3, D);
endmodule

12
gowin/ALU/src/fulladder.v Normal file
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module fulladder (
input A, B, Carry,
output Sum, CarryO
);
wire xor1, and1, and2;
halfadder h1(.A(A), .B(B), .Sum(xor1), .Carry(and1));
halfadder h2 (.A(xor1), .B(Carry), .Sum(Sum), .Carry(and2));
or o1 (CarryO, and1, and2);
endmodule

12
gowin/ALU/src/fullsubtraction.v Normal file
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module fullsubtraction (
input A, B, BorrowIN,
output Difference, BorrowOut
);
wire tempD, tempB1, tempB2;
halfsubtraction hf1(.A(A), .B(B), .Difference(tempD), .Borrow(tempB1));
halfsubtraction hf2(.A(tempD), .B(BorrowIN), .Difference(Difference), .Borrow(tempB2));
or o1 (BorrowOut, tempB1, tempB2);
endmodule

9
gowin/ALU/src/halfadder.v Normal file
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module halfadder (
input A, B,
output Sum, Carry
);
and a1 (Carry, A, B);
xor xo1 (Sum, A, B);
endmodule

12
gowin/ALU/src/halfsubtraction.v Normal file
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module halfsubtraction (
input A, B,
output Difference, Borrow
);
wire notA;
xor xo1 (Difference, A, B);
not a1 (notA, A);
and an1 (Borrow, notA, B);
endmodule

39
gowin/ALU/src/logicUnit.v Normal file
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module logicUnit (
input [2:0] opCode,
input [3:0] A, B,
output [3:0] resultA, resultO, resultX
);
wire [3:0] and1, or1, xor1;
and a01 (and1[0], A[0], B[0]);
and a02 (and1[1], A[1], B[1]);
and a03 (and1[2], A[2], B[2]);
and a04 (and1[3], A[3], B[3]);
or o01 (or1[0], A[0], B[0]);
or o02 (or1[1], A[1], B[1]);
or o03 (or1[2], A[2], B[2]);
or o04 (or1[3], A[3], B[3]);
xor xor01 (xor1[0], A[0], B[0]);
xor xor02 (xor1[1], A[1], B[1]);
xor xor03 (xor1[2], A[2], B[2]);
xor xor04 (xor1[3], A[3], B[3]);
and a_o1 (resultA[0], opCode[0], and1[0]);
and a_o2 (resultA[1], opCode[0], and1[1]);
and a_o3 (resultA[2], opCode[0], and1[2]);
and a_o4 (resultA[3], opCode[0], and1[3]);
and o_o1 (resultO[0], opCode[1], or1[0]);
and o_o2 (resultO[1], opCode[1], or1[1]);
and o_o3 (resultO[2], opCode[1], or1[2]);
and o_o4 (resultO[3], opCode[1], or1[3]);
and x_o1 (resultX[0], opCode[2], xor1[0]);
and x_o2 (resultX[1], opCode[2], xor1[1]);
and x_o3 (resultX[2], opCode[2], xor1[2]);
and x_o4 (resultX[3], opCode[2], xor1[3]);
endmodule

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gowin/ALU/src/multiplier.v Normal file
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module multiplier (
input [3:0] A, B,
output [7:0] Y
);
wire [3:0] b0, a0, a1, a2;
wire [4:0] S0, S1, S2;
wire carry0, carry1, carry2;
wire overflow0, overflow1, overflow2;
// Partial product generation
and (Y[0], A[0], B[0]); // LSB of the result
// Generate partial products for B[0] and B[1]
and ab00 (b0[0], A[1], B[0]);
and ab01 (b0[1], A[2], B[0]);
and ab02 (b0[2], A[3], B[0]);
not ab03 (b0[3], 1'b1); // Initialize b0[3] to 0
and aa00 (a0[0], A[0], B[1]);
and aa01 (a0[1], A[1], B[1]);
and aa02 (a0[2], A[2], B[1]);
and aa03 (a0[3], A[3], B[1]);
// First addition
addition add0 (
.A(a0),
.B(b0),
.CarryIN(1'b0),
.Y(S0[3:0]),
.CarryOUT(S0[4]),
.overflow(overflow0)
);
// Generate partial products for B[2]
and aa10 (a1[0], A[0], B[2]);
and aa11 (a1[1], A[1], B[2]);
and aa12 (a1[2], A[2], B[2]);
and aa13 (a1[3], A[3], B[2]);
// Second addition
addition add1 (
.A(a1),
.B(S0[4:1]),
.CarryIN(1'b0),
.Y(S1[3:0]),
.CarryOUT(S1[4]),
.overflow(overflow1)
);
// Generate partial products for B[3]
and aa20 (a2[0], A[0], B[3]);
and aa21 (a2[1], A[1], B[3]);
and aa22 (a2[2], A[2], B[3]);
and aa23 (a2[3], A[3], B[3]);
// Third addition
addition add2 (
.A(a2),
.B(S1[4:1]),
.CarryIN(1'b0),
.Y(S2[3:0]),
.CarryOUT(S2[4]),
.overflow(overflow2)
);
// Combine results into the final output Y
or o01 (Y[1], S0[0], 1'b0);
or o02 (Y[2], S1[0], 1'b0);
or o03 (Y[3], S2[0], 1'b0);
or o04 (Y[4], S2[1], 1'b0);
or o05 (Y[5], S2[2], 1'b0);
or o06 (Y[6], S2[3], 1'b0);
or o07 (Y[7], S2[4], 1'b0);
endmodule

25
gowin/ALU/src/opCode.v Normal file
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module opCode (
input [2:0] A,
output [7:0] opCode
);
wire and1, and2, and3, and4, notA, notB, notC;
not n1(notA, A[2]);
not n2(notB, A[1]);
not n3(notC, A[0]);
and a01(and1, A[2], A[1]);
and a02(and2, notA, A[1]);
and a03(and3, A[2], notB);
and a04(and4, notA, notB);
and a1(opCode[0], and4, notC);
and a2(opCode[1], and4, A[0]);
and a3(opCode[2], and2, notC);
and a4(opCode[3], and2, A[0]);
and a5(opCode[4], and3, notC);
and a6(opCode[5], and3, A[0]);
and a7(opCode[6], and1, notC);
and a8(opCode[7], and1, A[0]);
endmodule

20
gowin/ALU/src/selector.v Normal file
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module selector (
input [3:0] A,
input [3:0] B,
input [2:0] opCodeA,
input [1:0] select,
input [11:0] ALUY,
output reg [11:0] Y
);
always @(*) begin
case (select)
2'b00: Y = {8'b00000000, A}; // Zero-extend A to 8 bits
2'b01: Y = {8'b00000000, B}; // Zero-extend B to 8 bits
2'b10: Y = {9'b000000000, opCodeA}; // Zero-extend opCodeA to 8 bits
2'b11: Y = ALUY; // Directly assign ALUY
default: Y = ALUY; // Default case for safety
endcase
end
endmodule

16
gowin/ALU/src/subtraction.v Normal file
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module subtraction (
input [3:0] A, B,
input BorrowIN,
output [3:0] Y,
output BorrowOUT //Overflow signal'ini yani negatif gonderecek
);
wire [3:0] tempB;
// Full Subtraction logic for each bit (borrow-in for each subsequent bit)
fullsubtraction f0 (.A(A[0]), .B(B[0]), .BorrowIN(BorrowIN), .Difference(Y[0]), .BorrowOut(tempB[0]));
fullsubtraction f1 (.A(A[1]), .B(B[1]), .BorrowIN(tempB[0]), .Difference(Y[1]), .BorrowOut(tempB[1]));
fullsubtraction f2 (.A(A[2]), .B(B[2]), .BorrowIN(tempB[1]), .Difference(Y[2]), .BorrowOut(tempB[2]));
fullsubtraction f3 (.A(A[3]), .B(B[3]), .BorrowIN(tempB[2]), .Difference(Y[3]), .BorrowOut(BorrowOUT));
endmodule

65
gowin/ALU/src/top.cst Normal file
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//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Physical Constraints file
//Tool Version: V1.9.9.03 Education (64-bit)
//Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18
//Device Version: C
//Created Time: Mon 01 20 17:48:00 2025
IO_LOC "Y[11]" B12;
IO_PORT "Y[11]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[10]" B13;
IO_PORT "Y[10]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[9]" B14;
IO_PORT "Y[9]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[8]" D14;
IO_PORT "Y[8]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[7]" J14;
IO_PORT "Y[7]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[6]" M14;
IO_PORT "Y[6]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[5]" T12;
IO_PORT "Y[5]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[4]" T11;
IO_PORT "Y[4]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[3]" P9;
IO_PORT "Y[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[2]" P8;
IO_PORT "Y[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[1]" T7;
IO_PORT "Y[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[0]" P6;
IO_PORT "Y[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[1]" L14;
IO_PORT "leds[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[0]" L16;
IO_PORT "leds[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Cin" E9;
IO_PORT "Cin" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "select[1]" A14;
IO_PORT "select[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "select[0]" A15;
IO_PORT "select[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[2]" E8;
IO_PORT "opCodeA[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[1]" T4;
IO_PORT "opCodeA[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[0]" T5;
IO_PORT "opCodeA[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "B[3]" N8;
IO_PORT "B[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[2]" N7;
IO_PORT "B[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[1]" D11;
IO_PORT "B[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[0]" B11;
IO_PORT "B[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[3]" L9;
IO_PORT "A[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[2]" E15;
IO_PORT "A[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[1]" N6;
IO_PORT "A[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[0]" A11;
IO_PORT "A[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;

19
gowin/ALU/src/top.v Normal file
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module top (
input [3:0] A, B,
input [2:0] opCodeA,
input [1:0] select,
input Cin,
output [1:0] leds,
output [11:0] Y
);
wire wire1, wire2;
wire [11:0] selectY;
ALU a1(.A(A), .B(B), .opCodeA(opCodeA), .CarryIN(Cin), .bcd(selectY), .CarryOUT(wire2), .overflow(wire1)); //ALU module
selector s1(.A(A), .B(B), .opCodeA(opCodeA), .select(select), .ALUY(selectY), .Y(Y)); // selector for 7 segment
assign leds[0] = ~wire1; //overflow led
assign leds[1] = ~wire2; //CarryOut/BorrowOut led
endmodule

200
logisim/!OLDarithmeticTEST.circ Normal file
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@ -0,0 +1,200 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.9.0" version="1.0">
This file is intended to be loaded by Logisim-evolution v3.9.0(https://github.com/logisim-evolution/).
<lib desc="#Wiring" name="0">
<tool name="Splitter">
<a name="facing" val="west"/>
</tool>
<tool name="Pin">
<a name="appearance" val="classic"/>
</tool>
</lib>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4"/>
<lib desc="#I/O" name="5"/>
<lib desc="#TTL" name="6"/>
<lib desc="#TCL" name="7"/>
<lib desc="#Base" name="8"/>
<lib desc="#BFH-Praktika" name="9"/>
<lib desc="#Input/Output-Extra" name="10"/>
<lib desc="#Soc" name="11"/>
<lib desc="file#arithmeticunit.circ" name="12"/>
<main name="autest"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Poke Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Wiring Tool"/>
<tool lib="8" name="Text Tool"/>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
</tool>
<sep/>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
<tool lib="1" name="XOR Gate"/>
<tool lib="1" name="NAND Gate"/>
<tool lib="1" name="NOR Gate"/>
<sep/>
<tool lib="4" name="D Flip-Flop"/>
<tool lib="4" name="Register"/>
</toolbar>
<circuit name="autest">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="autest"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
<comp lib="0" loc="(160,300)" name="Splitter">
<a name="facing" val="north"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(260,280)" name="Splitter">
<a name="facing" val="north"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(360,250)" name="Pin">
<a name="appearance" val="NewPins"/>
</comp>
<comp lib="0" loc="(380,200)" name="Splitter"/>
<comp lib="0" loc="(740,480)" name="Splitter">
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(750,250)" name="Splitter">
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(780,530)" name="Ground"/>
<comp lib="0" loc="(790,300)" name="Ground"/>
<comp lib="0" loc="(810,430)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="9"/>
<a name="incoming" val="9"/>
</comp>
<comp lib="0" loc="(820,200)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="9"/>
<a name="incoming" val="9"/>
</comp>
<comp lib="12" loc="(600,230)" name="arithmeticUnit"/>
<comp lib="5" loc="(160,270)" name="DipSwitch">
<a name="facing" val="south"/>
<a name="number" val="4"/>
</comp>
<comp lib="5" loc="(260,240)" name="DipSwitch">
<a name="facing" val="south"/>
<a name="number" val="4"/>
</comp>
<comp lib="5" loc="(400,200)" name="DipSwitch">
<a name="facing" val="west"/>
<a name="number" val="2"/>
</comp>
<comp lib="5" loc="(630,320)" name="LED">
<a name="facing" val="north"/>
</comp>
<comp lib="5" loc="(670,350)" name="LED">
<a name="facing" val="north"/>
</comp>
<comp lib="5" loc="(860,290)" name="7-Segment Display"/>
<comp lib="5" loc="(870,60)" name="7-Segment Display"/>
<comp lib="5" loc="(920,290)" name="7-Segment Display"/>
<comp lib="5" loc="(930,60)" name="7-Segment Display"/>
<comp lib="5" loc="(980,290)" name="7-Segment Display"/>
<comp lib="5" loc="(990,60)" name="7-Segment Display"/>
<comp lib="8" loc="(512,186)" name="Text">
<a name="text" val="decoded opCode"/>
</comp>
<comp lib="8" loc="(581,379)" name="Text">
<a name="text" val="and CarryOut in add"/>
</comp>
<comp lib="8" loc="(616,358)" name="Text">
<a name="text" val="negative"/>
</comp>
<comp lib="9" loc="(860,290)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(870,420)" name="Binary_to_BCD_converter"/>
<comp lib="9" loc="(870,60)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(880,190)" name="Binary_to_BCD_converter"/>
<comp lib="9" loc="(920,290)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(930,60)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(980,290)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(990,60)" name="BCD_to_7_Segment_decoder"/>
<wire from="(1000,140)" to="(1000,170)"/>
<wire from="(120,270)" to="(120,280)"/>
<wire from="(130,270)" to="(130,280)"/>
<wire from="(140,270)" to="(140,280)"/>
<wire from="(150,270)" to="(150,280)"/>
<wire from="(160,300)" to="(380,300)"/>
<wire from="(220,240)" to="(220,260)"/>
<wire from="(230,240)" to="(230,260)"/>
<wire from="(240,240)" to="(240,260)"/>
<wire from="(250,240)" to="(250,260)"/>
<wire from="(260,280)" to="(380,280)"/>
<wire from="(360,250)" to="(380,250)"/>
<wire from="(380,200)" to="(380,230)"/>
<wire from="(380,270)" to="(380,280)"/>
<wire from="(380,290)" to="(380,300)"/>
<wire from="(600,230)" to="(730,230)"/>
<wire from="(600,250)" to="(750,250)"/>
<wire from="(600,270)" to="(670,270)"/>
<wire from="(600,290)" to="(630,290)"/>
<wire from="(630,290)" to="(630,320)"/>
<wire from="(670,270)" to="(670,350)"/>
<wire from="(730,230)" to="(730,480)"/>
<wire from="(730,480)" to="(740,480)"/>
<wire from="(760,440)" to="(790,440)"/>
<wire from="(760,450)" to="(790,450)"/>
<wire from="(760,460)" to="(790,460)"/>
<wire from="(760,470)" to="(790,470)"/>
<wire from="(770,210)" to="(800,210)"/>
<wire from="(770,220)" to="(800,220)"/>
<wire from="(770,230)" to="(800,230)"/>
<wire from="(770,240)" to="(800,240)"/>
<wire from="(780,480)" to="(780,490)"/>
<wire from="(780,480)" to="(790,480)"/>
<wire from="(780,490)" to="(780,500)"/>
<wire from="(780,490)" to="(790,490)"/>
<wire from="(780,500)" to="(780,510)"/>
<wire from="(780,500)" to="(790,500)"/>
<wire from="(780,510)" to="(780,520)"/>
<wire from="(780,510)" to="(790,510)"/>
<wire from="(780,520)" to="(780,530)"/>
<wire from="(780,520)" to="(790,520)"/>
<wire from="(790,250)" to="(790,260)"/>
<wire from="(790,250)" to="(800,250)"/>
<wire from="(790,260)" to="(790,270)"/>
<wire from="(790,260)" to="(800,260)"/>
<wire from="(790,270)" to="(790,280)"/>
<wire from="(790,270)" to="(800,270)"/>
<wire from="(790,280)" to="(790,290)"/>
<wire from="(790,280)" to="(800,280)"/>
<wire from="(790,290)" to="(790,300)"/>
<wire from="(790,290)" to="(800,290)"/>
<wire from="(810,420)" to="(810,430)"/>
<wire from="(810,420)" to="(840,420)"/>
<wire from="(820,190)" to="(820,200)"/>
<wire from="(820,190)" to="(850,190)"/>
<wire from="(870,370)" to="(870,400)"/>
<wire from="(880,140)" to="(880,170)"/>
<wire from="(930,370)" to="(930,400)"/>
<wire from="(940,140)" to="(940,170)"/>
<wire from="(990,370)" to="(990,400)"/>
</circuit>
</project>

3135
logisim/!OLDhalfsubraction.circ Normal file
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File diff suppressed because it is too large Load Diff

673
logisim/alu.circ Normal file
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@ -0,0 +1,673 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.9.0" version="1.0">
This file is intended to be loaded by Logisim-evolution v3.9.0(https://github.com/logisim-evolution/).
<lib desc="#Wiring" name="0">
<tool name="Splitter">
<a name="facing" val="west"/>
</tool>
<tool name="Pin">
<a name="appearance" val="classic"/>
</tool>
<tool name="Power">
<a name="facing" val="west"/>
</tool>
</lib>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4"/>
<lib desc="#I/O" name="5"/>
<lib desc="#TTL" name="6">
<tool name="7432">
<a name="facing" val="south"/>
</tool>
</lib>
<lib desc="#TCL" name="7"/>
<lib desc="#Base" name="8"/>
<lib desc="#BFH-Praktika" name="9"/>
<lib desc="#Input/Output-Extra" name="10"/>
<lib desc="#Soc" name="11"/>
<lib desc="file#arithmeticunit.circ" name="12"/>
<lib desc="file#multiplier4.circ" name="13">
<tool name="bit4multiplier">
<a name="facing" val="south"/>
</tool>
</lib>
<main name="alu"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Poke Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Wiring Tool"/>
<tool lib="8" name="Text Tool"/>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
</tool>
<sep/>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
<tool lib="1" name="XOR Gate"/>
<tool lib="1" name="NAND Gate"/>
<tool lib="1" name="NOR Gate"/>
<sep/>
<tool lib="4" name="D Flip-Flop"/>
<tool lib="4" name="Register"/>
</toolbar>
<circuit name="alu">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="alu"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
<comp lib="0" loc="(1110,1150)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(2090,2170)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="8"/>
<a name="incoming" val="8"/>
</comp>
<comp lib="0" loc="(2110,2070)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="Y"/>
<a name="output" val="true"/>
<a name="width" val="8"/>
</comp>
<comp lib="0" loc="(320,90)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="opC"/>
<a name="width" val="3"/>
</comp>
<comp lib="0" loc="(360,1250)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="3"/>
<a name="incoming" val="3"/>
</comp>
<comp lib="0" loc="(360,90)" name="Splitter">
<a name="fanout" val="3"/>
<a name="incoming" val="3"/>
</comp>
<comp lib="0" loc="(430,1630)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="8"/>
<a name="incoming" val="8"/>
</comp>
<comp lib="0" loc="(430,510)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="Cin"/>
</comp>
<comp lib="0" loc="(470,460)" name="Splitter"/>
<comp lib="0" loc="(650,50)" name="Splitter">
<a name="facing" val="south"/>
<a name="fanout" val="8"/>
<a name="incoming" val="8"/>
</comp>
<comp lib="0" loc="(710,530)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="overflow"/>
<a name="output" val="true"/>
</comp>
<comp lib="0" loc="(710,560)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="Cout"/>
<a name="output" val="true"/>
</comp>
<comp lib="0" loc="(770,490)" name="Splitter">
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(780,1560)" name="Splitter">
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(790,840)" name="Splitter">
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(80,530)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="A"/>
<a name="width" val="4"/>
</comp>
<comp lib="0" loc="(80,560)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="B"/>
<a name="width" val="4"/>
</comp>
<comp lib="0" loc="(840,1200)" name="Splitter">
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="12" loc="(630,50)" name="OpCode"/>
<comp lib="12" loc="(690,490)" name="arithmeticUnit"/>
<comp lib="12" loc="(700,1250)" name="logic"/>
<comp lib="13" loc="(430,1610)" name="bit4multiplier">
<a name="facing" val="south"/>
</comp>
<comp lib="6" loc="(1140,660)" name="7432"/>
<comp lib="6" loc="(1420,670)" name="7432"/>
<comp lib="6" loc="(150,1800)" name="7408"/>
<comp lib="6" loc="(160,2080)" name="7408"/>
<comp lib="6" loc="(1790,1950)" name="7432">
<a name="facing" val="south"/>
</comp>
<comp lib="6" loc="(830,540)" name="7408"/>
<comp lib="6" loc="(840,830)" name="7408"/>
<comp lib="6" loc="(880,1520)" name="7432">
<a name="facing" val="north"/>
</comp>
<comp lib="6" loc="(970,1230)" name="7432">
<a name="facing" val="north"/>
</comp>
<comp lib="8" loc="(1010,815)" name="Text">
<a name="text" val="sub"/>
</comp>
<comp lib="8" loc="(1040,1740)" name="Text">
<a name="text" val="0"/>
</comp>
<comp lib="8" loc="(1055,1530)" name="Text">
<a name="text" val="2"/>
</comp>
<comp lib="8" loc="(1150,1120)" name="Text">
<a name="text" val="3"/>
</comp>
<comp lib="8" loc="(1195,1260)" name="Text">
<a name="text" val="2"/>
</comp>
<comp lib="8" loc="(1240,1560)" name="Text">
<a name="text" val="3"/>
</comp>
<comp lib="8" loc="(1290,510)" name="Text">
<a name="text" val="0"/>
</comp>
<comp lib="8" loc="(1300,550)" name="Text">
<a name="text" val="1"/>
</comp>
<comp lib="8" loc="(1355,775)" name="Text">
<a name="text" val="3"/>
</comp>
<comp lib="8" loc="(1360,1380)" name="Text">
<a name="text" val="0"/>
</comp>
<comp lib="8" loc="(1365,835)" name="Text">
<a name="text" val="2"/>
</comp>
<comp lib="8" loc="(1420,1665)" name="Text">
<a name="text" val="1"/>
</comp>
<comp lib="8" loc="(1420,1710)" name="Text">
<a name="text" val="2"/>
</comp>
<comp lib="8" loc="(1420,1760)" name="Text">
<a name="text" val="3"/>
</comp>
<comp lib="8" loc="(1695,1905)" name="Text">
<a name="text" val="0"/>
</comp>
<comp lib="8" loc="(1775,1920)" name="Text">
<a name="text" val="1"/>
</comp>
<comp lib="8" loc="(1800,1915)" name="Text">
<a name="text" val="2"/>
</comp>
<comp lib="8" loc="(1855,1915)" name="Text">
<a name="text" val="3"/>
</comp>
<comp lib="8" loc="(285,2210)" name="Text">
<a name="text" val="6"/>
</comp>
<comp lib="8" loc="(355,1690)" name="Text">
<a name="text" val="0"/>
</comp>
<comp lib="8" loc="(390,1765)" name="Text">
<a name="text" val="1"/>
</comp>
<comp lib="8" loc="(465,2020)" name="Text">
<a name="text" val="4"/>
</comp>
<comp lib="8" loc="(465,2035)" name="Text">
<a name="text" val="5"/>
</comp>
<comp lib="8" loc="(475,2110)" name="Text">
<a name="text" val="7"/>
</comp>
<comp lib="8" loc="(480,1840)" name="Text">
<a name="text" val="3"/>
</comp>
<comp lib="8" loc="(510,1880)" name="Text">
<a name="text" val="2"/>
</comp>
<comp lib="8" loc="(700,1465)" name="Text">
<a name="text" val="1"/>
</comp>
<comp lib="8" loc="(845,1300)" name="Text">
<a name="text" val="1"/>
</comp>
<comp lib="8" loc="(870,1345)" name="Text">
<a name="text" val="0"/>
</comp>
<comp lib="8" loc="(870,690)" name="Text">
<a name="text" val="2"/>
</comp>
<comp lib="8" loc="(870,955)" name="Text">
<a name="text" val="2"/>
</comp>
<comp lib="8" loc="(880,300)" name="Text">
<a name="text" val="temp0"/>
</comp>
<comp lib="8" loc="(895,730)" name="Text">
<a name="text" val="0"/>
</comp>
<comp lib="8" loc="(905,1910)" name="Text">
<a name="text" val="2"/>
</comp>
<comp lib="8" loc="(930,1855)" name="Text">
<a name="text" val="3"/>
</comp>
<comp lib="8" loc="(935,1785)" name="Text">
<a name="text" val="1"/>
</comp>
<comp lib="8" loc="(950,715)" name="Text">
<a name="text" val="temp3"/>
</comp>
<comp lib="8" loc="(955,380)" name="Text">
<a name="text" val="temp1"/>
</comp>
<comp lib="8" loc="(975,930)" name="Text">
<a name="text" val="3"/>
</comp>
<comp lib="8" loc="(990,545)" name="Text">
<a name="text" val="add"/>
</comp>
<comp lib="8" loc="(995,750)" name="Text">
<a name="text" val="1"/>
</comp>
<wire from="(100,1700)" to="(100,2000)"/>
<wire from="(100,1700)" to="(180,1700)"/>
<wire from="(100,2000)" to="(190,2000)"/>
<wire from="(1000,1120)" to="(1140,1120)"/>
<wire from="(1000,1140)" to="(1020,1140)"/>
<wire from="(1000,1160)" to="(1030,1160)"/>
<wire from="(1000,1180)" to="(1010,1180)"/>
<wire from="(1000,1200)" to="(1040,1200)"/>
<wire from="(1000,1220)" to="(1000,1250)"/>
<wire from="(1010,1180)" to="(1010,1250)"/>
<wire from="(1010,1250)" to="(1180,1250)"/>
<wire from="(1020,1010)" to="(1020,1140)"/>
<wire from="(1020,480)" to="(1020,590)"/>
<wire from="(1030,1160)" to="(1030,1190)"/>
<wire from="(1030,1190)" to="(1090,1190)"/>
<wire from="(1030,1750)" to="(1030,2020)"/>
<wire from="(1030,2020)" to="(1760,2020)"/>
<wire from="(1040,1180)" to="(1040,1200)"/>
<wire from="(1040,1180)" to="(1090,1180)"/>
<wire from="(1040,1470)" to="(1040,1710)"/>
<wire from="(1040,1710)" to="(1450,1710)"/>
<wire from="(1050,1050)" to="(1050,1160)"/>
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<wire from="(1050,1170)" to="(1090,1170)"/>
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<wire from="(1080,590)" to="(1190,590)"/>
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<wire from="(1690,2060)" to="(1760,2060)"/>
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<wire from="(170,2110)" to="(170,2150)"/>
<wire from="(170,2150)" to="(250,2150)"/>
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<wire from="(180,360)" to="(710,360)"/>
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<wire from="(1820,2020)" to="(1890,2020)"/>
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<wire from="(190,2140)" to="(590,2140)"/>
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<wire from="(390,1670)" to="(390,1850)"/>
<wire from="(390,1670)" to="(410,1670)"/>
<wire from="(390,550)" to="(390,1290)"/>
<wire from="(390,550)" to="(470,550)"/>
<wire from="(400,1270)" to="(430,1270)"/>
<wire from="(400,1290)" to="(400,1390)"/>
<wire from="(400,1290)" to="(480,1290)"/>
<wire from="(400,1390)" to="(410,1390)"/>
<wire from="(400,530)" to="(400,1270)"/>
<wire from="(400,530)" to="(470,530)"/>
<wire from="(410,1680)" to="(550,1680)"/>
<wire from="(410,1690)" to="(540,1690)"/>
<wire from="(410,1700)" to="(590,1700)"/>
<wire from="(410,1710)" to="(580,1710)"/>
<wire from="(430,1270)" to="(430,1390)"/>
<wire from="(430,1270)" to="(480,1270)"/>
<wire from="(430,1390)" to="(430,1400)"/>
<wire from="(430,1610)" to="(430,1630)"/>
<wire from="(430,510)" to="(470,510)"/>
<wire from="(470,460)" to="(470,490)"/>
<wire from="(480,1270)" to="(490,1270)"/>
<wire from="(480,2120)" to="(480,2320)"/>
<wire from="(480,2320)" to="(1970,2320)"/>
<wire from="(490,440)" to="(730,440)"/>
<wire from="(490,450)" to="(720,450)"/>
<wire from="(540,1690)" to="(540,1980)"/>
<wire from="(550,1680)" to="(550,1940)"/>
<wire from="(580,1710)" to="(580,2130)"/>
<wire from="(590,1700)" to="(590,2140)"/>
<wire from="(630,50)" to="(650,50)"/>
<wire from="(670,70)" to="(670,410)"/>
<wire from="(680,70)" to="(680,420)"/>
<wire from="(690,490)" to="(770,490)"/>
<wire from="(690,510)" to="(780,510)"/>
<wire from="(690,530)" to="(710,530)"/>
<wire from="(690,550)" to="(700,550)"/>
<wire from="(690,70)" to="(690,430)"/>
<wire from="(700,1250)" to="(840,1250)"/>
<wire from="(700,1270)" to="(1130,1270)"/>
<wire from="(700,1290)" to="(760,1290)"/>
<wire from="(700,550)" to="(700,560)"/>
<wire from="(700,560)" to="(710,560)"/>
<wire from="(710,70)" to="(710,360)"/>
<wire from="(720,1450)" to="(720,1670)"/>
<wire from="(720,1450)" to="(850,1450)"/>
<wire from="(720,1670)" to="(1640,1670)"/>
<wire from="(720,350)" to="(720,450)"/>
<wire from="(720,350)" to="(760,350)"/>
<wire from="(720,70)" to="(720,350)"/>
<wire from="(730,400)" to="(730,440)"/>
<wire from="(730,400)" to="(880,400)"/>
<wire from="(730,70)" to="(730,400)"/>
<wire from="(760,1290)" to="(760,1560)"/>
<wire from="(760,1560)" to="(780,1560)"/>
<wire from="(760,350)" to="(760,730)"/>
<wire from="(760,730)" to="(760,900)"/>
<wire from="(760,730)" to="(890,730)"/>
<wire from="(760,900)" to="(780,900)"/>
<wire from="(780,510)" to="(780,790)"/>
<wire from="(780,790)" to="(790,790)"/>
<wire from="(780,900)" to="(780,930)"/>
<wire from="(780,900)" to="(870,900)"/>
<wire from="(780,930)" to="(930,930)"/>
<wire from="(790,1350)" to="(790,1430)"/>
<wire from="(790,1350)" to="(900,1350)"/>
<wire from="(790,1430)" to="(850,1430)"/>
<wire from="(790,450)" to="(860,450)"/>
<wire from="(790,460)" to="(920,460)"/>
<wire from="(790,470)" to="(820,470)"/>
<wire from="(790,480)" to="(790,610)"/>
<wire from="(790,610)" to="(900,610)"/>
<wire from="(790,790)" to="(790,840)"/>
<wire from="(80,530)" to="(400,530)"/>
<wire from="(80,550)" to="(390,550)"/>
<wire from="(80,550)" to="(80,560)"/>
<wire from="(800,1410)" to="(800,1520)"/>
<wire from="(800,1410)" to="(850,1410)"/>
<wire from="(800,1530)" to="(830,1530)"/>
<wire from="(800,1540)" to="(940,1540)"/>
<wire from="(800,1550)" to="(990,1550)"/>
<wire from="(810,770)" to="(810,800)"/>
<wire from="(810,770)" to="(870,770)"/>
<wire from="(810,810)" to="(830,810)"/>
<wire from="(810,820)" to="(830,820)"/>
<wire from="(810,830)" to="(810,910)"/>
<wire from="(810,910)" to="(910,910)"/>
<wire from="(820,1010)" to="(1020,1010)"/>
<wire from="(820,1010)" to="(820,1210)"/>
<wire from="(820,1210)" to="(860,1210)"/>
<wire from="(820,1300)" to="(820,1470)"/>
<wire from="(820,1300)" to="(880,1300)"/>
<wire from="(820,1470)" to="(850,1470)"/>
<wire from="(820,470)" to="(820,590)"/>
<wire from="(820,590)" to="(840,590)"/>
<wire from="(830,1490)" to="(830,1530)"/>
<wire from="(830,1490)" to="(850,1490)"/>
<wire from="(830,760)" to="(830,810)"/>
<wire from="(830,760)" to="(930,760)"/>
<wire from="(830,820)" to="(830,880)"/>
<wire from="(830,880)" to="(850,880)"/>
<wire from="(840,1200)" to="(840,1250)"/>
<wire from="(840,1360)" to="(1400,1360)"/>
<wire from="(840,1360)" to="(840,1390)"/>
<wire from="(840,1390)" to="(850,1390)"/>
<wire from="(840,570)" to="(840,590)"/>
<wire from="(850,860)" to="(850,880)"/>
<wire from="(860,1120)" to="(860,1160)"/>
<wire from="(860,1120)" to="(940,1120)"/>
<wire from="(860,1170)" to="(920,1170)"/>
<wire from="(860,1180)" to="(890,1180)"/>
<wire from="(860,1190)" to="(860,1210)"/>
<wire from="(860,450)" to="(860,510)"/>
<wire from="(860,570)" to="(860,630)"/>
<wire from="(860,630)" to="(980,630)"/>
<wire from="(870,770)" to="(870,800)"/>
<wire from="(870,860)" to="(870,900)"/>
<wire from="(880,1160)" to="(880,1300)"/>
<wire from="(880,1160)" to="(940,1160)"/>
<wire from="(880,400)" to="(880,440)"/>
<wire from="(880,440)" to="(880,510)"/>
<wire from="(880,440)" to="(940,440)"/>
<wire from="(880,570)" to="(880,690)"/>
<wire from="(880,690)" to="(1150,690)"/>
<wire from="(890,1180)" to="(890,1250)"/>
<wire from="(890,1250)" to="(1000,1250)"/>
<wire from="(890,730)" to="(890,750)"/>
<wire from="(890,750)" to="(890,800)"/>
<wire from="(890,750)" to="(950,750)"/>
<wire from="(890,860)" to="(890,950)"/>
<wire from="(890,950)" to="(1170,950)"/>
<wire from="(900,1100)" to="(900,1350)"/>
<wire from="(900,1100)" to="(940,1100)"/>
<wire from="(900,2030)" to="(900,2310)"/>
<wire from="(900,2310)" to="(1950,2310)"/>
<wire from="(900,340)" to="(1170,340)"/>
<wire from="(900,340)" to="(900,510)"/>
<wire from="(900,570)" to="(900,610)"/>
<wire from="(910,1200)" to="(910,1240)"/>
<wire from="(910,1200)" to="(940,1200)"/>
<wire from="(910,1240)" to="(1050,1240)"/>
<wire from="(910,1410)" to="(1220,1410)"/>
<wire from="(910,1430)" to="(1140,1430)"/>
<wire from="(910,1450)" to="(990,1450)"/>
<wire from="(910,1470)" to="(1040,1470)"/>
<wire from="(910,1490)" to="(1180,1490)"/>
<wire from="(910,1510)" to="(940,1510)"/>
<wire from="(910,650)" to="(1080,650)"/>
<wire from="(910,650)" to="(910,800)"/>
<wire from="(910,860)" to="(910,910)"/>
<wire from="(920,1050)" to="(1050,1050)"/>
<wire from="(920,1050)" to="(920,1140)"/>
<wire from="(920,1140)" to="(940,1140)"/>
<wire from="(920,1170)" to="(920,1180)"/>
<wire from="(920,1180)" to="(940,1180)"/>
<wire from="(920,460)" to="(920,510)"/>
<wire from="(920,570)" to="(920,590)"/>
<wire from="(920,590)" to="(980,590)"/>
<wire from="(930,2020)" to="(930,2290)"/>
<wire from="(930,2290)" to="(1940,2290)"/>
<wire from="(930,760)" to="(930,800)"/>
<wire from="(930,860)" to="(930,930)"/>
<wire from="(940,1510)" to="(940,1540)"/>
<wire from="(940,1890)" to="(940,2270)"/>
<wire from="(940,2270)" to="(1920,2270)"/>
<wire from="(940,440)" to="(940,480)"/>
<wire from="(940,480)" to="(1020,480)"/>
<wire from="(940,480)" to="(940,510)"/>
<wire from="(940,570)" to="(940,730)"/>
<wire from="(940,730)" to="(1230,730)"/>
<wire from="(950,750)" to="(950,800)"/>
<wire from="(950,860)" to="(950,940)"/>
<wire from="(950,940)" to="(1210,940)"/>
<wire from="(960,1840)" to="(960,2220)"/>
<wire from="(960,2220)" to="(1910,2220)"/>
<wire from="(960,390)" to="(1230,390)"/>
<wire from="(960,390)" to="(960,510)"/>
<wire from="(970,1760)" to="(970,1980)"/>
<wire from="(970,1980)" to="(1760,1980)"/>
<wire from="(970,740)" to="(1310,740)"/>
<wire from="(970,740)" to="(970,800)"/>
<wire from="(980,590)" to="(1020,590)"/>
<wire from="(980,590)" to="(980,630)"/>
<wire from="(990,1450)" to="(990,1550)"/>
</circuit>
</project>

276
logisim/alutest.circ Normal file
View File

@ -0,0 +1,276 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.9.0" version="1.0">
This file is intended to be loaded by Logisim-evolution v3.9.0(https://github.com/logisim-evolution/).
<lib desc="#Wiring" name="0">
<tool name="Splitter">
<a name="facing" val="west"/>
</tool>
<tool name="Pin">
<a name="appearance" val="classic"/>
</tool>
<tool name="Power">
<a name="facing" val="west"/>
</tool>
</lib>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4"/>
<lib desc="#I/O" name="5"/>
<lib desc="#TTL" name="6">
<tool name="7432">
<a name="facing" val="south"/>
</tool>
</lib>
<lib desc="#TCL" name="7"/>
<lib desc="#Base" name="8"/>
<lib desc="#BFH-Praktika" name="9"/>
<lib desc="#Input/Output-Extra" name="10"/>
<lib desc="#Soc" name="11"/>
<lib desc="file#alu.circ" name="12"/>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Poke Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Wiring Tool"/>
<tool lib="8" name="Text Tool"/>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
</tool>
<sep/>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
<tool lib="1" name="XOR Gate"/>
<tool lib="1" name="NAND Gate"/>
<tool lib="1" name="NOR Gate"/>
<sep/>
<tool lib="4" name="D Flip-Flop"/>
<tool lib="4" name="Register"/>
</toolbar>
<circuit name="main">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="main"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
<comp lib="0" loc="(100,630)" name="Splitter">
<a name="facing" val="south"/>
<a name="fanout" val="3"/>
<a name="incoming" val="3"/>
</comp>
<comp lib="0" loc="(120,530)" name="Splitter">
<a name="facing" val="north"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(140,560)" name="Pin">
<a name="appearance" val="classic"/>
</comp>
<comp lib="0" loc="(190,510)" name="Splitter">
<a name="facing" val="north"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(220,370)" name="Ground"/>
<comp lib="0" loc="(240,260)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="9"/>
<a name="incoming" val="9"/>
</comp>
<comp lib="0" loc="(450,450)" name="Ground"/>
<comp lib="0" loc="(470,340)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="9"/>
<a name="incoming" val="9"/>
</comp>
<comp lib="0" loc="(540,650)" name="Splitter">
<a name="fanout" val="8"/>
<a name="incoming" val="8"/>
</comp>
<comp lib="0" loc="(580,670)" name="Ground"/>
<comp lib="0" loc="(600,560)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="9"/>
<a name="incoming" val="9"/>
</comp>
<comp lib="12" loc="(450,610)" name="alu"/>
<comp lib="5" loc="(100,670)" name="DipSwitch">
<a name="number" val="3"/>
</comp>
<comp lib="5" loc="(180,160)" name="DipSwitch">
<a name="facing" val="south"/>
</comp>
<comp lib="5" loc="(280,130)" name="7-Segment Display"/>
<comp lib="5" loc="(340,130)" name="7-Segment Display"/>
<comp lib="5" loc="(400,130)" name="7-Segment Display"/>
<comp lib="5" loc="(470,560)" name="LED">
<a name="facing" val="south"/>
</comp>
<comp lib="5" loc="(500,560)" name="LED">
<a name="facing" val="south"/>
</comp>
<comp lib="5" loc="(510,210)" name="7-Segment Display"/>
<comp lib="5" loc="(570,210)" name="7-Segment Display"/>
<comp lib="5" loc="(630,210)" name="7-Segment Display"/>
<comp lib="5" loc="(640,430)" name="7-Segment Display"/>
<comp lib="5" loc="(700,430)" name="7-Segment Display"/>
<comp lib="5" loc="(760,430)" name="7-Segment Display"/>
<comp lib="8" loc="(115,860)" name="Text">
<a name="text" val="101 or"/>
</comp>
<comp lib="8" loc="(115,890)" name="Text">
<a name="text" val="110 xor"/>
</comp>
<comp lib="8" loc="(120,745)" name="Text">
<a name="text" val="000 add"/>
</comp>
<comp lib="8" loc="(120,775)" name="Text">
<a name="text" val="001 sub"/>
</comp>
<comp lib="8" loc="(120,800)" name="Text">
<a name="text" val="010 mult"/>
</comp>
<comp lib="8" loc="(120,830)" name="Text">
<a name="text" val="100 and"/>
</comp>
<comp lib="8" loc="(320,85)" name="Text">
<a name="text" val="A"/>
</comp>
<comp lib="8" loc="(560,170)" name="Text">
<a name="text" val="B"/>
</comp>
<comp lib="9" loc="(280,130)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(290,260)" name="Binary_to_BCD_converter"/>
<comp lib="9" loc="(340,130)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(400,130)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(510,210)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(520,340)" name="Binary_to_BCD_converter"/>
<comp lib="9" loc="(570,210)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(630,210)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(640,430)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(650,560)" name="Binary_to_BCD_converter"/>
<comp lib="9" loc="(700,430)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(760,430)" name="BCD_to_7_Segment_decoder"/>
<wire from="(100,340)" to="(100,420)"/>
<wire from="(100,420)" to="(100,510)"/>
<wire from="(100,420)" to="(360,420)"/>
<wire from="(100,610)" to="(100,630)"/>
<wire from="(100,610)" to="(230,610)"/>
<wire from="(110,160)" to="(110,190)"/>
<wire from="(110,510)" to="(140,510)"/>
<wire from="(110,650)" to="(110,670)"/>
<wire from="(120,160)" to="(120,200)"/>
<wire from="(120,530)" to="(140,530)"/>
<wire from="(120,650)" to="(120,670)"/>
<wire from="(130,160)" to="(130,360)"/>
<wire from="(130,360)" to="(140,360)"/>
<wire from="(130,650)" to="(130,670)"/>
<wire from="(140,160)" to="(140,300)"/>
<wire from="(140,300)" to="(140,350)"/>
<wire from="(140,300)" to="(220,300)"/>
<wire from="(140,350)" to="(150,350)"/>
<wire from="(140,360)" to="(140,400)"/>
<wire from="(140,400)" to="(140,510)"/>
<wire from="(140,400)" to="(350,400)"/>
<wire from="(140,530)" to="(140,540)"/>
<wire from="(140,540)" to="(180,540)"/>
<wire from="(140,560)" to="(150,560)"/>
<wire from="(150,160)" to="(150,290)"/>
<wire from="(150,290)" to="(150,340)"/>
<wire from="(150,290)" to="(220,290)"/>
<wire from="(150,340)" to="(160,340)"/>
<wire from="(150,350)" to="(150,490)"/>
<wire from="(150,560)" to="(150,630)"/>
<wire from="(150,630)" to="(230,630)"/>
<wire from="(160,160)" to="(160,280)"/>
<wire from="(160,280)" to="(160,330)"/>
<wire from="(160,280)" to="(220,280)"/>
<wire from="(160,330)" to="(170,330)"/>
<wire from="(160,340)" to="(160,490)"/>
<wire from="(170,160)" to="(170,270)"/>
<wire from="(170,270)" to="(170,320)"/>
<wire from="(170,270)" to="(220,270)"/>
<wire from="(170,320)" to="(180,320)"/>
<wire from="(170,330)" to="(170,490)"/>
<wire from="(180,320)" to="(180,490)"/>
<wire from="(180,540)" to="(180,670)"/>
<wire from="(180,670)" to="(230,670)"/>
<wire from="(190,510)" to="(190,520)"/>
<wire from="(190,520)" to="(210,520)"/>
<wire from="(210,520)" to="(210,650)"/>
<wire from="(210,650)" to="(230,650)"/>
<wire from="(220,310)" to="(220,320)"/>
<wire from="(220,320)" to="(220,330)"/>
<wire from="(220,330)" to="(220,340)"/>
<wire from="(220,340)" to="(220,350)"/>
<wire from="(220,350)" to="(220,370)"/>
<wire from="(240,260)" to="(260,260)"/>
<wire from="(290,210)" to="(290,240)"/>
<wire from="(350,210)" to="(350,240)"/>
<wire from="(350,350)" to="(350,400)"/>
<wire from="(350,350)" to="(450,350)"/>
<wire from="(360,360)" to="(360,420)"/>
<wire from="(360,360)" to="(450,360)"/>
<wire from="(370,370)" to="(370,440)"/>
<wire from="(370,370)" to="(450,370)"/>
<wire from="(380,380)" to="(380,450)"/>
<wire from="(380,380)" to="(450,380)"/>
<wire from="(410,210)" to="(410,240)"/>
<wire from="(450,390)" to="(450,400)"/>
<wire from="(450,400)" to="(450,410)"/>
<wire from="(450,410)" to="(450,420)"/>
<wire from="(450,420)" to="(450,430)"/>
<wire from="(450,430)" to="(450,450)"/>
<wire from="(450,610)" to="(470,610)"/>
<wire from="(450,630)" to="(500,630)"/>
<wire from="(450,650)" to="(540,650)"/>
<wire from="(470,340)" to="(490,340)"/>
<wire from="(470,560)" to="(470,610)"/>
<wire from="(500,560)" to="(500,630)"/>
<wire from="(520,290)" to="(520,320)"/>
<wire from="(560,570)" to="(580,570)"/>
<wire from="(560,580)" to="(580,580)"/>
<wire from="(560,590)" to="(580,590)"/>
<wire from="(560,600)" to="(580,600)"/>
<wire from="(560,610)" to="(580,610)"/>
<wire from="(560,620)" to="(580,620)"/>
<wire from="(560,630)" to="(580,630)"/>
<wire from="(560,640)" to="(580,640)"/>
<wire from="(580,290)" to="(580,320)"/>
<wire from="(580,650)" to="(580,670)"/>
<wire from="(600,560)" to="(620,560)"/>
<wire from="(640,290)" to="(640,320)"/>
<wire from="(650,510)" to="(650,540)"/>
<wire from="(70,160)" to="(100,160)"/>
<wire from="(70,160)" to="(70,360)"/>
<wire from="(70,360)" to="(80,360)"/>
<wire from="(710,510)" to="(710,540)"/>
<wire from="(770,510)" to="(770,540)"/>
<wire from="(80,190)" to="(110,190)"/>
<wire from="(80,190)" to="(80,350)"/>
<wire from="(80,350)" to="(90,350)"/>
<wire from="(80,360)" to="(80,450)"/>
<wire from="(80,450)" to="(380,450)"/>
<wire from="(80,450)" to="(80,510)"/>
<wire from="(90,200)" to="(120,200)"/>
<wire from="(90,200)" to="(90,340)"/>
<wire from="(90,340)" to="(100,340)"/>
<wire from="(90,350)" to="(90,440)"/>
<wire from="(90,440)" to="(370,440)"/>
<wire from="(90,440)" to="(90,510)"/>
</circuit>
</project>

276
logisim/alutest3.circ Normal file
View File

@ -0,0 +1,276 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.9.0" version="1.0">
This file is intended to be loaded by Logisim-evolution v3.9.0(https://github.com/logisim-evolution/).
<lib desc="#Wiring" name="0">
<tool name="Splitter">
<a name="facing" val="west"/>
</tool>
<tool name="Pin">
<a name="appearance" val="classic"/>
</tool>
<tool name="Power">
<a name="facing" val="west"/>
</tool>
</lib>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4"/>
<lib desc="#I/O" name="5"/>
<lib desc="#TTL" name="6">
<tool name="7432">
<a name="facing" val="south"/>
</tool>
</lib>
<lib desc="#TCL" name="7"/>
<lib desc="#Base" name="8"/>
<lib desc="#BFH-Praktika" name="9"/>
<lib desc="#Input/Output-Extra" name="10"/>
<lib desc="#Soc" name="11"/>
<lib desc="file#alu2.circ" name="12"/>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Poke Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Wiring Tool"/>
<tool lib="8" name="Text Tool"/>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
</tool>
<sep/>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
<tool lib="1" name="XOR Gate"/>
<tool lib="1" name="NAND Gate"/>
<tool lib="1" name="NOR Gate"/>
<sep/>
<tool lib="4" name="D Flip-Flop"/>
<tool lib="4" name="Register"/>
</toolbar>
<circuit name="main">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="main"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
<comp lib="0" loc="(100,630)" name="Splitter">
<a name="facing" val="south"/>
<a name="fanout" val="3"/>
<a name="incoming" val="3"/>
</comp>
<comp lib="0" loc="(120,530)" name="Splitter">
<a name="facing" val="north"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(140,560)" name="Pin">
<a name="appearance" val="classic"/>
</comp>
<comp lib="0" loc="(190,510)" name="Splitter">
<a name="facing" val="north"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(220,370)" name="Ground"/>
<comp lib="0" loc="(240,260)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="9"/>
<a name="incoming" val="9"/>
</comp>
<comp lib="0" loc="(450,450)" name="Ground"/>
<comp lib="0" loc="(470,340)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="9"/>
<a name="incoming" val="9"/>
</comp>
<comp lib="0" loc="(540,650)" name="Splitter">
<a name="fanout" val="8"/>
<a name="incoming" val="8"/>
</comp>
<comp lib="0" loc="(580,670)" name="Ground"/>
<comp lib="0" loc="(600,560)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="9"/>
<a name="incoming" val="9"/>
</comp>
<comp lib="12" loc="(450,610)" name="alu"/>
<comp lib="5" loc="(100,670)" name="DipSwitch">
<a name="number" val="3"/>
</comp>
<comp lib="5" loc="(180,160)" name="DipSwitch">
<a name="facing" val="south"/>
</comp>
<comp lib="5" loc="(280,130)" name="7-Segment Display"/>
<comp lib="5" loc="(340,130)" name="7-Segment Display"/>
<comp lib="5" loc="(400,130)" name="7-Segment Display"/>
<comp lib="5" loc="(470,560)" name="LED">
<a name="facing" val="south"/>
</comp>
<comp lib="5" loc="(500,560)" name="LED">
<a name="facing" val="south"/>
</comp>
<comp lib="5" loc="(510,210)" name="7-Segment Display"/>
<comp lib="5" loc="(570,210)" name="7-Segment Display"/>
<comp lib="5" loc="(630,210)" name="7-Segment Display"/>
<comp lib="5" loc="(640,430)" name="7-Segment Display"/>
<comp lib="5" loc="(700,430)" name="7-Segment Display"/>
<comp lib="5" loc="(760,430)" name="7-Segment Display"/>
<comp lib="8" loc="(117,861)" name="Text">
<a name="text" val="101 or"/>
</comp>
<comp lib="8" loc="(119,890)" name="Text">
<a name="text" val="110 xor"/>
</comp>
<comp lib="8" loc="(120,834)" name="Text">
<a name="text" val="100 and"/>
</comp>
<comp lib="8" loc="(121,777)" name="Text">
<a name="text" val="001 sub"/>
</comp>
<comp lib="8" loc="(122,748)" name="Text">
<a name="text" val="000 add"/>
</comp>
<comp lib="8" loc="(124,804)" name="Text">
<a name="text" val="010 mult"/>
</comp>
<comp lib="8" loc="(324,88)" name="Text">
<a name="text" val="A"/>
</comp>
<comp lib="8" loc="(560,173)" name="Text">
<a name="text" val="B"/>
</comp>
<comp lib="9" loc="(280,130)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(290,260)" name="Binary_to_BCD_converter"/>
<comp lib="9" loc="(340,130)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(400,130)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(510,210)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(520,340)" name="Binary_to_BCD_converter"/>
<comp lib="9" loc="(570,210)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(630,210)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(640,430)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(650,560)" name="Binary_to_BCD_converter"/>
<comp lib="9" loc="(700,430)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(760,430)" name="BCD_to_7_Segment_decoder"/>
<wire from="(100,340)" to="(100,420)"/>
<wire from="(100,420)" to="(100,510)"/>
<wire from="(100,420)" to="(360,420)"/>
<wire from="(100,610)" to="(100,630)"/>
<wire from="(100,610)" to="(230,610)"/>
<wire from="(110,160)" to="(110,190)"/>
<wire from="(110,510)" to="(140,510)"/>
<wire from="(110,650)" to="(110,670)"/>
<wire from="(120,160)" to="(120,200)"/>
<wire from="(120,530)" to="(140,530)"/>
<wire from="(120,650)" to="(120,670)"/>
<wire from="(130,160)" to="(130,360)"/>
<wire from="(130,360)" to="(140,360)"/>
<wire from="(130,650)" to="(130,670)"/>
<wire from="(140,160)" to="(140,300)"/>
<wire from="(140,300)" to="(140,350)"/>
<wire from="(140,300)" to="(220,300)"/>
<wire from="(140,350)" to="(150,350)"/>
<wire from="(140,360)" to="(140,400)"/>
<wire from="(140,400)" to="(140,510)"/>
<wire from="(140,400)" to="(350,400)"/>
<wire from="(140,530)" to="(140,540)"/>
<wire from="(140,540)" to="(180,540)"/>
<wire from="(140,560)" to="(150,560)"/>
<wire from="(150,160)" to="(150,290)"/>
<wire from="(150,290)" to="(150,340)"/>
<wire from="(150,290)" to="(220,290)"/>
<wire from="(150,340)" to="(160,340)"/>
<wire from="(150,350)" to="(150,490)"/>
<wire from="(150,560)" to="(150,630)"/>
<wire from="(150,630)" to="(230,630)"/>
<wire from="(160,160)" to="(160,280)"/>
<wire from="(160,280)" to="(160,330)"/>
<wire from="(160,280)" to="(220,280)"/>
<wire from="(160,330)" to="(170,330)"/>
<wire from="(160,340)" to="(160,490)"/>
<wire from="(170,160)" to="(170,270)"/>
<wire from="(170,270)" to="(170,320)"/>
<wire from="(170,270)" to="(220,270)"/>
<wire from="(170,320)" to="(180,320)"/>
<wire from="(170,330)" to="(170,490)"/>
<wire from="(180,320)" to="(180,490)"/>
<wire from="(180,540)" to="(180,670)"/>
<wire from="(180,670)" to="(230,670)"/>
<wire from="(190,510)" to="(190,520)"/>
<wire from="(190,520)" to="(210,520)"/>
<wire from="(210,520)" to="(210,650)"/>
<wire from="(210,650)" to="(230,650)"/>
<wire from="(220,310)" to="(220,320)"/>
<wire from="(220,320)" to="(220,330)"/>
<wire from="(220,330)" to="(220,340)"/>
<wire from="(220,340)" to="(220,350)"/>
<wire from="(220,350)" to="(220,370)"/>
<wire from="(240,260)" to="(260,260)"/>
<wire from="(290,210)" to="(290,240)"/>
<wire from="(350,210)" to="(350,240)"/>
<wire from="(350,350)" to="(350,400)"/>
<wire from="(350,350)" to="(450,350)"/>
<wire from="(360,360)" to="(360,420)"/>
<wire from="(360,360)" to="(450,360)"/>
<wire from="(370,370)" to="(370,440)"/>
<wire from="(370,370)" to="(450,370)"/>
<wire from="(380,380)" to="(380,450)"/>
<wire from="(380,380)" to="(450,380)"/>
<wire from="(410,210)" to="(410,240)"/>
<wire from="(450,390)" to="(450,400)"/>
<wire from="(450,400)" to="(450,410)"/>
<wire from="(450,410)" to="(450,420)"/>
<wire from="(450,420)" to="(450,430)"/>
<wire from="(450,430)" to="(450,450)"/>
<wire from="(450,610)" to="(470,610)"/>
<wire from="(450,630)" to="(500,630)"/>
<wire from="(450,650)" to="(540,650)"/>
<wire from="(470,340)" to="(490,340)"/>
<wire from="(470,560)" to="(470,610)"/>
<wire from="(500,560)" to="(500,630)"/>
<wire from="(520,290)" to="(520,320)"/>
<wire from="(560,570)" to="(580,570)"/>
<wire from="(560,580)" to="(580,580)"/>
<wire from="(560,590)" to="(580,590)"/>
<wire from="(560,600)" to="(580,600)"/>
<wire from="(560,610)" to="(580,610)"/>
<wire from="(560,620)" to="(580,620)"/>
<wire from="(560,630)" to="(580,630)"/>
<wire from="(560,640)" to="(580,640)"/>
<wire from="(580,290)" to="(580,320)"/>
<wire from="(580,650)" to="(580,670)"/>
<wire from="(600,560)" to="(620,560)"/>
<wire from="(640,290)" to="(640,320)"/>
<wire from="(650,510)" to="(650,540)"/>
<wire from="(70,160)" to="(100,160)"/>
<wire from="(70,160)" to="(70,360)"/>
<wire from="(70,360)" to="(80,360)"/>
<wire from="(710,510)" to="(710,540)"/>
<wire from="(770,510)" to="(770,540)"/>
<wire from="(80,190)" to="(110,190)"/>
<wire from="(80,190)" to="(80,350)"/>
<wire from="(80,350)" to="(90,350)"/>
<wire from="(80,360)" to="(80,450)"/>
<wire from="(80,450)" to="(380,450)"/>
<wire from="(80,450)" to="(80,510)"/>
<wire from="(90,200)" to="(120,200)"/>
<wire from="(90,200)" to="(90,340)"/>
<wire from="(90,340)" to="(100,340)"/>
<wire from="(90,350)" to="(90,440)"/>
<wire from="(90,440)" to="(370,440)"/>
<wire from="(90,440)" to="(90,510)"/>
</circuit>
</project>

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logisim/arithmeticunit.circ Normal file
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logisim/autest.circ Normal file
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@ -0,0 +1,299 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.9.0" version="1.0">
This file is intended to be loaded by Logisim-evolution v3.9.0(https://github.com/logisim-evolution/).
<lib desc="#Wiring" name="0">
<tool name="Splitter">
<a name="facing" val="west"/>
</tool>
<tool name="Pin">
<a name="appearance" val="classic"/>
</tool>
<tool name="Power">
<a name="facing" val="west"/>
</tool>
</lib>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4"/>
<lib desc="#I/O" name="5"/>
<lib desc="#TTL" name="6">
<tool name="7432">
<a name="facing" val="south"/>
</tool>
</lib>
<lib desc="#TCL" name="7"/>
<lib desc="#Base" name="8"/>
<lib desc="#BFH-Praktika" name="9"/>
<lib desc="#Input/Output-Extra" name="10"/>
<lib desc="#Soc" name="11"/>
<lib desc="file#arithmeticunit.circ" name="12"/>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Poke Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Wiring Tool"/>
<tool lib="8" name="Text Tool"/>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
</tool>
<sep/>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
<tool lib="1" name="XOR Gate"/>
<tool lib="1" name="NAND Gate"/>
<tool lib="1" name="NOR Gate"/>
<sep/>
<tool lib="4" name="D Flip-Flop"/>
<tool lib="4" name="Register"/>
</toolbar>
<circuit name="main">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="main"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
<comp lib="0" loc="(100,680)" name="Splitter">
<a name="facing" val="south"/>
</comp>
<comp lib="0" loc="(120,580)" name="Splitter">
<a name="facing" val="north"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(140,610)" name="Pin">
<a name="appearance" val="classic"/>
</comp>
<comp lib="0" loc="(190,560)" name="Splitter">
<a name="facing" val="north"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(220,420)" name="Ground"/>
<comp lib="0" loc="(240,310)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="9"/>
<a name="incoming" val="9"/>
</comp>
<comp lib="0" loc="(450,500)" name="Ground"/>
<comp lib="0" loc="(470,390)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="9"/>
<a name="incoming" val="9"/>
</comp>
<comp lib="0" loc="(590,650)" name="Splitter">
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(630,710)" name="Ground"/>
<comp lib="0" loc="(650,600)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="9"/>
<a name="incoming" val="9"/>
</comp>
<comp lib="0" loc="(900,640)" name="Splitter">
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(940,700)" name="Ground"/>
<comp lib="0" loc="(960,590)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="9"/>
<a name="incoming" val="9"/>
</comp>
<comp lib="12" loc="(450,660)" name="arithmeticUnit"/>
<comp lib="5" loc="(100,700)" name="DipSwitch">
<a name="number" val="2"/>
</comp>
<comp lib="5" loc="(1000,460)" name="7-Segment Display"/>
<comp lib="5" loc="(1060,460)" name="7-Segment Display"/>
<comp lib="5" loc="(1120,460)" name="7-Segment Display"/>
<comp lib="5" loc="(180,210)" name="DipSwitch">
<a name="facing" val="south"/>
</comp>
<comp lib="5" loc="(280,180)" name="7-Segment Display"/>
<comp lib="5" loc="(340,180)" name="7-Segment Display"/>
<comp lib="5" loc="(400,180)" name="7-Segment Display"/>
<comp lib="5" loc="(460,840)" name="LED">
<a name="facing" val="north"/>
</comp>
<comp lib="5" loc="(490,840)" name="LED">
<a name="facing" val="north"/>
</comp>
<comp lib="5" loc="(510,260)" name="7-Segment Display"/>
<comp lib="5" loc="(570,260)" name="7-Segment Display"/>
<comp lib="5" loc="(630,260)" name="7-Segment Display"/>
<comp lib="5" loc="(690,470)" name="7-Segment Display"/>
<comp lib="5" loc="(750,470)" name="7-Segment Display"/>
<comp lib="5" loc="(810,470)" name="7-Segment Display"/>
<comp lib="8" loc="(108,789)" name="Text">
<a name="text" val="switch 1 sub"/>
</comp>
<comp lib="8" loc="(112,763)" name="Text">
<a name="text" val="switch 2 add"/>
</comp>
<comp lib="8" loc="(119,815)" name="Text">
<a name="text" val="decoded opcode"/>
</comp>
<comp lib="8" loc="(333,149)" name="Text">
<a name="text" val="A"/>
</comp>
<comp lib="8" loc="(560,220)" name="Text">
<a name="text" val="B"/>
</comp>
<comp lib="9" loc="(1000,460)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(1010,590)" name="Binary_to_BCD_converter"/>
<comp lib="9" loc="(1060,460)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(1120,460)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(280,180)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(290,310)" name="Binary_to_BCD_converter"/>
<comp lib="9" loc="(340,180)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(400,180)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(510,260)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(520,390)" name="Binary_to_BCD_converter"/>
<comp lib="9" loc="(570,260)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(630,260)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(690,470)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(700,600)" name="Binary_to_BCD_converter"/>
<comp lib="9" loc="(750,470)" name="BCD_to_7_Segment_decoder"/>
<comp lib="9" loc="(810,470)" name="BCD_to_7_Segment_decoder"/>
<wire from="(100,390)" to="(100,470)"/>
<wire from="(100,470)" to="(100,560)"/>
<wire from="(100,470)" to="(360,470)"/>
<wire from="(100,660)" to="(100,680)"/>
<wire from="(100,660)" to="(230,660)"/>
<wire from="(1010,540)" to="(1010,570)"/>
<wire from="(1070,540)" to="(1070,570)"/>
<wire from="(110,210)" to="(110,240)"/>
<wire from="(110,560)" to="(140,560)"/>
<wire from="(1130,540)" to="(1130,570)"/>
<wire from="(120,210)" to="(120,250)"/>
<wire from="(120,580)" to="(140,580)"/>
<wire from="(130,210)" to="(130,410)"/>
<wire from="(130,410)" to="(140,410)"/>
<wire from="(140,210)" to="(140,350)"/>
<wire from="(140,350)" to="(140,400)"/>
<wire from="(140,350)" to="(220,350)"/>
<wire from="(140,400)" to="(150,400)"/>
<wire from="(140,410)" to="(140,450)"/>
<wire from="(140,450)" to="(140,560)"/>
<wire from="(140,450)" to="(350,450)"/>
<wire from="(140,580)" to="(140,590)"/>
<wire from="(140,590)" to="(180,590)"/>
<wire from="(140,610)" to="(150,610)"/>
<wire from="(150,210)" to="(150,340)"/>
<wire from="(150,340)" to="(150,390)"/>
<wire from="(150,340)" to="(220,340)"/>
<wire from="(150,390)" to="(160,390)"/>
<wire from="(150,400)" to="(150,540)"/>
<wire from="(150,610)" to="(150,680)"/>
<wire from="(150,680)" to="(230,680)"/>
<wire from="(160,210)" to="(160,330)"/>
<wire from="(160,330)" to="(160,380)"/>
<wire from="(160,330)" to="(220,330)"/>
<wire from="(160,380)" to="(170,380)"/>
<wire from="(160,390)" to="(160,540)"/>
<wire from="(170,210)" to="(170,320)"/>
<wire from="(170,320)" to="(170,370)"/>
<wire from="(170,320)" to="(220,320)"/>
<wire from="(170,370)" to="(180,370)"/>
<wire from="(170,380)" to="(170,540)"/>
<wire from="(180,370)" to="(180,540)"/>
<wire from="(180,590)" to="(180,720)"/>
<wire from="(180,720)" to="(230,720)"/>
<wire from="(190,560)" to="(190,570)"/>
<wire from="(190,570)" to="(210,570)"/>
<wire from="(210,570)" to="(210,700)"/>
<wire from="(210,700)" to="(230,700)"/>
<wire from="(220,360)" to="(220,370)"/>
<wire from="(220,370)" to="(220,380)"/>
<wire from="(220,380)" to="(220,390)"/>
<wire from="(220,390)" to="(220,400)"/>
<wire from="(220,400)" to="(220,420)"/>
<wire from="(240,310)" to="(260,310)"/>
<wire from="(290,260)" to="(290,290)"/>
<wire from="(350,260)" to="(350,290)"/>
<wire from="(350,400)" to="(350,450)"/>
<wire from="(350,400)" to="(450,400)"/>
<wire from="(360,410)" to="(360,470)"/>
<wire from="(360,410)" to="(450,410)"/>
<wire from="(370,420)" to="(370,490)"/>
<wire from="(370,420)" to="(450,420)"/>
<wire from="(380,430)" to="(380,500)"/>
<wire from="(380,430)" to="(450,430)"/>
<wire from="(410,260)" to="(410,290)"/>
<wire from="(450,440)" to="(450,450)"/>
<wire from="(450,450)" to="(450,460)"/>
<wire from="(450,460)" to="(450,470)"/>
<wire from="(450,470)" to="(450,480)"/>
<wire from="(450,480)" to="(450,500)"/>
<wire from="(450,660)" to="(590,660)"/>
<wire from="(450,680)" to="(590,680)"/>
<wire from="(450,700)" to="(490,700)"/>
<wire from="(450,720)" to="(460,720)"/>
<wire from="(460,720)" to="(460,840)"/>
<wire from="(470,390)" to="(490,390)"/>
<wire from="(490,700)" to="(490,840)"/>
<wire from="(520,340)" to="(520,370)"/>
<wire from="(580,340)" to="(580,370)"/>
<wire from="(590,650)" to="(590,660)"/>
<wire from="(590,680)" to="(590,750)"/>
<wire from="(590,750)" to="(900,750)"/>
<wire from="(610,610)" to="(630,610)"/>
<wire from="(610,620)" to="(630,620)"/>
<wire from="(610,630)" to="(630,630)"/>
<wire from="(610,640)" to="(630,640)"/>
<wire from="(630,650)" to="(630,660)"/>
<wire from="(630,660)" to="(630,670)"/>
<wire from="(630,670)" to="(630,680)"/>
<wire from="(630,680)" to="(630,690)"/>
<wire from="(630,690)" to="(630,710)"/>
<wire from="(640,340)" to="(640,370)"/>
<wire from="(650,600)" to="(670,600)"/>
<wire from="(70,210)" to="(100,210)"/>
<wire from="(70,210)" to="(70,410)"/>
<wire from="(70,410)" to="(80,410)"/>
<wire from="(700,550)" to="(700,580)"/>
<wire from="(760,550)" to="(760,580)"/>
<wire from="(80,240)" to="(110,240)"/>
<wire from="(80,240)" to="(80,400)"/>
<wire from="(80,400)" to="(90,400)"/>
<wire from="(80,410)" to="(80,500)"/>
<wire from="(80,500)" to="(380,500)"/>
<wire from="(80,500)" to="(80,560)"/>
<wire from="(820,550)" to="(820,580)"/>
<wire from="(90,250)" to="(120,250)"/>
<wire from="(90,250)" to="(90,390)"/>
<wire from="(90,390)" to="(100,390)"/>
<wire from="(90,400)" to="(90,490)"/>
<wire from="(90,490)" to="(370,490)"/>
<wire from="(90,490)" to="(90,560)"/>
<wire from="(900,640)" to="(900,750)"/>
<wire from="(920,600)" to="(940,600)"/>
<wire from="(920,610)" to="(940,610)"/>
<wire from="(920,620)" to="(940,620)"/>
<wire from="(920,630)" to="(940,630)"/>
<wire from="(940,640)" to="(940,650)"/>
<wire from="(940,650)" to="(940,660)"/>
<wire from="(940,660)" to="(940,670)"/>
<wire from="(940,670)" to="(940,680)"/>
<wire from="(940,680)" to="(940,690)"/>
<wire from="(940,690)" to="(940,700)"/>
<wire from="(940,690)" to="(950,690)"/>
<wire from="(960,590)" to="(980,590)"/>
</circuit>
</project>

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logisim/halfsubraction.circ Normal file
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1344
logisim/halfsubraction2.circ Normal file
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639
logisim/multiplier4.circ Normal file
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@ -0,0 +1,639 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.9.0" version="1.0">
This file is intended to be loaded by Logisim-evolution v3.9.0(https://github.com/logisim-evolution/).
<lib desc="#Wiring" name="0">
<tool name="Pin">
<a name="appearance" val="classic"/>
</tool>
<tool name="Power">
<a name="facing" val="west"/>
</tool>
</lib>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4"/>
<lib desc="#I/O" name="5"/>
<lib desc="#TTL" name="6"/>
<lib desc="#TCL" name="7"/>
<lib desc="#Base" name="8"/>
<lib desc="#BFH-Praktika" name="9"/>
<lib desc="#Input/Output-Extra" name="10"/>
<lib desc="#Soc" name="11"/>
<main name="bit4multiplier"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Poke Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Wiring Tool"/>
<tool lib="8" name="Text Tool"/>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
</tool>
<sep/>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
<tool lib="1" name="XOR Gate"/>
<tool lib="1" name="NAND Gate"/>
<tool lib="1" name="NOR Gate"/>
<sep/>
<tool lib="4" name="D Flip-Flop"/>
<tool lib="4" name="Register"/>
</toolbar>
<circuit name="bit4multiplier">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="bit4multiplier"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
<comp lib="0" loc="(1060,870)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="8"/>
<a name="incoming" val="8"/>
</comp>
<comp lib="0" loc="(1070,870)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="Y"/>
<a name="output" val="true"/>
<a name="width" val="8"/>
</comp>
<comp lib="0" loc="(180,150)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="south"/>
<a name="label" val="A"/>
<a name="width" val="4"/>
</comp>
<comp lib="0" loc="(180,200)" name="Splitter">
<a name="facing" val="south"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(210,830)" name="Splitter">
<a name="facing" val="south"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(230,150)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="south"/>
<a name="label" val="B"/>
<a name="width" val="4"/>
</comp>
<comp lib="0" loc="(230,560)" name="Splitter">
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(240,160)" name="Splitter">
<a name="facing" val="south"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(300,910)" name="Power">
<a name="facing" val="west"/>
</comp>
<comp lib="0" loc="(310,340)" name="Power">
<a name="facing" val="west"/>
</comp>
<comp lib="0" loc="(320,610)" name="Power">
<a name="facing" val="west"/>
</comp>
<comp lib="0" loc="(450,410)" name="Ground"/>
<comp lib="0" loc="(450,690)" name="Ground"/>
<comp lib="0" loc="(450,990)" name="Ground"/>
<comp lib="0" loc="(520,460)" name="Ground">
<a name="facing" val="west"/>
</comp>
<comp lib="0" loc="(520,920)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(550,180)" name="Power">
<a name="facing" val="west"/>
</comp>
<comp lib="0" loc="(550,410)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(570,360)" name="Ground">
<a name="facing" val="west"/>
</comp>
<comp lib="0" loc="(580,730)" name="Ground">
<a name="facing" val="west"/>
</comp>
<comp lib="0" loc="(590,900)" name="Ground">
<a name="facing" val="north"/>
</comp>
<comp lib="0" loc="(610,590)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(690,270)" name="Ground">
<a name="facing" val="east"/>
</comp>
<comp lib="0" loc="(770,180)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(830,910)" name="Splitter">
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(840,720)" name="Splitter">
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(850,800)" name="Splitter">
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(870,500)" name="Splitter">
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(880,390)" name="Splitter">
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="6" loc="(320,370)" name="7408"/>
<comp lib="6" loc="(320,650)" name="7408"/>
<comp lib="6" loc="(320,940)" name="7408"/>
<comp lib="6" loc="(550,230)" name="7408"/>
<comp loc="(810,360)" name="addition4"/>
<comp loc="(810,730)" name="addition4"/>
<comp loc="(810,920)" name="addition4"/>
<wire from="(1020,350)" to="(1020,890)"/>
<wire from="(1020,890)" to="(1040,890)"/>
<wire from="(1040,310)" to="(1040,880)"/>
<wire from="(1060,870)" to="(1070,870)"/>
<wire from="(140,170)" to="(140,560)"/>
<wire from="(140,170)" to="(180,170)"/>
<wire from="(140,560)" to="(160,560)"/>
<wire from="(160,190)" to="(160,520)"/>
<wire from="(160,190)" to="(250,190)"/>
<wire from="(160,520)" to="(190,520)"/>
<wire from="(160,560)" to="(160,830)"/>
<wire from="(160,560)" to="(230,560)"/>
<wire from="(160,830)" to="(210,830)"/>
<wire from="(180,150)" to="(180,170)"/>
<wire from="(180,170)" to="(180,200)"/>
<wire from="(190,220)" to="(190,270)"/>
<wire from="(190,270)" to="(190,320)"/>
<wire from="(190,270)" to="(510,270)"/>
<wire from="(190,320)" to="(250,320)"/>
<wire from="(190,520)" to="(190,890)"/>
<wire from="(190,890)" to="(190,980)"/>
<wire from="(190,890)" to="(370,890)"/>
<wire from="(190,980)" to="(330,980)"/>
<wire from="(200,220)" to="(200,250)"/>
<wire from="(200,250)" to="(200,300)"/>
<wire from="(200,250)" to="(530,250)"/>
<wire from="(200,300)" to="(270,300)"/>
<wire from="(200,470)" to="(200,500)"/>
<wire from="(200,470)" to="(240,470)"/>
<wire from="(200,500)" to="(220,500)"/>
<wire from="(210,220)" to="(210,230)"/>
<wire from="(210,230)" to="(210,280)"/>
<wire from="(210,230)" to="(530,230)"/>
<wire from="(210,280)" to="(430,280)"/>
<wire from="(220,1010)" to="(390,1010)"/>
<wire from="(220,220)" to="(220,260)"/>
<wire from="(220,220)" to="(500,220)"/>
<wire from="(220,260)" to="(370,260)"/>
<wire from="(220,500)" to="(220,730)"/>
<wire from="(220,500)" to="(360,500)"/>
<wire from="(220,730)" to="(350,730)"/>
<wire from="(220,850)" to="(220,1010)"/>
<wire from="(230,150)" to="(230,160)"/>
<wire from="(230,160)" to="(240,160)"/>
<wire from="(230,850)" to="(230,990)"/>
<wire from="(230,990)" to="(350,990)"/>
<wire from="(240,210)" to="(240,470)"/>
<wire from="(240,210)" to="(260,210)"/>
<wire from="(240,850)" to="(240,870)"/>
<wire from="(240,870)" to="(410,870)"/>
<wire from="(250,180)" to="(250,190)"/>
<wire from="(250,320)" to="(250,470)"/>
<wire from="(250,470)" to="(410,470)"/>
<wire from="(250,520)" to="(310,520)"/>
<wire from="(250,530)" to="(370,530)"/>
<wire from="(250,540)" to="(300,540)"/>
<wire from="(250,550)" to="(280,550)"/>
<wire from="(250,850)" to="(250,860)"/>
<wire from="(250,860)" to="(350,860)"/>
<wire from="(260,180)" to="(260,210)"/>
<wire from="(270,180)" to="(270,190)"/>
<wire from="(270,190)" to="(430,190)"/>
<wire from="(270,300)" to="(270,450)"/>
<wire from="(270,450)" to="(350,450)"/>
<wire from="(280,180)" to="(280,210)"/>
<wire from="(280,210)" to="(350,210)"/>
<wire from="(280,320)" to="(280,420)"/>
<wire from="(280,320)" to="(350,320)"/>
<wire from="(280,420)" to="(330,420)"/>
<wire from="(280,550)" to="(280,790)"/>
<wire from="(280,790)" to="(410,790)"/>
<wire from="(300,540)" to="(300,700)"/>
<wire from="(300,700)" to="(330,700)"/>
<wire from="(300,900)" to="(300,910)"/>
<wire from="(300,900)" to="(330,900)"/>
<wire from="(310,340)" to="(330,340)"/>
<wire from="(310,520)" to="(310,590)"/>
<wire from="(310,590)" to="(350,590)"/>
<wire from="(320,610)" to="(330,610)"/>
<wire from="(330,400)" to="(330,420)"/>
<wire from="(330,420)" to="(390,420)"/>
<wire from="(330,610)" to="(330,620)"/>
<wire from="(330,680)" to="(330,700)"/>
<wire from="(330,900)" to="(330,910)"/>
<wire from="(330,970)" to="(330,980)"/>
<wire from="(330,980)" to="(410,980)"/>
<wire from="(350,210)" to="(350,320)"/>
<wire from="(350,210)" to="(410,210)"/>
<wire from="(350,320)" to="(350,340)"/>
<wire from="(350,400)" to="(350,450)"/>
<wire from="(350,590)" to="(350,620)"/>
<wire from="(350,680)" to="(350,710)"/>
<wire from="(350,710)" to="(350,730)"/>
<wire from="(350,710)" to="(390,710)"/>
<wire from="(350,860)" to="(350,910)"/>
<wire from="(350,970)" to="(350,990)"/>
<wire from="(360,500)" to="(360,610)"/>
<wire from="(360,500)" to="(420,500)"/>
<wire from="(360,610)" to="(370,610)"/>
<wire from="(370,1020)" to="(470,1020)"/>
<wire from="(370,260)" to="(370,340)"/>
<wire from="(370,400)" to="(370,430)"/>
<wire from="(370,430)" to="(530,430)"/>
<wire from="(370,530)" to="(370,590)"/>
<wire from="(370,590)" to="(410,590)"/>
<wire from="(370,610)" to="(370,620)"/>
<wire from="(370,680)" to="(370,750)"/>
<wire from="(370,750)" to="(470,750)"/>
<wire from="(370,890)" to="(370,910)"/>
<wire from="(370,890)" to="(430,890)"/>
<wire from="(370,970)" to="(370,1020)"/>
<wire from="(390,310)" to="(1040,310)"/>
<wire from="(390,310)" to="(390,340)"/>
<wire from="(390,400)" to="(390,420)"/>
<wire from="(390,600)" to="(390,620)"/>
<wire from="(390,600)" to="(590,600)"/>
<wire from="(390,680)" to="(390,710)"/>
<wire from="(390,850)" to="(390,910)"/>
<wire from="(390,850)" to="(480,850)"/>
<wire from="(390,970)" to="(390,1010)"/>
<wire from="(410,210)" to="(410,340)"/>
<wire from="(410,400)" to="(410,470)"/>
<wire from="(410,590)" to="(410,620)"/>
<wire from="(410,680)" to="(410,790)"/>
<wire from="(410,870)" to="(410,910)"/>
<wire from="(410,970)" to="(410,980)"/>
<wire from="(420,500)" to="(420,610)"/>
<wire from="(420,610)" to="(430,610)"/>
<wire from="(430,1050)" to="(500,1050)"/>
<wire from="(430,130)" to="(430,140)"/>
<wire from="(430,130)" to="(600,130)"/>
<wire from="(430,140)" to="(430,160)"/>
<wire from="(430,140)" to="(710,140)"/>
<wire from="(430,160)" to="(430,190)"/>
<wire from="(430,160)" to="(660,160)"/>
<wire from="(430,280)" to="(430,340)"/>
<wire from="(430,400)" to="(430,440)"/>
<wire from="(430,440)" to="(530,440)"/>
<wire from="(430,610)" to="(430,620)"/>
<wire from="(430,680)" to="(430,710)"/>
<wire from="(430,710)" to="(540,710)"/>
<wire from="(430,890)" to="(430,910)"/>
<wire from="(430,970)" to="(430,1050)"/>
<wire from="(450,330)" to="(450,340)"/>
<wire from="(450,330)" to="(490,330)"/>
<wire from="(450,400)" to="(450,410)"/>
<wire from="(450,610)" to="(450,620)"/>
<wire from="(450,610)" to="(590,610)"/>
<wire from="(450,680)" to="(450,690)"/>
<wire from="(450,870)" to="(450,910)"/>
<wire from="(450,870)" to="(470,870)"/>
<wire from="(450,970)" to="(450,990)"/>
<wire from="(470,620)" to="(470,750)"/>
<wire from="(470,620)" to="(590,620)"/>
<wire from="(470,870)" to="(470,940)"/>
<wire from="(470,940)" to="(500,940)"/>
<wire from="(470,950)" to="(470,1020)"/>
<wire from="(470,950)" to="(500,950)"/>
<wire from="(480,850)" to="(480,930)"/>
<wire from="(480,850)" to="(500,850)"/>
<wire from="(480,930)" to="(500,930)"/>
<wire from="(490,330)" to="(490,420)"/>
<wire from="(490,420)" to="(530,420)"/>
<wire from="(500,170)" to="(500,220)"/>
<wire from="(500,170)" to="(580,170)"/>
<wire from="(500,960)" to="(500,1050)"/>
<wire from="(510,270)" to="(510,300)"/>
<wire from="(510,300)" to="(620,300)"/>
<wire from="(510,500)" to="(510,770)"/>
<wire from="(510,500)" to="(870,500)"/>
<wire from="(510,770)" to="(590,770)"/>
<wire from="(520,450)" to="(520,460)"/>
<wire from="(520,450)" to="(530,450)"/>
<wire from="(520,920)" to="(530,920)"/>
<wire from="(530,120)" to="(530,230)"/>
<wire from="(530,120)" to="(640,120)"/>
<wire from="(530,250)" to="(530,280)"/>
<wire from="(530,280)" to="(560,280)"/>
<wire from="(530,340)" to="(530,380)"/>
<wire from="(530,340)" to="(770,340)"/>
<wire from="(530,380)" to="(590,380)"/>
<wire from="(530,920)" to="(530,940)"/>
<wire from="(530,940)" to="(590,940)"/>
<wire from="(540,630)" to="(540,710)"/>
<wire from="(540,630)" to="(590,630)"/>
<wire from="(550,180)" to="(560,180)"/>
<wire from="(550,400)" to="(550,410)"/>
<wire from="(550,400)" to="(590,400)"/>
<wire from="(560,180)" to="(560,200)"/>
<wire from="(560,260)" to="(560,280)"/>
<wire from="(560,700)" to="(560,750)"/>
<wire from="(560,700)" to="(610,700)"/>
<wire from="(560,750)" to="(590,750)"/>
<wire from="(570,360)" to="(590,360)"/>
<wire from="(570,810)" to="(570,960)"/>
<wire from="(570,810)" to="(850,810)"/>
<wire from="(570,960)" to="(590,960)"/>
<wire from="(580,170)" to="(580,200)"/>
<wire from="(580,260)" to="(580,280)"/>
<wire from="(580,280)" to="(640,280)"/>
<wire from="(580,730)" to="(590,730)"/>
<wire from="(590,900)" to="(590,920)"/>
<wire from="(600,130)" to="(600,200)"/>
<wire from="(600,260)" to="(600,320)"/>
<wire from="(600,320)" to="(720,320)"/>
<wire from="(610,590)" to="(610,700)"/>
<wire from="(620,190)" to="(620,200)"/>
<wire from="(620,190)" to="(750,190)"/>
<wire from="(620,260)" to="(620,300)"/>
<wire from="(640,120)" to="(640,200)"/>
<wire from="(640,260)" to="(640,280)"/>
<wire from="(640,280)" to="(710,280)"/>
<wire from="(660,160)" to="(660,200)"/>
<wire from="(660,260)" to="(660,300)"/>
<wire from="(660,300)" to="(750,300)"/>
<wire from="(680,200)" to="(750,200)"/>
<wire from="(680,260)" to="(680,270)"/>
<wire from="(680,270)" to="(690,270)"/>
<wire from="(710,140)" to="(710,280)"/>
<wire from="(720,210)" to="(720,320)"/>
<wire from="(720,210)" to="(750,210)"/>
<wire from="(750,220)" to="(750,300)"/>
<wire from="(770,180)" to="(770,340)"/>
<wire from="(810,360)" to="(870,360)"/>
<wire from="(810,380)" to="(820,380)"/>
<wire from="(810,730)" to="(840,730)"/>
<wire from="(810,750)" to="(970,750)"/>
<wire from="(810,920)" to="(830,920)"/>
<wire from="(810,940)" to="(860,940)"/>
<wire from="(820,380)" to="(820,510)"/>
<wire from="(820,510)" to="(890,510)"/>
<wire from="(830,910)" to="(830,920)"/>
<wire from="(840,720)" to="(840,730)"/>
<wire from="(850,800)" to="(850,810)"/>
<wire from="(850,870)" to="(950,870)"/>
<wire from="(850,880)" to="(930,880)"/>
<wire from="(850,890)" to="(910,890)"/>
<wire from="(850,900)" to="(900,900)"/>
<wire from="(860,680)" to="(990,680)"/>
<wire from="(860,690)" to="(900,690)"/>
<wire from="(860,700)" to="(930,700)"/>
<wire from="(860,710)" to="(940,710)"/>
<wire from="(860,940)" to="(860,950)"/>
<wire from="(860,950)" to="(1040,950)"/>
<wire from="(870,360)" to="(870,390)"/>
<wire from="(870,390)" to="(880,390)"/>
<wire from="(870,760)" to="(900,760)"/>
<wire from="(870,770)" to="(930,770)"/>
<wire from="(870,780)" to="(940,780)"/>
<wire from="(870,790)" to="(970,790)"/>
<wire from="(890,460)" to="(930,460)"/>
<wire from="(890,470)" to="(920,470)"/>
<wire from="(890,480)" to="(910,480)"/>
<wire from="(890,490)" to="(890,510)"/>
<wire from="(900,350)" to="(1020,350)"/>
<wire from="(900,360)" to="(930,360)"/>
<wire from="(900,370)" to="(920,370)"/>
<wire from="(900,380)" to="(910,380)"/>
<wire from="(900,690)" to="(900,760)"/>
<wire from="(900,900)" to="(900,940)"/>
<wire from="(900,940)" to="(1040,940)"/>
<wire from="(910,380)" to="(910,480)"/>
<wire from="(910,890)" to="(910,930)"/>
<wire from="(910,930)" to="(1040,930)"/>
<wire from="(920,370)" to="(920,470)"/>
<wire from="(930,360)" to="(930,460)"/>
<wire from="(930,700)" to="(930,770)"/>
<wire from="(930,880)" to="(930,920)"/>
<wire from="(930,920)" to="(1040,920)"/>
<wire from="(940,710)" to="(940,780)"/>
<wire from="(950,870)" to="(950,910)"/>
<wire from="(950,910)" to="(1040,910)"/>
<wire from="(970,750)" to="(970,790)"/>
<wire from="(990,680)" to="(990,900)"/>
<wire from="(990,900)" to="(1040,900)"/>
</circuit>
<circuit name="fulladder">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="fulladder"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
<comp lib="0" loc="(130,220)" name="Power"/>
<comp lib="0" loc="(200,480)" name="Ground"/>
<comp lib="0" loc="(250,300)" name="Ground"/>
<comp lib="0" loc="(300,390)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="CarryO"/>
<a name="output" val="true"/>
</comp>
<comp lib="0" loc="(310,260)" name="Power"/>
<comp lib="0" loc="(410,60)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="south"/>
<a name="label" val="Cin"/>
</comp>
<comp lib="0" loc="(430,340)" name="Ground"/>
<comp lib="0" loc="(460,250)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="Sum"/>
<a name="output" val="true"/>
</comp>
<comp lib="0" loc="(80,110)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="B"/>
</comp>
<comp lib="0" loc="(80,400)" name="Power"/>
<comp lib="0" loc="(80,70)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="A"/>
</comp>
<comp lib="6" loc="(120,260)" name="7408"/>
<comp lib="6" loc="(300,300)" name="7486"/>
<comp lib="6" loc="(70,440)" name="7432"/>
<wire from="(100,200)" to="(100,410)"/>
<wire from="(100,200)" to="(190,200)"/>
<wire from="(120,320)" to="(120,410)"/>
<wire from="(120,320)" to="(270,320)"/>
<wire from="(130,220)" to="(130,230)"/>
<wire from="(140,390)" to="(140,410)"/>
<wire from="(140,390)" to="(300,390)"/>
<wire from="(150,70)" to="(150,230)"/>
<wire from="(150,70)" to="(350,70)"/>
<wire from="(170,110)" to="(170,230)"/>
<wire from="(170,110)" to="(330,110)"/>
<wire from="(190,200)" to="(190,230)"/>
<wire from="(200,470)" to="(200,480)"/>
<wire from="(210,140)" to="(210,230)"/>
<wire from="(210,140)" to="(370,140)"/>
<wire from="(230,180)" to="(230,230)"/>
<wire from="(230,180)" to="(410,180)"/>
<wire from="(250,210)" to="(250,230)"/>
<wire from="(250,210)" to="(270,210)"/>
<wire from="(250,290)" to="(250,300)"/>
<wire from="(270,210)" to="(270,320)"/>
<wire from="(310,260)" to="(310,270)"/>
<wire from="(330,110)" to="(330,270)"/>
<wire from="(350,70)" to="(350,270)"/>
<wire from="(370,140)" to="(370,250)"/>
<wire from="(370,250)" to="(370,270)"/>
<wire from="(370,250)" to="(390,250)"/>
<wire from="(390,250)" to="(390,270)"/>
<wire from="(410,180)" to="(410,270)"/>
<wire from="(410,60)" to="(410,180)"/>
<wire from="(430,250)" to="(430,270)"/>
<wire from="(430,250)" to="(460,250)"/>
<wire from="(430,330)" to="(430,340)"/>
<wire from="(80,110)" to="(170,110)"/>
<wire from="(80,400)" to="(80,410)"/>
<wire from="(80,70)" to="(150,70)"/>
</circuit>
<circuit name="addition4">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="addition4"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
<comp lib="0" loc="(130,160)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="B"/>
<a name="width" val="4"/>
</comp>
<comp lib="0" loc="(130,50)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="A"/>
<a name="width" val="4"/>
</comp>
<comp lib="0" loc="(140,150)" name="Splitter">
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(140,50)" name="Splitter">
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(330,30)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="south"/>
<a name="label" val="CarryIn"/>
</comp>
<comp lib="0" loc="(480,490)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="CarryO"/>
<a name="output" val="true"/>
</comp>
<comp lib="0" loc="(550,130)" name="Splitter">
<a name="facing" val="west"/>
<a name="fanout" val="4"/>
<a name="incoming" val="4"/>
</comp>
<comp lib="0" loc="(560,120)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="Sum"/>
<a name="output" val="true"/>
<a name="width" val="4"/>
</comp>
<comp loc="(460,120)" name="fulladder"/>
<comp loc="(460,250)" name="fulladder"/>
<comp loc="(460,360)" name="fulladder"/>
<comp loc="(460,470)" name="fulladder"/>
<wire from="(130,160)" to="(140,160)"/>
<wire from="(130,50)" to="(140,50)"/>
<wire from="(140,150)" to="(140,160)"/>
<wire from="(160,10)" to="(220,10)"/>
<wire from="(160,110)" to="(210,110)"/>
<wire from="(160,120)" to="(180,120)"/>
<wire from="(160,130)" to="(170,130)"/>
<wire from="(160,140)" to="(160,510)"/>
<wire from="(160,20)" to="(200,20)"/>
<wire from="(160,30)" to="(190,30)"/>
<wire from="(160,40)" to="(160,90)"/>
<wire from="(160,510)" to="(240,510)"/>
<wire from="(170,130)" to="(170,400)"/>
<wire from="(170,400)" to="(240,400)"/>
<wire from="(180,120)" to="(180,290)"/>
<wire from="(180,290)" to="(240,290)"/>
<wire from="(190,30)" to="(190,100)"/>
<wire from="(200,20)" to="(200,270)"/>
<wire from="(200,270)" to="(240,270)"/>
<wire from="(210,110)" to="(210,160)"/>
<wire from="(210,160)" to="(240,160)"/>
<wire from="(220,10)" to="(220,140)"/>
<wire from="(220,140)" to="(240,140)"/>
<wire from="(240,220)" to="(240,250)"/>
<wire from="(240,220)" to="(460,220)"/>
<wire from="(240,30)" to="(240,120)"/>
<wire from="(240,30)" to="(330,30)"/>
<wire from="(240,340)" to="(240,360)"/>
<wire from="(240,340)" to="(460,340)"/>
<wire from="(240,450)" to="(240,470)"/>
<wire from="(240,450)" to="(460,450)"/>
<wire from="(30,490)" to="(240,490)"/>
<wire from="(30,90)" to="(160,90)"/>
<wire from="(30,90)" to="(30,490)"/>
<wire from="(460,120)" to="(530,120)"/>
<wire from="(460,140)" to="(460,220)"/>
<wire from="(460,250)" to="(470,250)"/>
<wire from="(460,270)" to="(460,340)"/>
<wire from="(460,360)" to="(480,360)"/>
<wire from="(460,380)" to="(460,450)"/>
<wire from="(460,470)" to="(500,470)"/>
<wire from="(460,490)" to="(480,490)"/>
<wire from="(470,150)" to="(470,250)"/>
<wire from="(470,150)" to="(530,150)"/>
<wire from="(480,160)" to="(480,360)"/>
<wire from="(480,160)" to="(530,160)"/>
<wire from="(500,170)" to="(500,470)"/>
<wire from="(500,170)" to="(530,170)"/>
<wire from="(530,120)" to="(530,140)"/>
<wire from="(550,120)" to="(550,130)"/>
<wire from="(550,120)" to="(560,120)"/>
<wire from="(90,100)" to="(190,100)"/>
<wire from="(90,100)" to="(90,380)"/>
<wire from="(90,380)" to="(240,380)"/>
</circuit>
</project>

163
logisim/opCode.circ Normal file
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@ -0,0 +1,163 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.9.0" version="1.0">
This file is intended to be loaded by Logisim-evolution v3.9.0(https://github.com/logisim-evolution/).
<lib desc="#Wiring" name="0">
<tool name="Pin">
<a name="appearance" val="classic"/>
</tool>
</lib>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4"/>
<lib desc="#I/O" name="5"/>
<lib desc="#TTL" name="6"/>
<lib desc="#TCL" name="7"/>
<lib desc="#Base" name="8"/>
<lib desc="#BFH-Praktika" name="9"/>
<lib desc="#Input/Output-Extra" name="10"/>
<lib desc="#Soc" name="11"/>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Poke Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Wiring Tool"/>
<tool lib="8" name="Text Tool"/>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
</tool>
<sep/>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
<tool lib="1" name="XOR Gate"/>
<tool lib="1" name="NAND Gate"/>
<tool lib="1" name="NOR Gate"/>
<sep/>
<tool lib="4" name="D Flip-Flop"/>
<tool lib="4" name="Register"/>
</toolbar>
<circuit name="main">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="main"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
<comp lib="1" loc="(330,220)" name="NOT Gate"/>
<comp lib="1" loc="(330,310)" name="NOT Gate"/>
<comp lib="1" loc="(550,140)" name="AND Gate"/>
<comp lib="1" loc="(550,260)" name="AND Gate"/>
<comp lib="1" loc="(550,380)" name="AND Gate"/>
<comp lib="1" loc="(550,500)" name="AND Gate"/>
<comp lib="1" loc="(560,80)" name="NOT Gate">
<a name="facing" val="south"/>
</comp>
<comp lib="1" loc="(690,140)" name="AND Gate"/>
<comp lib="1" loc="(690,200)" name="AND Gate"/>
<comp lib="1" loc="(690,260)" name="AND Gate"/>
<comp lib="1" loc="(690,320)" name="AND Gate"/>
<comp lib="1" loc="(690,380)" name="AND Gate"/>
<comp lib="1" loc="(690,440)" name="AND Gate"/>
<comp lib="1" loc="(690,500)" name="AND Gate"/>
<comp lib="1" loc="(690,560)" name="AND Gate"/>
<comp lib="5" loc="(260,200)" name="DipSwitch">
<a name="facing" val="south"/>
</comp>
<comp lib="5" loc="(740,120)" name="LedBar"/>
<wire from="(150,220)" to="(230,220)"/>
<wire from="(150,50)" to="(150,220)"/>
<wire from="(150,50)" to="(560,50)"/>
<wire from="(230,200)" to="(230,220)"/>
<wire from="(240,200)" to="(240,280)"/>
<wire from="(240,280)" to="(240,310)"/>
<wire from="(240,280)" to="(500,280)"/>
<wire from="(240,310)" to="(240,520)"/>
<wire from="(240,310)" to="(300,310)"/>
<wire from="(240,520)" to="(500,520)"/>
<wire from="(250,200)" to="(250,220)"/>
<wire from="(250,220)" to="(250,360)"/>
<wire from="(250,220)" to="(300,220)"/>
<wire from="(250,360)" to="(250,480)"/>
<wire from="(250,360)" to="(500,360)"/>
<wire from="(250,480)" to="(500,480)"/>
<wire from="(330,120)" to="(330,220)"/>
<wire from="(330,120)" to="(440,120)"/>
<wire from="(330,310)" to="(340,310)"/>
<wire from="(340,160)" to="(340,310)"/>
<wire from="(340,160)" to="(500,160)"/>
<wire from="(340,310)" to="(340,400)"/>
<wire from="(340,400)" to="(500,400)"/>
<wire from="(440,120)" to="(440,240)"/>
<wire from="(440,120)" to="(500,120)"/>
<wire from="(440,240)" to="(500,240)"/>
<wire from="(550,120)" to="(550,140)"/>
<wire from="(550,120)" to="(570,120)"/>
<wire from="(550,260)" to="(570,260)"/>
<wire from="(550,360)" to="(550,380)"/>
<wire from="(550,360)" to="(570,360)"/>
<wire from="(550,480)" to="(550,500)"/>
<wire from="(550,480)" to="(570,480)"/>
<wire from="(560,50)" to="(600,50)"/>
<wire from="(560,80)" to="(610,80)"/>
<wire from="(570,120)" to="(570,180)"/>
<wire from="(570,120)" to="(640,120)"/>
<wire from="(570,180)" to="(640,180)"/>
<wire from="(570,240)" to="(570,260)"/>
<wire from="(570,240)" to="(640,240)"/>
<wire from="(570,260)" to="(570,300)"/>
<wire from="(570,300)" to="(640,300)"/>
<wire from="(570,360)" to="(570,420)"/>
<wire from="(570,360)" to="(640,360)"/>
<wire from="(570,420)" to="(640,420)"/>
<wire from="(570,480)" to="(570,540)"/>
<wire from="(570,480)" to="(640,480)"/>
<wire from="(570,540)" to="(640,540)"/>
<wire from="(600,220)" to="(600,340)"/>
<wire from="(600,220)" to="(640,220)"/>
<wire from="(600,340)" to="(600,460)"/>
<wire from="(600,340)" to="(640,340)"/>
<wire from="(600,460)" to="(600,580)"/>
<wire from="(600,460)" to="(640,460)"/>
<wire from="(600,50)" to="(600,220)"/>
<wire from="(600,580)" to="(640,580)"/>
<wire from="(610,280)" to="(620,280)"/>
<wire from="(610,80)" to="(610,280)"/>
<wire from="(610,80)" to="(630,80)"/>
<wire from="(620,280)" to="(620,400)"/>
<wire from="(620,280)" to="(640,280)"/>
<wire from="(620,400)" to="(620,520)"/>
<wire from="(620,400)" to="(640,400)"/>
<wire from="(620,520)" to="(640,520)"/>
<wire from="(630,160)" to="(640,160)"/>
<wire from="(630,80)" to="(630,160)"/>
<wire from="(690,140)" to="(740,140)"/>
<wire from="(690,200)" to="(750,200)"/>
<wire from="(690,260)" to="(760,260)"/>
<wire from="(690,320)" to="(770,320)"/>
<wire from="(690,380)" to="(780,380)"/>
<wire from="(690,440)" to="(790,440)"/>
<wire from="(690,500)" to="(800,500)"/>
<wire from="(690,560)" to="(810,560)"/>
<wire from="(740,120)" to="(740,140)"/>
<wire from="(750,120)" to="(750,200)"/>
<wire from="(760,120)" to="(760,260)"/>
<wire from="(770,120)" to="(770,320)"/>
<wire from="(780,120)" to="(780,380)"/>
<wire from="(790,120)" to="(790,440)"/>
<wire from="(800,120)" to="(800,500)"/>
<wire from="(810,120)" to="(810,560)"/>
</circuit>
</project>

262
logisim/subraction.circ Normal file
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@ -0,0 +1,262 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.9.0" version="1.0">
This file is intended to be loaded by Logisim-evolution v3.9.0(https://github.com/logisim-evolution/).
<lib desc="#Wiring" name="0">
<tool name="Pin">
<a name="appearance" val="classic"/>
</tool>
</lib>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4"/>
<lib desc="#I/O" name="5"/>
<lib desc="#TTL" name="6"/>
<lib desc="#TCL" name="7"/>
<lib desc="#Base" name="8"/>
<lib desc="#BFH-Praktika" name="9"/>
<lib desc="#Input/Output-Extra" name="10"/>
<lib desc="#Soc" name="11"/>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Poke Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Wiring Tool"/>
<tool lib="8" name="Text Tool"/>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
</tool>
<sep/>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
<tool lib="1" name="XOR Gate"/>
<tool lib="1" name="NAND Gate"/>
<tool lib="1" name="NOR Gate"/>
<sep/>
<tool lib="4" name="D Flip-Flop"/>
<tool lib="4" name="Register"/>
</toolbar>
<circuit name="main">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="main"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
</circuit>
<circuit name="opcode">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="opcode"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
<comp lib="0" loc="(1040,180)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="opcode1"/>
<a name="output" val="true"/>
</comp>
<comp lib="0" loc="(1050,320)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="opcode6"/>
<a name="output" val="true"/>
</comp>
<comp lib="0" loc="(1060,620)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="opcode5"/>
<a name="output" val="true"/>
</comp>
<comp lib="0" loc="(1070,60)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="opcode3"/>
<a name="output" val="true"/>
</comp>
<comp lib="0" loc="(1100,380)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="opcode7"/>
<a name="output" val="true"/>
</comp>
<comp lib="0" loc="(230,280)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="A0"/>
</comp>
<comp lib="0" loc="(230,400)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="A1"/>
</comp>
<comp lib="0" loc="(230,540)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="A2"/>
</comp>
<comp lib="0" loc="(980,220)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="opcode0"/>
<a name="output" val="true"/>
</comp>
<comp lib="0" loc="(990,30)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="opcode2"/>
<a name="output" val="true"/>
</comp>
<comp lib="0" loc="(990,660)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="opcode4"/>
<a name="output" val="true"/>
</comp>
<comp lib="1" loc="(330,520)" name="NOT Gate"/>
<comp lib="1" loc="(340,250)" name="NOT Gate"/>
<comp lib="1" loc="(350,380)" name="NOT Gate"/>
<comp lib="6" loc="(620,380)" name="7408"/>
<comp lib="6" loc="(840,970)" name="7408"/>
<comp lib="6" loc="(920,120)" name="7408"/>
<comp lib="6" loc="(940,470)" name="7408"/>
<comp lib="8" loc="(455,245)" name="Text">
<a name="text" val="notc"/>
</comp>
<comp lib="8" loc="(460,375)" name="Text">
<a name="text" val="notb"/>
</comp>
<comp lib="8" loc="(470,510)" name="Text">
<a name="text" val="nota"/>
</comp>
<comp lib="8" loc="(690,295)" name="Text">
<a name="text" val="and3"/>
</comp>
<wire from="(1000,280)" to="(1000,520)"/>
<wire from="(1000,280)" to="(1010,280)"/>
<wire from="(1000,520)" to="(1030,520)"/>
<wire from="(1010,150)" to="(1010,170)"/>
<wire from="(1010,170)" to="(1010,280)"/>
<wire from="(1010,170)" to="(1020,170)"/>
<wire from="(1010,320)" to="(1010,440)"/>
<wire from="(1010,320)" to="(1050,320)"/>
<wire from="(1010,500)" to="(1010,540)"/>
<wire from="(1010,80)" to="(1010,90)"/>
<wire from="(1020,70)" to="(1020,170)"/>
<wire from="(1020,70)" to="(1030,70)"/>
<wire from="(1030,150)" to="(1030,180)"/>
<wire from="(1030,180)" to="(1040,180)"/>
<wire from="(1030,400)" to="(1030,440)"/>
<wire from="(1030,500)" to="(1030,520)"/>
<wire from="(1030,70)" to="(1030,90)"/>
<wire from="(1050,340)" to="(1050,440)"/>
<wire from="(1050,500)" to="(1050,620)"/>
<wire from="(1050,60)" to="(1050,90)"/>
<wire from="(1050,60)" to="(1070,60)"/>
<wire from="(1050,620)" to="(1060,620)"/>
<wire from="(1070,380)" to="(1070,440)"/>
<wire from="(1070,380)" to="(1100,380)"/>
<wire from="(230,280)" to="(250,280)"/>
<wire from="(230,400)" to="(260,400)"/>
<wire from="(230,540)" to="(260,540)"/>
<wire from="(250,250)" to="(250,280)"/>
<wire from="(250,250)" to="(310,250)"/>
<wire from="(250,280)" to="(970,280)"/>
<wire from="(260,380)" to="(260,400)"/>
<wire from="(260,380)" to="(320,380)"/>
<wire from="(260,400)" to="(560,400)"/>
<wire from="(260,520)" to="(260,540)"/>
<wire from="(260,520)" to="(300,520)"/>
<wire from="(260,540)" to="(630,540)"/>
<wire from="(330,250)" to="(340,250)"/>
<wire from="(330,520)" to="(690,520)"/>
<wire from="(340,250)" to="(880,250)"/>
<wire from="(350,380)" to="(460,380)"/>
<wire from="(460,370)" to="(460,380)"/>
<wire from="(460,380)" to="(600,380)"/>
<wire from="(560,400)" to="(560,470)"/>
<wire from="(560,470)" to="(650,470)"/>
<wire from="(600,320)" to="(600,380)"/>
<wire from="(600,320)" to="(670,320)"/>
<wire from="(610,330)" to="(610,430)"/>
<wire from="(610,330)" to="(650,330)"/>
<wire from="(610,430)" to="(630,430)"/>
<wire from="(630,400)" to="(630,410)"/>
<wire from="(630,410)" to="(630,430)"/>
<wire from="(630,430)" to="(630,540)"/>
<wire from="(650,330)" to="(650,350)"/>
<wire from="(650,410)" to="(650,440)"/>
<wire from="(650,440)" to="(650,470)"/>
<wire from="(650,440)" to="(710,440)"/>
<wire from="(670,320)" to="(670,330)"/>
<wire from="(670,330)" to="(670,350)"/>
<wire from="(670,330)" to="(730,330)"/>
<wire from="(670,410)" to="(670,550)"/>
<wire from="(670,550)" to="(860,550)"/>
<wire from="(690,300)" to="(690,350)"/>
<wire from="(690,300)" to="(780,300)"/>
<wire from="(690,410)" to="(690,430)"/>
<wire from="(690,430)" to="(690,520)"/>
<wire from="(690,430)" to="(770,430)"/>
<wire from="(710,340)" to="(710,350)"/>
<wire from="(710,340)" to="(770,340)"/>
<wire from="(710,410)" to="(710,440)"/>
<wire from="(730,330)" to="(730,350)"/>
<wire from="(730,350)" to="(730,360)"/>
<wire from="(730,410)" to="(730,510)"/>
<wire from="(730,510)" to="(840,510)"/>
<wire from="(750,320)" to="(750,350)"/>
<wire from="(750,320)" to="(950,320)"/>
<wire from="(770,340)" to="(770,430)"/>
<wire from="(780,300)" to="(780,400)"/>
<wire from="(780,400)" to="(920,400)"/>
<wire from="(840,60)" to="(840,80)"/>
<wire from="(840,60)" to="(950,60)"/>
<wire from="(840,80)" to="(1010,80)"/>
<wire from="(840,80)" to="(840,510)"/>
<wire from="(860,370)" to="(860,550)"/>
<wire from="(860,370)" to="(970,370)"/>
<wire from="(880,250)" to="(880,530)"/>
<wire from="(880,250)" to="(930,250)"/>
<wire from="(880,530)" to="(970,530)"/>
<wire from="(900,190)" to="(930,190)"/>
<wire from="(900,70)" to="(900,190)"/>
<wire from="(900,70)" to="(970,70)"/>
<wire from="(920,400)" to="(920,510)"/>
<wire from="(920,510)" to="(930,510)"/>
<wire from="(930,150)" to="(930,190)"/>
<wire from="(930,190)" to="(930,250)"/>
<wire from="(930,250)" to="(990,250)"/>
<wire from="(930,510)" to="(930,540)"/>
<wire from="(930,510)" to="(950,510)"/>
<wire from="(930,540)" to="(1010,540)"/>
<wire from="(950,150)" to="(950,180)"/>
<wire from="(950,180)" to="(950,320)"/>
<wire from="(950,180)" to="(990,180)"/>
<wire from="(950,500)" to="(950,510)"/>
<wire from="(950,60)" to="(950,90)"/>
<wire from="(970,150)" to="(970,220)"/>
<wire from="(970,220)" to="(980,220)"/>
<wire from="(970,280)" to="(1000,280)"/>
<wire from="(970,280)" to="(970,340)"/>
<wire from="(970,340)" to="(1050,340)"/>
<wire from="(970,370)" to="(970,400)"/>
<wire from="(970,400)" to="(1030,400)"/>
<wire from="(970,400)" to="(970,440)"/>
<wire from="(970,500)" to="(970,530)"/>
<wire from="(970,70)" to="(970,90)"/>
<wire from="(990,150)" to="(990,180)"/>
<wire from="(990,250)" to="(990,440)"/>
<wire from="(990,30)" to="(990,90)"/>
<wire from="(990,500)" to="(990,660)"/>
</circuit>
</project>

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module overflowDetect (
input [1:0] opCode,
input [3:0] A, B,
input [3:0] Y,
input CarryOUT,
output overflowDetect
);
wire opC;
wire sign1, sign2, sign3, sign4;
wire addOverflow, subOverflow;
wire detect1, detect2;
or o1 (opC, opCode[0], opCode[1]); //check add or sub
xnor xno1 (sign1, A[3], B[3]); // A B same sign
xor xo2 (sign3, A[3], B[3]); // A and B opposite sign
xor xo1 (sign2, Y[3], A[3]); // A and Sum opposite sign
and a01 (addOverflow, sign1, opCode[0]); // A B same for add
and a02 (subOverflow, sign3, opCode[1]); // A B diff for sub
or o2 (detect1, addOverflow, subOverflow);
and a03(detect2, detect1, sign2);
and a04(overflowDetect, opC, detect2);
endmodule

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[ZoneTransfer]
ZoneId=3

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verilog/ALU0.2/!NOTUSE!selector.v Normal file
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module selector (
input [3:0] select,
input [7:0] Y,
input [3:0] A, B,
input [2:0] opCodeA,
output [7:0] s0
);
wire [3:0] a0, b0, tempAB, tempYO;
wire [7:0] y0;
wire [2:0] op0;
wire tempsO, temps;
// Select signals for A
and a00 (a0[0], select[0], A[0]);
and a01 (a0[1], select[0], A[1]);
and a02 (a0[2], select[0], A[2]);
and a03 (a0[3], select[0], A[3]);
// Select signals for B
and b00 (b0[0], select[1], B[0]);
and b01 (b0[1], select[1], B[1]);
and b02 (b0[2], select[1], B[2]);
and b03 (b0[3], select[1], B[3]);
// Select signals for Y
and y00 (y0[0], select[2], Y[0]);
and y01 (y0[1], select[2], Y[1]);
and y02 (y0[2], select[2], Y[2]);
and y03 (y0[3], select[2], Y[3]);
and y04 (y0[4], select[2], Y[4]);
and y05 (y0[5], select[2], Y[5]);
and y06 (y0[6], select[2], Y[6]);
and y07 (y0[7], select[2], Y[7]);
// Select signals for opCodeA
and op00 (op0[0], select[3], opCodeA[0]);
and op01 (op0[1], select[3], opCodeA[1]);
and op02 (op0[2], select[3], opCodeA[2]);
// Combine A and B
or or1 (tempAB[0], a0[0], b0[0]);
or or2 (tempAB[1], a0[1], b0[1]);
or or3 (tempAB[2], a0[2], b0[2]);
or or4 (tempAB[3], a0[3], b0[3]);
// Combine Y and opCodeA
or or5 (tempYO[0], y0[0], op0[0]);
or or6 (tempYO[1], y0[1], op0[1]);
or or7 (tempYO[2], y0[2], op0[2]);
or or8 (tempYO[3], y0[3], 1'b0);
// NOR for select logic
nor s01 (tempsO, select[0], select[1]);
nor s02 (temps, tempsO, select[3]);
// Final s0 connections
or or9 (s0[0], tempAB[0], tempYO[0]);
or or10 (s0[1], tempAB[1], tempYO[1]);
or or11 (s0[2], tempAB[2], tempYO[2]);
or or12 (s0[3], tempAB[3], tempYO[3]);
and and13 (s0[4], y0[4], temps);
and and14 (s0[5], y0[5], temps);
and and15 (s0[6], y0[6], temps);
and and16 (s0[7], y0[7], temps);
endmodule

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module ALU (
input [3:0] A, B,
input CarryIN,
input [2:0] opCodeA,
output [7:0] Y,
output CarryOUT, overflow
);
// Supports: ADD[0], SUB[1], MULT[2], AND[4], OR[5], XOR[6]
wire [7:0] opCode8;
wire [3:0] add_Y, sub_Y;
wire [3:0] resultA, resultO, resultX, lUOutput1;
wire [3:0] aUtemp1, aUtemp2, lUOutput2;
wire [3:0] wireY, wireLA;
wire [7:0] opwireM, wireM, Y;
opCode opCd (.A(opCodeA), .opCode(opCode8));
arithmeticUnit aU(.opCode(opCode8[1:0]), .A(A), .B(B), .CarryIN(CarryIN), .add_Y(add_Y), .sub_Y(sub_Y), .CarryOUT(CarryOUT), .overflow(overflow));
logicUnit lU (.opCode(opCode8[6:4]), .A(A), .B(B), .resultA(resultA), .resultO(resultO), .resultX(resultX));
multiplier mU (.A(A), .B(B), .Y(opwireM));
or o01 (lUOutput1[0], resultA[0], resultO[0]);
or o02 (lUOutput1[1], resultA[1], resultO[1]);
or o03 (lUOutput1[2], resultA[2], resultO[2]);
or o04 (lUOutput1[3], resultA[3], resultO[3]);
or o11 (lUOutput2[0], lUOutput1[0], resultX[0]);
or o12 (lUOutput2[1], lUOutput1[1], resultX[1]);
or o13 (lUOutput2[2], lUOutput1[2], resultX[2]);
or o14 (lUOutput2[3], lUOutput1[3], resultX[3]);
and a01 (aUtemp1[0], opCode8[0], add_Y[0]);
and a02 (aUtemp1[1], opCode8[0], add_Y[1]);
and a03 (aUtemp1[2], opCode8[0], add_Y[2]);
and a04 (aUtemp1[3], opCode8[0], add_Y[3]);
and a11 (aUtemp2[0], opCode8[1], sub_Y[0]);
and a12 (aUtemp2[1], opCode8[1], sub_Y[1]);
and a13 (aUtemp2[2], opCode8[1], sub_Y[2]);
and a14 (aUtemp2[3], opCode8[1], sub_Y[3]);
and a21 (wireM[0], opCode8[2], opwireM[0]);
and a22 (wireM[1], opCode8[2], opwireM[1]);
and a23 (wireM[2], opCode8[2], opwireM[2]);
and a24 (wireM[3], opCode8[2], opwireM[3]);
and a25 (wireM[4], opCode8[2], opwireM[4]);
and a26 (wireM[5], opCode8[2], opwireM[5]);
and a27 (wireM[6], opCode8[2], opwireM[6]);
and a28 (wireM[7], opCode8[2], opwireM[7]);
or o21 (wireY[0], aUtemp1[0], aUtemp2[0]);
or o22 (wireY[1], aUtemp1[1], aUtemp2[1]);
or o23 (wireY[2], aUtemp1[2], aUtemp2[2]);
or o24 (wireY[3], aUtemp1[3], aUtemp2[3]);
or o1 (wireLA[0], lUOutput2[0], wireY[0]);
or o2 (wireLA[1], lUOutput2[1], wireY[1]);
or o3 (wireLA[2], lUOutput2[2], wireY[2]);
or o4 (wireLA[3], lUOutput2[3], wireY[3]);
or o31 (Y[0], wireLA[0], wireM[0]);
or o32 (Y[1], wireLA[1], wireM[1]);
or o33 (Y[2], wireLA[2], wireM[2]);
or o34 (Y[3], wireLA[3], wireM[3]);
or o35 (Y[4], 1'b0, wireM[4]);
or o36 (Y[5], 1'b0, wireM[5]);
or o37 (Y[6], 1'b0, wireM[6]);
or o38 (Y[7], 1'b0, wireM[7]);
//BinaryToBCD btod1(.binary(Y), .bcd(bcd)); // WIRE Y BINARY!!!!
endmodule

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[ZoneTransfer]
ZoneId=3

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[ZoneTransfer]
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verilog/ALU0.2/ALUTB.v Normal file
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module ALUTB ();
reg [3:0] A, B;
reg CarryIN;
reg [2:0] opCodeA;
wire CarryOUT, overflow;
wire [11:0] bcd;
ALU uut(
.A(A),
.B(B),
.CarryIN(CarryIN),
.opCodeA(opCodeA),
.CarryOUT(CarryOUT),
.bcd(bcd),
.overflow(overflow)
);
initial begin
$dumpfile("ALU.vcd"); // GTKWAVE SIMULTAIN DATA WAVEFORM
$dumpvars; // ICARUS VERILOG ADD ALL VARIABLES
A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b011; #5;
A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b011; #5;
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b011; #5;
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b011; #5;
A = 4'b0111; B = 4'b0111; CarryIN = 1'b1; opCodeA = 3'b011; #5;
A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b111; #5;
A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b111; #5;
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b111; #5;
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b111; #5;
A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b111; #5;
A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b010; #5;
A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b010; #5;
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b010; #5;
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b010; #5;
A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b010; #5;
$finish; //NOT CONTAIN CLK, BUT STILL STOPS CODE
end
endmodule

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[ZoneTransfer]
ZoneId=3

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[ZoneTransfer]
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verilog/ALU0.2/BinaryToBCD.v Normal file
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module BinaryToBCD (
input [7:0] binary,
output [11:0] bcd
);
wire empty1, empty2;
wire [3:0] dab1, dab2, dab3, dab4, dab5;
and a111 (empty1, 1'b0, 1'b0);
and a000 (empty2, 1'b0, 1'b0);
and a222 (bcd[11], 1'b0, 1'b0);
and a223 (bcd[10], 1'b0, 1'b0);
dabble d1t (.A((empty1)),
.B(binary[7]),
.C(binary[6]),
.D(binary[5]),
.X(dab1[0]),
.Y(dab1[1]),
.Z(dab1[2]),
.E(dab1[3]));
dabble d2u (.A((dab1[1])),
.B(dab1[2]),
.C(dab1[3]),
.D(binary[4]),
.X(dab2[0]),
.Y(dab2[1]),
.Z(dab2[2]),
.E(dab2[3]));
dabble d3v (.A((dab2[1])),
.B(dab2[2]),
.C(dab2[3]),
.D(binary[3]),
.X(dab3[0]),
.Y(dab3[1]),
.Z(dab3[2]),
.E(dab3[3]));
dabble d4w (.A((empty2)),
.B(dab1[0]),
.C(dab2[0]),
.D(dab3[0]),
.X(bcd[9]),
.Y(dab4[1]),
.Z(dab4[2]),
.E(dab4[3]));
dabble d5x (.A((dab3[1])),
.B(dab3[2]),
.C(dab3[3]),
.D(binary[2]),
.X(dab5[0]),
.Y(dab5[1]),
.Z(dab5[2]),
.E(dab5[3]));
dabble d6y (.A((dab4[1])),
.B(dab4[2]),
.C(dab4[3]),
.D(dab5[0]),
.X(bcd[8]),
.Y(bcd[7]),
.Z(bcd[6]),
.E(bcd[5]));
dabble d7z (.A((dab5[1])),
.B(dab5[2]),
.C(dab5[3]),
.D(binary[1]),
.X(bcd[4]),
.Y(bcd[3]),
.Z(bcd[2]),
.E(bcd[1]));
or o1 (bcd[0], binary[0], 1'b0);
endmodule

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$date
Mon Dec 23 02:48:47 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module BinaryToBCDTB $end
$var wire 12 ! bcd [11:0] $end
$var reg 8 " binary [7:0] $end
$scope module uut $end
$var wire 8 # binary [7:0] $end
$var wire 1 $ empty1 $end
$var wire 1 % empty2 $end
$var wire 4 & dab5 [3:0] $end
$var wire 4 ' dab4 [3:0] $end
$var wire 4 ( dab3 [3:0] $end
$var wire 4 ) dab2 [3:0] $end
$var wire 4 * dab1 [3:0] $end
$var wire 12 + bcd [11:0] $end
$scope module d1t $end
$var wire 1 $ A $end
$var wire 1 , B $end
$var wire 1 - C $end
$var wire 1 . D $end
$var wire 1 / E $end
$var wire 1 0 X $end
$var wire 1 1 Y $end
$var wire 1 2 Z $end
$var wire 1 3 nor1 $end
$var wire 1 4 nor2 $end
$var wire 1 5 nor3 $end
$var wire 1 6 or1 $end
$var wire 1 7 xor1 $end
$var wire 1 8 xor2 $end
$upscope $end
$scope module d2u $end
$var wire 1 9 A $end
$var wire 1 : B $end
$var wire 1 ; C $end
$var wire 1 < D $end
$var wire 1 = E $end
$var wire 1 > X $end
$var wire 1 ? Y $end
$var wire 1 @ Z $end
$var wire 1 A nor1 $end
$var wire 1 B nor2 $end
$var wire 1 C nor3 $end
$var wire 1 D or1 $end
$var wire 1 E xor1 $end
$var wire 1 F xor2 $end
$upscope $end
$scope module d3v $end
$var wire 1 G A $end
$var wire 1 H B $end
$var wire 1 I C $end
$var wire 1 J D $end
$var wire 1 K E $end
$var wire 1 L X $end
$var wire 1 M Y $end
$var wire 1 N Z $end
$var wire 1 O nor1 $end
$var wire 1 P nor2 $end
$var wire 1 Q nor3 $end
$var wire 1 R or1 $end
$var wire 1 S xor1 $end
$var wire 1 T xor2 $end
$upscope $end
$scope module d4w $end
$var wire 1 % A $end
$var wire 1 U B $end
$var wire 1 V C $end
$var wire 1 W D $end
$var wire 1 X E $end
$var wire 1 Y X $end
$var wire 1 Z Y $end
$var wire 1 [ Z $end
$var wire 1 \ nor1 $end
$var wire 1 ] nor2 $end
$var wire 1 ^ nor3 $end
$var wire 1 _ or1 $end
$var wire 1 ` xor1 $end
$var wire 1 a xor2 $end
$upscope $end
$scope module d5x $end
$var wire 1 b A $end
$var wire 1 c B $end
$var wire 1 d C $end
$var wire 1 e D $end
$var wire 1 f E $end
$var wire 1 g X $end
$var wire 1 h Y $end
$var wire 1 i Z $end
$var wire 1 j nor1 $end
$var wire 1 k nor2 $end
$var wire 1 l nor3 $end
$var wire 1 m or1 $end
$var wire 1 n xor1 $end
$var wire 1 o xor2 $end
$upscope $end
$scope module d6y $end
$var wire 1 p A $end
$var wire 1 q B $end
$var wire 1 r C $end
$var wire 1 s D $end
$var wire 1 t E $end
$var wire 1 u X $end
$var wire 1 v Y $end
$var wire 1 w Z $end
$var wire 1 x nor1 $end
$var wire 1 y nor2 $end
$var wire 1 z nor3 $end
$var wire 1 { or1 $end
$var wire 1 | xor1 $end
$var wire 1 } xor2 $end
$upscope $end
$scope module d7z $end
$var wire 1 ~ A $end
$var wire 1 !" B $end
$var wire 1 "" C $end
$var wire 1 #" D $end
$var wire 1 $" E $end
$var wire 1 %" X $end
$var wire 1 &" Y $end
$var wire 1 '" Z $end
$var wire 1 (" nor1 $end
$var wire 1 )" nor2 $end
$var wire 1 *" nor3 $end
$var wire 1 +" or1 $end
$var wire 1 ," xor1 $end
$var wire 1 -" xor2 $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0-"
0,"
1+"
0*"
1)"
1("
0'"
0&"
0%"
0$"
0#"
0""
0!"
0~
0}
0|
1{
0z
1y
1x
0w
0v
0u
0t
0s
0r
0q
0p
0o
0n
1m
0l
1k
1j
0i
0h
0g
0f
0e
0d
0c
0b
0a
0`
1_
0^
1]
1\
0[
0Z
0Y
0X
0W
0V
0U
0T
0S
1R
0Q
1P
1O
0N
0M
0L
0K
0J
0I
0H
0G
0F
0E
1D
0C
1B
1A
0@
0?
0>
0=
0<
0;
0:
09
08
07
16
05
14
13
02
01
00
0/
0.
0-
0,
b0 +
b0 *
b0 )
b0 (
b0z '
b0 &
0%
0$
b0 #
b0 "
b0 !
$end
#10
1%"
1*"
0("
1!"
0k
b100 &
1i
1o
0P
1d
0)"
1S
b1000 (
1K
1,"
b10000 !
b10000 +
0$"
1J
1#"
b1010 "
b1010 #
#20
0%"
1$"
0*"
0y
b1000010 !
b1000010 +
1w
1("
1}
0!"
0]
1r
1k
b0 &
0i
1`
b100z '
1X
0o
1W
0d
1L
b1 (
0K
1Q
0O
1H
0B
b100 )
1@
1F
04
1;
17
b1000 *
1/
1.
b101010 "
b101010 #
#30
1&"
0+"
1v
0,"
1y
0{
1~
0u
1h
0z
0m
0x
1q
1c
0'"
1[
1N
0w
0|
0t
1-"
1a
1T
1O
0}
0s
0""
1%"
0$"
1V
1I
0H
0]
0r
0g
0f
1*"
1>
1=
b1001 )
0@
0`
b10z '
0X
0l
0("
1C
0D
0W
0n
0j
0!"
0A
0L
0b
1k
b10 &
0i
1:
0Q
0M
0o
b1100 *
12
0P
1R
0d
18
0S
b100 (
0K
b10011001 !
b10011001 +
1-
0J
b1100011 "
b1100011 #
#40
1w
1n
1b
1M
1}
1u
0R
1r
1z
0v
1`
b110z '
1X
1!"
0y
1{
1G
1W
1i
1|
0t
1?
1L
1m
1s
1""
1%"
1Q
0j
1g
1f
1*"
0)"
0O
0c
1l
0("
1-"
19
0H
0N
0k
0~
0:
11
1F
0@
1T
1o
b1101 &
0h
0&"
0'"
02
14
06
0;
0D
0I
0d
0+"
03
08
07
b10 *
0/
0E
b11 )
0=
0S
b11 (
0K
0,"
b101010011 !
b101010011 +
1$"
1,
0-
0.
1<
1J
0#"
b10011001 "
b10011001 #
#50
0t
1{
1w
0y
1}
1%"
0|
0u
1r
1*"
0s
0z
1X
1o
0("
0g
1x
0_
0l
0q
0c
0`
1j
b100z '
0[
0N
1Y
0W
1d
0b
1a
1^
0L
1K
b1000 (
0M
0&"
1V
0I
0H
0\
0F
0Q
1R
1>
0=
0@
1U
1S
1O
0T
1C
1D
10
0G
0~
1!"
1:
1E
0A
15
b1 )
0?
0h
1i
1-"
1'"
12
09
04
16
0;
1m
1""
1+"
18
01
17
b101 *
0/
1n
b1100 &
1f
1,"
b1001010101 !
b1001010101 +
0$"
1-
1.
1e
1#"
b11111111 "
b11111111 #
#60

2
verilog/ALU0.2/BinaryToBCD.vcdZone.Identifier Normal file
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[ZoneTransfer]
ZoneId=3

2
verilog/ALU0.2/BinaryToBCD.vZone.Identifier Normal file
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[ZoneTransfer]
ZoneId=3

40
verilog/ALU0.2/BinaryToBCDTB.v Normal file
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module BinaryToBCDTB;
// Testbench signals
reg [7:0] binary;
wire [11:0] bcd; // Output BCD
// Instantiate the BinaryToBCD module
BinaryToBCD uut (
.binary(binary),
.bcd(bcd)
);
// Testbench procedure
initial begin
$monitor("Time: %0t | Binary: %b | BCD: %b (Hundreds: %d, Tens: %d, Ones: %d)",
$time, binary, bcd, bcd[11:8], bcd[7:4], bcd[3:0]);
$dumpfile("BinaryToBCD.vcd");
$dumpvars;
// Test cases
binary = 8'b00000000; // Decimal: 0
#10;
binary = 8'b00001010; // Decimal: 10
#10;
binary = 8'b00101010; // Decimal: 42
#10;
binary = 8'b01100011; // Decimal: 99
#10;
binary = 8'b10011001; // Decimal: 153
#10;
binary = 8'b11111111; // Decimal: 255
#10;
// End simulation
$finish;
end
endmodule

2
verilog/ALU0.2/BinaryToBCDTB.vZone.Identifier Normal file
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[ZoneTransfer]
ZoneId=3

20
verilog/ALU0.2/addition.v Normal file
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module addition (
input [3:0] A, B,
input CarryIN,
output [3:0] Y,
output CarryOUT,
output overflow
);
wire [2:0] Carry4;
fulladder f0(.A(A[0]), .B(B[0]), .Carry(CarryIN), .Sum(Y[0]), .CarryO(Carry4[0]));
fulladder f1(.A(A[1]), .B(B[1]), .Carry(Carry4[0]), .Sum(Y[1]), .CarryO(Carry4[1]));
fulladder f2(.A(A[2]), .B(B[2]), .Carry(Carry4[1]), .Sum(Y[2]), .CarryO(Carry4[2]));
fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(CarryOUT));
//overflowDetect od1 (.opCode(2'b01), .A(A), .B(B), .Y(Y), .CarryOUT(CarryOUT), .overflowDetect(overflow)); (KULLANILMAYACAK!!!!)
xor ov1 (overflow, Carry4[2], CarryOUT);
endmodule

2
verilog/ALU0.2/addition.vZone.Identifier Normal file
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[ZoneTransfer]
ZoneId=3

33
verilog/ALU0.2/arithmeticUnit.v Normal file
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module arithmeticUnit (
input [1:0] opCode,
input [3:0] A, B,
input CarryIN,
output [3:0] add_Y, sub_Y,
output CarryOUT,
output overflow
);
wire [3:0] addY, subY;
wire CarryOUTADD, CarryOUTSUB, tempCAdd, tempCSub, tempoverflow;
addition a1(.A(A), .B(B), .CarryIN(CarryIN), .Y(addY), .CarryOUT(CarryOUTADD), .overflow(tempoverflow));
subtraction s1(.A(A), .B(B), .BorrowIN(CarryIN), .Y(subY), .BorrowOUT(CarryOUTSUB));
and add1 (add_Y[0], opCode[0], addY[0]);
and add2 (add_Y[1], opCode[0], addY[1]);
and add3 (add_Y[2], opCode[0], addY[2]);
and add4 (add_Y[3], opCode[0], addY[3]);
and sub1 (sub_Y[0], opCode[1], subY[0]);
and sub2 (sub_Y[1], opCode[1], subY[1]);
and sub3 (sub_Y[2], opCode[1], subY[2]);
and sub4 (sub_Y[3], opCode[1], subY[3]);
// or or1 (CarryOUT, CarryOUTADD, CarryOUTSUB); (OLD!!!)
and and10 (tempCSub, CarryOUTSUB, opCode[1]);
and and11 (tempCAdd, CarryOUTADD, opCode[0]);
or or4 (CarryOUT, tempCAdd, tempCSub);
and add12 (overflow, opCode[0], tempoverflow);
endmodule

2
verilog/ALU0.2/arithmeticUnit.vZone.Identifier Normal file
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[ZoneTransfer]
ZoneId=3

362
verilog/ALU0.2/binarytobcd Normal file
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x56140140d330 .scope module, "BinaryToBCDTB" "BinaryToBCDTB" 2 1;
.timescale 0 0;
v0x561401436a70_0 .net "bcd", 11 0, L_0x56140143cdd0; 1 drivers
v0x561401436b30_0 .var "binary", 7 0;
S_0x56140140a900 .scope module, "uut" "BinaryToBCD" 2 7, 3 1 0, S_0x56140140d330;
.timescale 0 0;
.port_info 0 /INPUT 8 "binary";
.port_info 1 /OUTPUT 12 "bcd";
L_0x7f952d86e018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x7f952d86e060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x561401413c60 .functor AND 1, L_0x7f952d86e018, L_0x7f952d86e060, C4<1>, C4<1>;
L_0x7f952d86e0a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x7f952d86e0f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x561401436c90 .functor AND 1, L_0x7f952d86e0a8, L_0x7f952d86e0f0, C4<1>, C4<1>;
L_0x7f952d86e138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x7f952d86e180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x561401436df0 .functor AND 1, L_0x7f952d86e138, L_0x7f952d86e180, C4<1>, C4<1>;
L_0x7f952d86e1c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x7f952d86e210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x561401436f80 .functor AND 1, L_0x7f952d86e1c8, L_0x7f952d86e210, C4<1>, C4<1>;
L_0x7f952d86e258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x56140143d200 .functor OR 1, L_0x56140143d2c0, L_0x7f952d86e258, C4<0>, C4<0>;
v0x561401435620_0 .net/2u *"_ivl_0", 0 0, L_0x7f952d86e018; 1 drivers
v0x561401435720_0 .net/2u *"_ivl_10", 0 0, L_0x7f952d86e138; 1 drivers
v0x561401435800_0 .net/2u *"_ivl_12", 0 0, L_0x7f952d86e180; 1 drivers
v0x5614014358c0_0 .net *"_ivl_132", 0 0, L_0x56140143d200; 1 drivers
v0x5614014359a0_0 .net *"_ivl_136", 0 0, L_0x56140143d2c0; 1 drivers
v0x561401435a80_0 .net/2u *"_ivl_137", 0 0, L_0x7f952d86e258; 1 drivers
v0x561401435b60_0 .net *"_ivl_14", 0 0, L_0x561401436f80; 1 drivers
o0x7f952d8b8e48 .functor BUFZ 1, C4<z>; HiZ drive
; Elide local net with no drivers, v0x561401435c40_0 name=_ivl_141
v0x561401435d20_0 .net/2u *"_ivl_16", 0 0, L_0x7f952d86e1c8; 1 drivers
v0x561401435e90_0 .net/2u *"_ivl_18", 0 0, L_0x7f952d86e210; 1 drivers
v0x561401435f70_0 .net/2u *"_ivl_2", 0 0, L_0x7f952d86e060; 1 drivers
v0x561401436050_0 .net/2u *"_ivl_4", 0 0, L_0x7f952d86e0a8; 1 drivers
v0x561401436130_0 .net/2u *"_ivl_6", 0 0, L_0x7f952d86e0f0; 1 drivers
v0x561401436210_0 .net *"_ivl_8", 0 0, L_0x561401436df0; 1 drivers
v0x5614014362f0_0 .net "bcd", 11 0, L_0x56140143cdd0; alias, 1 drivers
v0x5614014363d0_0 .net "binary", 7 0, v0x561401436b30_0; 1 drivers
v0x5614014364b0_0 .net "dab1", 3 0, L_0x561401437c20; 1 drivers
v0x561401436590_0 .net "dab2", 3 0, L_0x561401438a60; 1 drivers
v0x561401436670_0 .net "dab3", 3 0, L_0x561401439840; 1 drivers
v0x561401436750_0 .net "dab4", 3 0, L_0x56140143d510; 1 drivers
v0x561401436830_0 .net "dab5", 3 0, L_0x56140143b080; 1 drivers
v0x561401436910_0 .net "empty1", 0 0, L_0x561401413c60; 1 drivers
v0x5614014369b0_0 .net "empty2", 0 0, L_0x561401436c90; 1 drivers
L_0x561401437960 .part v0x561401436b30_0, 7, 1;
L_0x561401437a50 .part v0x561401436b30_0, 6, 1;
L_0x561401437af0 .part v0x561401436b30_0, 5, 1;
L_0x561401437c20 .concat8 [ 1 1 1 1], L_0x561401437500, L_0x561401437670, L_0x5614014377d0, L_0x561401437840;
L_0x561401438630 .part L_0x561401437c20, 1, 1;
L_0x561401438760 .part L_0x561401437c20, 2, 1;
L_0x561401438840 .part L_0x561401437c20, 3, 1;
L_0x561401438970 .part v0x561401436b30_0, 4, 1;
L_0x561401438a60 .concat8 [ 1 1 1 1], L_0x5614014381d0, L_0x561401438340, L_0x5614014384a0, L_0x561401438510;
L_0x5614014393d0 .part L_0x561401438a60, 1, 1;
L_0x561401439560 .part L_0x561401438a60, 2, 1;
L_0x561401439600 .part L_0x561401438a60, 3, 1;
L_0x5614014397a0 .part v0x561401436b30_0, 3, 1;
L_0x561401439840 .concat8 [ 1 1 1 1], L_0x561401438fb0, L_0x5614014390e0, L_0x561401439240, L_0x5614014392b0;
L_0x56140143a190 .part L_0x561401437c20, 0, 1;
L_0x56140143a230 .part L_0x561401438a60, 0, 1;
L_0x56140143a360 .part L_0x561401439840, 0, 1;
L_0x56140143acc0 .part L_0x561401439840, 1, 1;
L_0x56140143ae90 .part L_0x561401439840, 2, 1;
L_0x56140143af30 .part L_0x561401439840, 3, 1;
L_0x56140143adf0 .part v0x561401436b30_0, 2, 1;
L_0x56140143b080 .concat8 [ 1 1 1 1], L_0x56140143a8a0, L_0x56140143a9d0, L_0x56140143ab30, L_0x56140143aba0;
L_0x56140143bac0 .part L_0x56140143d510, 1, 1;
L_0x56140143bbf0 .part L_0x56140143d510, 2, 1;
L_0x56140143bd60 .part L_0x56140143d510, 3, 1;
L_0x56140143be00 .part L_0x56140143b080, 0, 1;
L_0x56140143c840 .part L_0x56140143b080, 1, 1;
L_0x56140143c970 .part L_0x56140143b080, 2, 1;
L_0x56140143cb90 .part L_0x56140143b080, 3, 1;
L_0x56140143cc30 .part v0x561401436b30_0, 1, 1;
LS_0x56140143cdd0_0_0 .concat8 [ 1 1 1 1], L_0x56140143d200, L_0x56140143c720, L_0x56140143c6b0, L_0x56140143c550;
LS_0x56140143cdd0_0_4 .concat8 [ 1 1 1 1], L_0x56140143c420, L_0x56140143b9a0, L_0x56140143b930, L_0x56140143b7d0;
LS_0x56140143cdd0_0_8 .concat8 [ 1 1 1 1], L_0x56140143b6a0, L_0x561401439d70, L_0x561401436f80, L_0x561401436df0;
L_0x56140143cdd0 .concat8 [ 4 4 4 0], LS_0x56140143cdd0_0_0, LS_0x56140143cdd0_0_4, LS_0x56140143cdd0_0_8;
L_0x56140143d2c0 .part v0x561401436b30_0, 0, 1;
L_0x56140143d510 .concat [ 1 1 1 1], o0x7f952d8b8e48, L_0x561401439ea0, L_0x56140143a000, L_0x56140143a070;
S_0x561401408560 .scope module, "d1t" "dabble" 3 14, 4 1 0, S_0x56140140a900;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C";
.port_info 3 /INPUT 1 "D";
.port_info 4 /OUTPUT 1 "X";
.port_info 5 /OUTPUT 1 "Y";
.port_info 6 /OUTPUT 1 "Z";
.port_info 7 /OUTPUT 1 "E";
L_0x5614014370c0 .functor XOR 1, L_0x561401413c60, L_0x561401437af0, C4<0>, C4<0>;
L_0x561401437130 .functor NOR 1, L_0x561401413c60, L_0x561401437960, C4<0>, C4<0>;
L_0x561401437200 .functor XOR 1, L_0x561401413c60, L_0x561401437a50, C4<0>, C4<0>;
L_0x5614014372d0 .functor NOR 1, L_0x5614014370c0, L_0x561401437200, C4<0>, C4<0>;
L_0x5614014373f0 .functor NOR 1, L_0x5614014372d0, L_0x561401437130, C4<0>, C4<0>;
L_0x561401437500 .functor BUF 1, L_0x5614014373f0, C4<0>, C4<0>, C4<0>;
L_0x561401437600 .functor OR 1, L_0x5614014370c0, L_0x561401437130, C4<0>, C4<0>;
L_0x561401437670 .functor NOR 1, L_0x561401437600, L_0x561401437a50, C4<0>, C4<0>;
L_0x5614014377d0 .functor AND 1, L_0x561401437600, L_0x561401437200, C4<1>, C4<1>;
L_0x561401437840 .functor XOR 1, L_0x5614014373f0, L_0x561401437af0, C4<0>, C4<0>;
v0x56140140b5f0_0 .net "A", 0 0, L_0x561401413c60; alias, 1 drivers
v0x56140140b2e0_0 .net "B", 0 0, L_0x561401437960; 1 drivers
v0x56140140afa0_0 .net "C", 0 0, L_0x561401437a50; 1 drivers
v0x561401412b80_0 .net "D", 0 0, L_0x561401437af0; 1 drivers
v0x561401412e90_0 .net "E", 0 0, L_0x561401437840; 1 drivers
v0x5614014131a0_0 .net "X", 0 0, L_0x561401437500; 1 drivers
v0x561401413450_0 .net "Y", 0 0, L_0x561401437670; 1 drivers
v0x56140142f5e0_0 .net "Z", 0 0, L_0x5614014377d0; 1 drivers
v0x56140142f6a0_0 .net "nor1", 0 0, L_0x561401437130; 1 drivers
v0x56140142f760_0 .net "nor2", 0 0, L_0x5614014372d0; 1 drivers
v0x56140142f820_0 .net "nor3", 0 0, L_0x5614014373f0; 1 drivers
v0x56140142f8e0_0 .net "or1", 0 0, L_0x561401437600; 1 drivers
v0x56140142f9a0_0 .net "xor1", 0 0, L_0x5614014370c0; 1 drivers
v0x56140142fa60_0 .net "xor2", 0 0, L_0x561401437200; 1 drivers
S_0x56140142fc20 .scope module, "d2u" "dabble" 3 23, 4 1 0, S_0x56140140a900;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C";
.port_info 3 /INPUT 1 "D";
.port_info 4 /OUTPUT 1 "X";
.port_info 5 /OUTPUT 1 "Y";
.port_info 6 /OUTPUT 1 "Z";
.port_info 7 /OUTPUT 1 "E";
L_0x561401437de0 .functor XOR 1, L_0x561401438630, L_0x561401438970, C4<0>, C4<0>;
L_0x561401437e50 .functor NOR 1, L_0x561401438630, L_0x561401438760, C4<0>, C4<0>;
L_0x561401437f10 .functor XOR 1, L_0x561401438630, L_0x561401438840, C4<0>, C4<0>;
L_0x561401437f80 .functor NOR 1, L_0x561401437de0, L_0x561401437f10, C4<0>, C4<0>;
L_0x5614014380c0 .functor NOR 1, L_0x561401437f80, L_0x561401437e50, C4<0>, C4<0>;
L_0x5614014381d0 .functor BUF 1, L_0x5614014380c0, C4<0>, C4<0>, C4<0>;
L_0x5614014382d0 .functor OR 1, L_0x561401437de0, L_0x561401437e50, C4<0>, C4<0>;
L_0x561401438340 .functor NOR 1, L_0x5614014382d0, L_0x561401438840, C4<0>, C4<0>;
L_0x5614014384a0 .functor AND 1, L_0x5614014382d0, L_0x561401437f10, C4<1>, C4<1>;
L_0x561401438510 .functor XOR 1, L_0x5614014380c0, L_0x561401438970, C4<0>, C4<0>;
v0x56140142fef0_0 .net "A", 0 0, L_0x561401438630; 1 drivers
v0x56140142ffb0_0 .net "B", 0 0, L_0x561401438760; 1 drivers
v0x561401430070_0 .net "C", 0 0, L_0x561401438840; 1 drivers
v0x561401430110_0 .net "D", 0 0, L_0x561401438970; 1 drivers
v0x5614014301d0_0 .net "E", 0 0, L_0x561401438510; 1 drivers
v0x5614014302e0_0 .net "X", 0 0, L_0x5614014381d0; 1 drivers
v0x5614014303a0_0 .net "Y", 0 0, L_0x561401438340; 1 drivers
v0x561401430460_0 .net "Z", 0 0, L_0x5614014384a0; 1 drivers
v0x561401430520_0 .net "nor1", 0 0, L_0x561401437e50; 1 drivers
v0x5614014305e0_0 .net "nor2", 0 0, L_0x561401437f80; 1 drivers
v0x5614014306a0_0 .net "nor3", 0 0, L_0x5614014380c0; 1 drivers
v0x561401430760_0 .net "or1", 0 0, L_0x5614014382d0; 1 drivers
v0x561401430820_0 .net "xor1", 0 0, L_0x561401437de0; 1 drivers
v0x5614014308e0_0 .net "xor2", 0 0, L_0x561401437f10; 1 drivers
S_0x561401430aa0 .scope module, "d3v" "dabble" 3 32, 4 1 0, S_0x56140140a900;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C";
.port_info 3 /INPUT 1 "D";
.port_info 4 /OUTPUT 1 "X";
.port_info 5 /OUTPUT 1 "Y";
.port_info 6 /OUTPUT 1 "Z";
.port_info 7 /OUTPUT 1 "E";
L_0x561401438bf0 .functor XOR 1, L_0x5614014393d0, L_0x5614014397a0, C4<0>, C4<0>;
L_0x561401438c60 .functor NOR 1, L_0x5614014393d0, L_0x561401439560, C4<0>, C4<0>;
L_0x561401438d20 .functor XOR 1, L_0x5614014393d0, L_0x561401439600, C4<0>, C4<0>;
L_0x561401438d90 .functor NOR 1, L_0x561401438bf0, L_0x561401438d20, C4<0>, C4<0>;
L_0x561401438ea0 .functor NOR 1, L_0x561401438d90, L_0x561401438c60, C4<0>, C4<0>;
L_0x561401438fb0 .functor BUF 1, L_0x561401438ea0, C4<0>, C4<0>, C4<0>;
L_0x561401439070 .functor OR 1, L_0x561401438bf0, L_0x561401438c60, C4<0>, C4<0>;
L_0x5614014390e0 .functor NOR 1, L_0x561401439070, L_0x561401439600, C4<0>, C4<0>;
L_0x561401439240 .functor AND 1, L_0x561401439070, L_0x561401438d20, C4<1>, C4<1>;
L_0x5614014392b0 .functor XOR 1, L_0x561401438ea0, L_0x5614014397a0, C4<0>, C4<0>;
v0x561401430d50_0 .net "A", 0 0, L_0x5614014393d0; 1 drivers
v0x561401430e10_0 .net "B", 0 0, L_0x561401439560; 1 drivers
v0x561401430ed0_0 .net "C", 0 0, L_0x561401439600; 1 drivers
v0x561401430f70_0 .net "D", 0 0, L_0x5614014397a0; 1 drivers
v0x561401431030_0 .net "E", 0 0, L_0x5614014392b0; 1 drivers
v0x561401431140_0 .net "X", 0 0, L_0x561401438fb0; 1 drivers
v0x561401431200_0 .net "Y", 0 0, L_0x5614014390e0; 1 drivers
v0x5614014312c0_0 .net "Z", 0 0, L_0x561401439240; 1 drivers
v0x561401431380_0 .net "nor1", 0 0, L_0x561401438c60; 1 drivers
v0x5614014314d0_0 .net "nor2", 0 0, L_0x561401438d90; 1 drivers
v0x561401431590_0 .net "nor3", 0 0, L_0x561401438ea0; 1 drivers
v0x561401431650_0 .net "or1", 0 0, L_0x561401439070; 1 drivers
v0x561401431710_0 .net "xor1", 0 0, L_0x561401438bf0; 1 drivers
v0x5614014317d0_0 .net "xor2", 0 0, L_0x561401438d20; 1 drivers
S_0x561401431990 .scope module, "d4w" "dabble" 3 41, 4 1 0, S_0x56140140a900;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C";
.port_info 3 /INPUT 1 "D";
.port_info 4 /OUTPUT 1 "X";
.port_info 5 /OUTPUT 1 "Y";
.port_info 6 /OUTPUT 1 "Z";
.port_info 7 /OUTPUT 1 "E";
L_0x561401439730 .functor XOR 1, L_0x561401436c90, L_0x56140143a360, C4<0>, C4<0>;
L_0x561401439a00 .functor NOR 1, L_0x561401436c90, L_0x56140143a190, C4<0>, C4<0>;
L_0x561401439b00 .functor XOR 1, L_0x561401436c90, L_0x56140143a230, C4<0>, C4<0>;
L_0x561401439b70 .functor NOR 1, L_0x561401439730, L_0x561401439b00, C4<0>, C4<0>;
L_0x561401439c60 .functor NOR 1, L_0x561401439b70, L_0x561401439a00, C4<0>, C4<0>;
L_0x561401439d70 .functor BUF 1, L_0x561401439c60, C4<0>, C4<0>, C4<0>;
L_0x561401439e30 .functor OR 1, L_0x561401439730, L_0x561401439a00, C4<0>, C4<0>;
L_0x561401439ea0 .functor NOR 1, L_0x561401439e30, L_0x56140143a230, C4<0>, C4<0>;
L_0x56140143a000 .functor AND 1, L_0x561401439e30, L_0x561401439b00, C4<1>, C4<1>;
L_0x56140143a070 .functor XOR 1, L_0x561401439c60, L_0x56140143a360, C4<0>, C4<0>;
v0x561401431c40_0 .net "A", 0 0, L_0x561401436c90; alias, 1 drivers
v0x561401431d20_0 .net "B", 0 0, L_0x56140143a190; 1 drivers
v0x561401431de0_0 .net "C", 0 0, L_0x56140143a230; 1 drivers
v0x561401431e80_0 .net "D", 0 0, L_0x56140143a360; 1 drivers
v0x561401431f40_0 .net "E", 0 0, L_0x56140143a070; 1 drivers
v0x561401432050_0 .net "X", 0 0, L_0x561401439d70; 1 drivers
v0x561401432110_0 .net "Y", 0 0, L_0x561401439ea0; 1 drivers
v0x5614014321d0_0 .net "Z", 0 0, L_0x56140143a000; 1 drivers
v0x561401432290_0 .net "nor1", 0 0, L_0x561401439a00; 1 drivers
v0x5614014323e0_0 .net "nor2", 0 0, L_0x561401439b70; 1 drivers
v0x5614014324a0_0 .net "nor3", 0 0, L_0x561401439c60; 1 drivers
v0x561401432560_0 .net "or1", 0 0, L_0x561401439e30; 1 drivers
v0x561401432620_0 .net "xor1", 0 0, L_0x561401439730; 1 drivers
v0x5614014326e0_0 .net "xor2", 0 0, L_0x561401439b00; 1 drivers
S_0x5614014328a0 .scope module, "d5x" "dabble" 3 50, 4 1 0, S_0x56140140a900;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C";
.port_info 3 /INPUT 1 "D";
.port_info 4 /OUTPUT 1 "X";
.port_info 5 /OUTPUT 1 "Y";
.port_info 6 /OUTPUT 1 "Z";
.port_info 7 /OUTPUT 1 "E";
L_0x56140143a450 .functor XOR 1, L_0x56140143acc0, L_0x56140143adf0, C4<0>, C4<0>;
L_0x56140143a4c0 .functor NOR 1, L_0x56140143acc0, L_0x56140143ae90, C4<0>, C4<0>;
L_0x56140143a580 .functor XOR 1, L_0x56140143acc0, L_0x56140143af30, C4<0>, C4<0>;
L_0x56140143a620 .functor NOR 1, L_0x56140143a450, L_0x56140143a580, C4<0>, C4<0>;
L_0x56140143a790 .functor NOR 1, L_0x56140143a620, L_0x56140143a4c0, C4<0>, C4<0>;
L_0x56140143a8a0 .functor BUF 1, L_0x56140143a790, C4<0>, C4<0>, C4<0>;
L_0x56140143a960 .functor OR 1, L_0x56140143a450, L_0x56140143a4c0, C4<0>, C4<0>;
L_0x56140143a9d0 .functor NOR 1, L_0x56140143a960, L_0x56140143af30, C4<0>, C4<0>;
L_0x56140143ab30 .functor AND 1, L_0x56140143a960, L_0x56140143a580, C4<1>, C4<1>;
L_0x56140143aba0 .functor XOR 1, L_0x56140143a790, L_0x56140143adf0, C4<0>, C4<0>;
v0x561401432ba0_0 .net "A", 0 0, L_0x56140143acc0; 1 drivers
v0x561401432c80_0 .net "B", 0 0, L_0x56140143ae90; 1 drivers
v0x561401432d40_0 .net "C", 0 0, L_0x56140143af30; 1 drivers
v0x561401432de0_0 .net "D", 0 0, L_0x56140143adf0; 1 drivers
v0x561401432ea0_0 .net "E", 0 0, L_0x56140143aba0; 1 drivers
v0x561401432fb0_0 .net "X", 0 0, L_0x56140143a8a0; 1 drivers
v0x561401433070_0 .net "Y", 0 0, L_0x56140143a9d0; 1 drivers
v0x561401433130_0 .net "Z", 0 0, L_0x56140143ab30; 1 drivers
v0x5614014331f0_0 .net "nor1", 0 0, L_0x56140143a4c0; 1 drivers
v0x561401433340_0 .net "nor2", 0 0, L_0x56140143a620; 1 drivers
v0x561401433400_0 .net "nor3", 0 0, L_0x56140143a790; 1 drivers
v0x5614014334c0_0 .net "or1", 0 0, L_0x56140143a960; 1 drivers
v0x561401433580_0 .net "xor1", 0 0, L_0x56140143a450; 1 drivers
v0x561401433640_0 .net "xor2", 0 0, L_0x56140143a580; 1 drivers
S_0x561401433800 .scope module, "d6y" "dabble" 3 59, 4 1 0, S_0x56140140a900;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C";
.port_info 3 /INPUT 1 "D";
.port_info 4 /OUTPUT 1 "X";
.port_info 5 /OUTPUT 1 "Y";
.port_info 6 /OUTPUT 1 "Z";
.port_info 7 /OUTPUT 1 "E";
L_0x56140143b280 .functor XOR 1, L_0x56140143bac0, L_0x56140143be00, C4<0>, C4<0>;
L_0x56140143b2f0 .functor NOR 1, L_0x56140143bac0, L_0x56140143bbf0, C4<0>, C4<0>;
L_0x56140143b3b0 .functor XOR 1, L_0x56140143bac0, L_0x56140143bd60, C4<0>, C4<0>;
L_0x56140143b420 .functor NOR 1, L_0x56140143b280, L_0x56140143b3b0, C4<0>, C4<0>;
L_0x56140143b590 .functor NOR 1, L_0x56140143b420, L_0x56140143b2f0, C4<0>, C4<0>;
L_0x56140143b6a0 .functor BUF 1, L_0x56140143b590, C4<0>, C4<0>, C4<0>;
L_0x56140143b760 .functor OR 1, L_0x56140143b280, L_0x56140143b2f0, C4<0>, C4<0>;
L_0x56140143b7d0 .functor NOR 1, L_0x56140143b760, L_0x56140143bd60, C4<0>, C4<0>;
L_0x56140143b930 .functor AND 1, L_0x56140143b760, L_0x56140143b3b0, C4<1>, C4<1>;
L_0x56140143b9a0 .functor XOR 1, L_0x56140143b590, L_0x56140143be00, C4<0>, C4<0>;
v0x561401433ab0_0 .net "A", 0 0, L_0x56140143bac0; 1 drivers
v0x561401433b90_0 .net "B", 0 0, L_0x56140143bbf0; 1 drivers
v0x561401433c50_0 .net "C", 0 0, L_0x56140143bd60; 1 drivers
v0x561401433cf0_0 .net "D", 0 0, L_0x56140143be00; 1 drivers
v0x561401433db0_0 .net "E", 0 0, L_0x56140143b9a0; 1 drivers
v0x561401433ec0_0 .net "X", 0 0, L_0x56140143b6a0; 1 drivers
v0x561401433f80_0 .net "Y", 0 0, L_0x56140143b7d0; 1 drivers
v0x561401434040_0 .net "Z", 0 0, L_0x56140143b930; 1 drivers
v0x561401434100_0 .net "nor1", 0 0, L_0x56140143b2f0; 1 drivers
v0x561401434250_0 .net "nor2", 0 0, L_0x56140143b420; 1 drivers
v0x561401434310_0 .net "nor3", 0 0, L_0x56140143b590; 1 drivers
v0x5614014343d0_0 .net "or1", 0 0, L_0x56140143b760; 1 drivers
v0x561401434490_0 .net "xor1", 0 0, L_0x56140143b280; 1 drivers
v0x561401434550_0 .net "xor2", 0 0, L_0x56140143b3b0; 1 drivers
S_0x561401434710 .scope module, "d7z" "dabble" 3 68, 4 1 0, S_0x56140140a900;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C";
.port_info 3 /INPUT 1 "D";
.port_info 4 /OUTPUT 1 "X";
.port_info 5 /OUTPUT 1 "Y";
.port_info 6 /OUTPUT 1 "Z";
.port_info 7 /OUTPUT 1 "E";
L_0x56140143bfd0 .functor XOR 1, L_0x56140143c840, L_0x56140143cc30, C4<0>, C4<0>;
L_0x56140143c040 .functor NOR 1, L_0x56140143c840, L_0x56140143c970, C4<0>, C4<0>;
L_0x56140143c100 .functor XOR 1, L_0x56140143c840, L_0x56140143cb90, C4<0>, C4<0>;
L_0x56140143c1a0 .functor NOR 1, L_0x56140143bfd0, L_0x56140143c100, C4<0>, C4<0>;
L_0x56140143c310 .functor NOR 1, L_0x56140143c1a0, L_0x56140143c040, C4<0>, C4<0>;
L_0x56140143c420 .functor BUF 1, L_0x56140143c310, C4<0>, C4<0>, C4<0>;
L_0x56140143c4e0 .functor OR 1, L_0x56140143bfd0, L_0x56140143c040, C4<0>, C4<0>;
L_0x56140143c550 .functor NOR 1, L_0x56140143c4e0, L_0x56140143cb90, C4<0>, C4<0>;
L_0x56140143c6b0 .functor AND 1, L_0x56140143c4e0, L_0x56140143c100, C4<1>, C4<1>;
L_0x56140143c720 .functor XOR 1, L_0x56140143c310, L_0x56140143cc30, C4<0>, C4<0>;
v0x5614014349c0_0 .net "A", 0 0, L_0x56140143c840; 1 drivers
v0x561401434aa0_0 .net "B", 0 0, L_0x56140143c970; 1 drivers
v0x561401434b60_0 .net "C", 0 0, L_0x56140143cb90; 1 drivers
v0x561401434c00_0 .net "D", 0 0, L_0x56140143cc30; 1 drivers
v0x561401434cc0_0 .net "E", 0 0, L_0x56140143c720; 1 drivers
v0x561401434dd0_0 .net "X", 0 0, L_0x56140143c420; 1 drivers
v0x561401434e90_0 .net "Y", 0 0, L_0x56140143c550; 1 drivers
v0x561401434f50_0 .net "Z", 0 0, L_0x56140143c6b0; 1 drivers
v0x561401435010_0 .net "nor1", 0 0, L_0x56140143c040; 1 drivers
v0x561401435160_0 .net "nor2", 0 0, L_0x56140143c1a0; 1 drivers
v0x561401435220_0 .net "nor3", 0 0, L_0x56140143c310; 1 drivers
v0x5614014352e0_0 .net "or1", 0 0, L_0x56140143c4e0; 1 drivers
v0x5614014353a0_0 .net "xor1", 0 0, L_0x56140143bfd0; 1 drivers
v0x561401435460_0 .net "xor2", 0 0, L_0x56140143c100; 1 drivers
.scope S_0x56140140d330;
T_0 ;
%vpi_call 2 14 "$monitor", "Time: %0t | Binary: %b | BCD: %b (Hundreds: %d, Tens: %d, Ones: %d)", $time, v0x561401436b30_0, v0x561401436a70_0, &PV<v0x561401436a70_0, 8, 4>, &PV<v0x561401436a70_0, 4, 4>, &PV<v0x561401436a70_0, 0, 4> {0 0 0};
%vpi_call 2 16 "$dumpfile", "BinaryToBCD.vcd" {0 0 0};
%vpi_call 2 17 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 8;
%store/vec4 v0x561401436b30_0, 0, 8;
%delay 10, 0;
%pushi/vec4 10, 0, 8;
%store/vec4 v0x561401436b30_0, 0, 8;
%delay 10, 0;
%pushi/vec4 42, 0, 8;
%store/vec4 v0x561401436b30_0, 0, 8;
%delay 10, 0;
%pushi/vec4 99, 0, 8;
%store/vec4 v0x561401436b30_0, 0, 8;
%delay 10, 0;
%pushi/vec4 153, 0, 8;
%store/vec4 v0x561401436b30_0, 0, 8;
%delay 10, 0;
%pushi/vec4 255, 0, 8;
%store/vec4 v0x561401436b30_0, 0, 8;
%delay 10, 0;
%vpi_call 2 38 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 5;
"N/A";
"<interactive>";
"BinaryToBCDTB.v";
"BinaryToBCD.v";
"dabble.v";

2
verilog/ALU0.2/binarytobcdZone.Identifier Normal file
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@ -0,0 +1,2 @@
[ZoneTransfer]
ZoneId=3

52
verilog/ALU0.2/dabble Normal file
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x5621d16e7df0 .scope module, "dabble" "dabble" 2 1;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C";
.port_info 3 /INPUT 1 "D";
.port_info 4 /OUTPUT 1 "X";
.port_info 5 /OUTPUT 1 "Y";
.port_info 6 /OUTPUT 1 "Z";
.port_info 7 /OUTPUT 1 "E";
o0x7f27d282c018 .functor BUFZ 1, C4<z>; HiZ drive
o0x7f27d282c0a8 .functor BUFZ 1, C4<z>; HiZ drive
L_0x5621d1732e70 .functor XOR 1, o0x7f27d282c018, o0x7f27d282c0a8, C4<0>, C4<0>;
o0x7f27d282c048 .functor BUFZ 1, C4<z>; HiZ drive
L_0x5621d1732f60 .functor NOR 1, o0x7f27d282c018, o0x7f27d282c048, C4<0>, C4<0>;
o0x7f27d282c078 .functor BUFZ 1, C4<z>; HiZ drive
L_0x5621d1733000 .functor XOR 1, o0x7f27d282c018, o0x7f27d282c078, C4<0>, C4<0>;
L_0x5621d17330d0 .functor NOR 1, L_0x5621d1732e70, L_0x5621d1733000, C4<0>, C4<0>;
L_0x5621d1733240 .functor NOR 1, L_0x5621d17330d0, L_0x5621d1732f60, C4<0>, C4<0>;
L_0x5621d1733350 .functor BUF 1, L_0x5621d1733240, C4<0>, C4<0>, C4<0>;
L_0x5621d1733450 .functor OR 1, L_0x5621d1732e70, L_0x5621d1732f60, C4<0>, C4<0>;
L_0x5621d17334c0 .functor NOR 1, L_0x5621d1733450, o0x7f27d282c078, C4<0>, C4<0>;
L_0x5621d1733620 .functor AND 1, L_0x5621d1733450, L_0x5621d1733000, C4<1>, C4<1>;
L_0x5621d1733690 .functor XOR 1, L_0x5621d1733240, o0x7f27d282c0a8, C4<0>, C4<0>;
v0x5621d16e8050_0 .net "A", 0 0, o0x7f27d282c018; 0 drivers
v0x5621d1732380_0 .net "B", 0 0, o0x7f27d282c048; 0 drivers
v0x5621d1732440_0 .net "C", 0 0, o0x7f27d282c078; 0 drivers
v0x5621d17324e0_0 .net "D", 0 0, o0x7f27d282c0a8; 0 drivers
v0x5621d17325a0_0 .net "E", 0 0, L_0x5621d1733690; 1 drivers
v0x5621d17326b0_0 .net "X", 0 0, L_0x5621d1733350; 1 drivers
v0x5621d1732770_0 .net "Y", 0 0, L_0x5621d17334c0; 1 drivers
v0x5621d1732830_0 .net "Z", 0 0, L_0x5621d1733620; 1 drivers
v0x5621d17328f0_0 .net "nor1", 0 0, L_0x5621d1732f60; 1 drivers
v0x5621d17329b0_0 .net "nor2", 0 0, L_0x5621d17330d0; 1 drivers
v0x5621d1732a70_0 .net "nor3", 0 0, L_0x5621d1733240; 1 drivers
v0x5621d1732b30_0 .net "or1", 0 0, L_0x5621d1733450; 1 drivers
v0x5621d1732bf0_0 .net "xor1", 0 0, L_0x5621d1732e70; 1 drivers
v0x5621d1732cb0_0 .net "xor2", 0 0, L_0x5621d1733000; 1 drivers
# The file index is used to find the file name in the following table.
:file_names 3;
"N/A";
"<interactive>";
"dabble.v";

22
verilog/ALU0.2/dabble.v Normal file
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module dabble (
input A, B, C, D,
output X, Y, Z, E
);
wire xor1, nor1, xor2, nor2, nor3, or1;
xor xo1 (xor1, A, D);
nor no1 (nor1, A, B);
xor xo2 (xor2, A, C);
nor no2 (nor2, xor1, xor2);
nor no3 (nor3, nor2, nor1);
buf bu1 (X, nor3);
or o1 (or1, xor1, nor1);
nor no4 (Y, or1, C);
and an1 (Z, or1, xor2);
xor xo3 (E, nor3, D);
endmodule

2
verilog/ALU0.2/dabble.vZone.Identifier Normal file
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[ZoneTransfer]
ZoneId=3

2
verilog/ALU0.2/dabbleZone.Identifier Normal file
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[ZoneTransfer]
ZoneId=3

11
verilog/ALU0.2/divider.v Normal file
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@ -0,0 +1,11 @@
module divider (
input [3:0] D,
input [1:0] d,
output [2:0] R,
output [3:0] Q
);
wire s1,y1,c1;
dividerpu d1 (.A(D[3]), .B(d[0]), .Cin(1'b1), .S(s1), .Y(y1), .COut(c1));
dividerpu d2 (.A(1'b0), .B(d[1]), .Cin(c1), .S(s1), .Y(y1), .COut(c1));

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