kaltinsoy
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  • Joined on 2023-10-16
Repositories
9
 Projects Packages Public Activity Starred Repositories
kaltinsoy pushed to main at kaltinsoy/C 2025-02-06 10:22:41 +03:00
c71ffdd716 Chapter4
kaltinsoy pushed to main at kaltinsoy/C 2025-02-06 01:56:02 +03:00
08ec3be7a9 Chapter4
kaltinsoy pushed to main at kaltinsoy/C 2025-02-05 07:54:52 +03:00
0b7e3b6cb0 Chapter4
kaltinsoy pushed to main at kaltinsoy/C 2025-02-04 09:09:12 +03:00
4e7fa1b23f scanf return test
kaltinsoy pushed to main at kaltinsoy/C 2025-02-04 08:13:29 +03:00
8e36a1a11c Chapter3
kaltinsoy pushed to main at kaltinsoy/verilog 2025-02-03 22:47:01 +03:00
ee84dbe799 lab7
kaltinsoy pushed to main at kaltinsoy/C 2025-02-03 08:39:12 +03:00
bb35fb2db6 chapter3
kaltinsoy pushed to main at kaltinsoy/verilog 2025-02-01 06:35:38 +03:00
1d5ff13ca1 labs
57c2935e1c lab7
85dbb22740 lab6
Compare 3 commits »
kaltinsoy pushed to main at kaltinsoy/verilog 2025-01-26 06:06:07 +03:00
1b0958962c lab5
kaltinsoy pushed to main at kaltinsoy/verilog 2025-01-25 08:00:45 +03:00
7605bbf473 lab5
kaltinsoy pushed to main at kaltinsoy/verilog 2025-01-25 03:15:16 +03:00
c5e6bb95a0 lab4
kaltinsoy pushed to main at kaltinsoy/verilog 2025-01-23 07:58:51 +03:00
0f359fa8a4 f# fix
kaltinsoy pushed to main at kaltinsoy/4-bit-ALU 2025-01-23 07:57:16 +03:00
c34a3aa203 fixed
kaltinsoy pushed to main at kaltinsoy/4-bit-ALU 2025-01-23 07:56:21 +03:00
d4d35b4983 gowin impl removed because f#
kaltinsoy pushed to main at kaltinsoy/4-bit-ALU 2025-01-23 07:51:55 +03:00
91280fbab2 small fix
f233866913 small fix
Compare 2 commits »
kaltinsoy pushed to main at kaltinsoy/4-bit-ALU 2025-01-23 07:34:42 +03:00
0659f966b8 small fix
kaltinsoy pushed to main at kaltinsoy/4-bit-ALU 2025-01-23 07:26:40 +03:00
806d09692f small fix
kaltinsoy pushed to main at kaltinsoy/4-bit-ALU 2025-01-23 07:23:03 +03:00
2cf2de94d9 small changes
kaltinsoy pushed to main at kaltinsoy/4-bit-ALU 2025-01-23 07:17:06 +03:00
6080927957 small changes
kaltinsoy pushed to main at kaltinsoy/4-bit-ALU 2025-01-23 07:15:25 +03:00
5b3ff5bf91 Fix Verilog syntax highlighting