29 lines
395 B
Verilog
29 lines
395 B
Verilog
module tb();
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reg r1, r2;
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wire w1, w2, w3;
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test uut(
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.A(r1),
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.B(r2),
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.LED1(w1),
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.LED2(w2),
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.LED3(w3)
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);
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// test uut(r1, r2, w1, w2, w3);
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initial begin
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$dumpfile("dmp.vcd");
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$dumpvars;
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r1 = 0; r2 = 0; #10;
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r1 = 0; r2 = 1; #10;
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r1 = 1; r2 = 0; #10;
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$display(w3);
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r1 = 1; r2 = 1; #10;
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$display(w3);
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end
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endmodule |