kaltinsoy/verilog
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k0rrluna c5af5cfeda ALU & multiplication
2024-12-21 18:05:27 +03:00
gowin/OldBit3-ledTest
subtraction & multiplier
2024-12-20 21:28:15 +03:00
iverilog
subtraction & multiplier
2024-12-20 21:28:15 +03:00
project
opCode fixes
2024-12-15 04:25:43 +03:00
project0.2
ALU & multiplication
2024-12-21 18:05:27 +03:00
Description
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2 MiB
Languages
Verilog 99.2%
Shell 0.5%
Coq 0.3%