145 lines
2.1 KiB
Plaintext
145 lines
2.1 KiB
Plaintext
//
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//Written by GowinSynthesis
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//Tool Version "V1.9.9.02"
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//Sat May 4 01:07:38 2024
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//Source file index table:
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//file0 "\C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v"
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//file1 "\C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v"
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//file2 "\C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v"
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`timescale 100 ps/100 ps
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module halfAdder (
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A_d,
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B_d,
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C_d
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)
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;
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input [1:0] A_d;
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input [1:0] B_d;
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output [1:1] C_d;
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wire VCC;
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wire GND;
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LUT4 C_d_1_s (
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.F(C_d[1]),
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.I0(A_d[1]),
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.I1(B_d[0]),
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.I2(A_d[0]),
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.I3(B_d[1])
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);
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defparam C_d_1_s.INIT=16'h7888;
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VCC VCC_cZ (
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.V(VCC)
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);
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GND GND_cZ (
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.G(GND)
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);
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endmodule /* halfAdder */
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module halfAdder_0 (
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A_d,
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B_d,
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C_d
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)
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;
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input [1:0] A_d;
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input [1:0] B_d;
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output [3:2] C_d;
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wire VCC;
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wire GND;
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LUT4 C_d_3_s (
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.F(C_d[3]),
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.I0(A_d[0]),
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.I1(B_d[0]),
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.I2(A_d[1]),
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.I3(B_d[1])
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);
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defparam C_d_3_s.INIT=16'h7000;
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LUT4 C_d_2_s (
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.F(C_d[2]),
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.I0(A_d[1]),
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.I1(B_d[0]),
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.I2(A_d[0]),
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.I3(B_d[1])
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);
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defparam C_d_2_s.INIT=16'h8000;
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VCC VCC_cZ (
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.V(VCC)
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);
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GND GND_cZ (
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.G(GND)
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);
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endmodule /* halfAdder_0 */
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module mult2bit (
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A,
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B,
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C
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)
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;
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input [1:0] A;
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input [1:0] B;
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output [3:0] C;
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wire [1:0] A_d;
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wire [1:0] B_d;
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wire [0:0] C_d;
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wire [1:1] C_d_0;
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wire [3:2] C_d_1;
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wire VCC;
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wire GND;
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IBUF A_0_ibuf (
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.O(A_d[0]),
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.I(A[0])
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);
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IBUF A_1_ibuf (
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.O(A_d[1]),
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.I(A[1])
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);
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IBUF B_0_ibuf (
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.O(B_d[0]),
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.I(B[0])
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);
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IBUF B_1_ibuf (
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.O(B_d[1]),
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.I(B[1])
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);
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OBUF C_0_obuf (
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.O(C[0]),
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.I(C_d[0])
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);
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OBUF C_1_obuf (
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.O(C[1]),
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.I(C_d_0[1])
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);
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OBUF C_2_obuf (
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.O(C[2]),
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.I(C_d_1[2])
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);
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OBUF C_3_obuf (
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.O(C[3]),
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.I(C_d_1[3])
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);
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LUT2 C_d_0_s (
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.F(C_d[0]),
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.I0(B_d[0]),
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.I1(A_d[0])
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);
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defparam C_d_0_s.INIT=4'h8;
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halfAdder h0 (
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.A_d(A_d[1:0]),
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.B_d(B_d[1:0]),
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.C_d(C_d_0[1])
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);
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halfAdder_0 h1 (
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.A_d(A_d[1:0]),
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.B_d(B_d[1:0]),
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.C_d(C_d_1[3:2])
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);
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VCC VCC_cZ (
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.V(VCC)
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);
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GND GND_cZ (
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.G(GND)
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);
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GSR GSR (
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.GSRI(VCC)
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);
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endmodule /* mult2bit */
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