//
//Written by GowinSynthesis
//Tool Version "V1.9.9.02"
//Sat May  4 01:07:38 2024

//Source file index table:
//file0 "\C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v"
//file1 "\C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v"
//file2 "\C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v"
`timescale 100 ps/100 ps
module halfAdder (
  A_d,
  B_d,
  C_d
)
;
input [1:0] A_d;
input [1:0] B_d;
output [1:1] C_d;
wire VCC;
wire GND;
  LUT4 C_d_1_s (
    .F(C_d[1]),
    .I0(A_d[1]),
    .I1(B_d[0]),
    .I2(A_d[0]),
    .I3(B_d[1]) 
);
defparam C_d_1_s.INIT=16'h7888;
  VCC VCC_cZ (
    .V(VCC)
);
  GND GND_cZ (
    .G(GND)
);
endmodule /* halfAdder */
module halfAdder_0 (
  A_d,
  B_d,
  C_d
)
;
input [1:0] A_d;
input [1:0] B_d;
output [3:2] C_d;
wire VCC;
wire GND;
  LUT4 C_d_3_s (
    .F(C_d[3]),
    .I0(A_d[0]),
    .I1(B_d[0]),
    .I2(A_d[1]),
    .I3(B_d[1]) 
);
defparam C_d_3_s.INIT=16'h7000;
  LUT4 C_d_2_s (
    .F(C_d[2]),
    .I0(A_d[1]),
    .I1(B_d[0]),
    .I2(A_d[0]),
    .I3(B_d[1]) 
);
defparam C_d_2_s.INIT=16'h8000;
  VCC VCC_cZ (
    .V(VCC)
);
  GND GND_cZ (
    .G(GND)
);
endmodule /* halfAdder_0 */
module mult2bit (
  A,
  B,
  C
)
;
input [1:0] A;
input [1:0] B;
output [3:0] C;
wire [1:0] A_d;
wire [1:0] B_d;
wire [0:0] C_d;
wire [1:1] C_d_0;
wire [3:2] C_d_1;
wire VCC;
wire GND;
  IBUF A_0_ibuf (
    .O(A_d[0]),
    .I(A[0]) 
);
  IBUF A_1_ibuf (
    .O(A_d[1]),
    .I(A[1]) 
);
  IBUF B_0_ibuf (
    .O(B_d[0]),
    .I(B[0]) 
);
  IBUF B_1_ibuf (
    .O(B_d[1]),
    .I(B[1]) 
);
  OBUF C_0_obuf (
    .O(C[0]),
    .I(C_d[0]) 
);
  OBUF C_1_obuf (
    .O(C[1]),
    .I(C_d_0[1]) 
);
  OBUF C_2_obuf (
    .O(C[2]),
    .I(C_d_1[2]) 
);
  OBUF C_3_obuf (
    .O(C[3]),
    .I(C_d_1[3]) 
);
  LUT2 C_d_0_s (
    .F(C_d[0]),
    .I0(B_d[0]),
    .I1(A_d[0]) 
);
defparam C_d_0_s.INIT=4'h8;
  halfAdder h0 (
    .A_d(A_d[1:0]),
    .B_d(B_d[1:0]),
    .C_d(C_d_0[1])
);
  halfAdder_0 h1 (
    .A_d(A_d[1:0]),
    .B_d(B_d[1:0]),
    .C_d(C_d_1[3:2])
);
  VCC VCC_cZ (
    .V(VCC)
);
  GND GND_cZ (
    .G(GND)
);
  GSR GSR (
    .GSRI(VCC) 
);
endmodule /* mult2bit */