82 lines
3.0 KiB
Plaintext
82 lines
3.0 KiB
Plaintext
[
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{
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"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v",
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"InstLine" : 1,
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"InstName" : "ledTest",
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"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v",
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"ModuleLine" : 1,
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"ModuleName" : "ledTest",
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"SubInsts" : [
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{
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"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v",
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"InstLine" : 8,
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"InstName" : "adder",
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"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
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"ModuleLine" : 1,
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"ModuleName" : "bit3adder",
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"SubInsts" : [
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{
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"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
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"InstLine" : 9,
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"InstName" : "ha0",
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"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
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"ModuleLine" : 1,
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"ModuleName" : "halfadder"
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},
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{
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"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
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"InstLine" : 10,
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"InstName" : "fa0",
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"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
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"ModuleLine" : 1,
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"ModuleName" : "fulladder",
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"SubInsts" : [
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{
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"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
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"InstLine" : 8,
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"InstName" : "ha1",
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"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
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"ModuleLine" : 1,
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"ModuleName" : "halfadder"
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},
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{
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"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
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"InstLine" : 9,
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"InstName" : "ha2",
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"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
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"ModuleLine" : 1,
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"ModuleName" : "halfadder"
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}
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]
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},
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{
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"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v",
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"InstLine" : 11,
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"InstName" : "fa1",
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"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
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"ModuleLine" : 1,
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"ModuleName" : "fulladder",
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"SubInsts" : [
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{
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"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
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"InstLine" : 8,
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"InstName" : "ha1",
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"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
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"ModuleLine" : 1,
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"ModuleName" : "halfadder"
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},
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{
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"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v",
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"InstLine" : 9,
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"InstName" : "ha2",
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"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v",
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"ModuleLine" : 1,
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"ModuleName" : "halfadder"
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}
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]
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}
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]
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}
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]
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}
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] |