[ { "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v", "InstLine" : 1, "InstName" : "ledTest", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v", "ModuleLine" : 1, "ModuleName" : "ledTest", "SubInsts" : [ { "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/ledTest.v", "InstLine" : 8, "InstName" : "adder", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v", "ModuleLine" : 1, "ModuleName" : "bit3adder", "SubInsts" : [ { "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v", "InstLine" : 9, "InstName" : "ha0", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v", "ModuleLine" : 1, "ModuleName" : "halfadder" }, { "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v", "InstLine" : 10, "InstName" : "fa0", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v", "ModuleLine" : 1, "ModuleName" : "fulladder", "SubInsts" : [ { "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v", "InstLine" : 8, "InstName" : "ha1", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v", "ModuleLine" : 1, "ModuleName" : "halfadder" }, { "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v", "InstLine" : 9, "InstName" : "ha2", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v", "ModuleLine" : 1, "ModuleName" : "halfadder" } ] }, { "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/bit3adder.v", "InstLine" : 11, "InstName" : "fa1", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v", "ModuleLine" : 1, "ModuleName" : "fulladder", "SubInsts" : [ { "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v", "InstLine" : 8, "InstName" : "ha1", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v", "ModuleLine" : 1, "ModuleName" : "halfadder" }, { "InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/fulladder.v", "InstLine" : 9, "InstName" : "ha2", "ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/fpga_project/src/halfadder.v", "ModuleLine" : 1, "ModuleName" : "halfadder" } ] } ] } ] } ]