34 lines
2.4 KiB
XML
34 lines
2.4 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE gowin-synthesis-project>
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<Project>
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<Version>beta</Version>
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<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
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<FileList>
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<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v" type="verilog"/>
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<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v" type="verilog"/>
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<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v" type="verilog"/>
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<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v" type="verilog"/>
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<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v" type="verilog"/>
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<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v" type="verilog"/>
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<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v" type="verilog"/>
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<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v" type="verilog"/>
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<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v" type="verilog"/>
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<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v" type="verilog"/>
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<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v" type="verilog"/>
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<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v" type="verilog"/>
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<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v" type="verilog"/>
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<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v" type="verilog"/>
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<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v" type="verilog"/>
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</FileList>
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<OptionList>
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<Option type="disable_insert_pad" value="0"/>
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<Option type="global_freq" value="100.000"/>
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<Option type="looplimit" value="2000"/>
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<Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg"/>
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<Option type="print_all_synthesis_warning" value="0"/>
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<Option type="ram_rw_check" value="0"/>
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<Option type="verilog_language" value="verilog-2001"/>
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<Option type="vhdl_language" value="vhdl-1993"/>
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</OptionList>
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</Project>
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