123 lines
922 B
Plaintext
123 lines
922 B
Plaintext
$date
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Mon Jul 8 05:12:15 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module timerTB $end
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$var wire 6 ! count [5:0] $end
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$var reg 1 " clock $end
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$var reg 3 # counter [2:0] $end
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$var reg 1 $ gate $end
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$var reg 1 % reset $end
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$var reg 1 & way $end
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$scope module uut $end
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$var wire 1 " clock $end
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$var wire 3 ' counter [2:0] $end
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$var wire 1 $ gate $end
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$var wire 1 % reset $end
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$var wire 1 & way $end
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$var reg 6 ( count [5:0] $end
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$var reg 6 ) countReg [5:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b101011 )
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b101011 (
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b10 '
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1&
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1%
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1$
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b10 #
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0"
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b101011 !
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$end
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#5
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b0 !
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b0 (
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b0 )
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1"
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#10
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0"
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#15
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1"
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#20
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0"
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#25
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1"
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#30
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0"
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#35
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1"
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#40
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0"
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#45
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1"
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#50
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0"
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#55
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1"
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#60
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0"
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#65
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1"
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#70
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0"
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#75
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1"
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#80
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0"
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#85
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1"
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#90
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0"
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#95
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1"
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#100
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0"
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#105
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1"
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#110
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0"
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#115
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1"
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#120
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0"
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#125
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1"
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#130
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0"
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#135
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1"
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#140
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0"
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#145
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1"
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#150
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0"
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#155
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1"
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#160
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0"
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#165
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1"
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#170
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0"
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#175
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1"
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#180
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0"
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#185
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1"
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#190
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0"
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#195
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1"
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#200
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0"
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