13 lines
241 B
Verilog
13 lines
241 B
Verilog
module bit3adder(
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input [2:0] A,
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input [2:0] B,
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output [3:0] C
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);
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wire c1,c2,c3,c4;
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halfadder ha0(A[0], B[0], C[0], c1);
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fulladder fa0(A[1], B[1], c1, C[1], c2);
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fulladder fa1(A[2], B[2], c2, C[2], C[3]);
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endmodule |