27 lines
397 B
Verilog
27 lines
397 B
Verilog
module ALUtb();
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reg [3:0] A,B;
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reg CarryIN;
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reg [2:0] opCodeA;
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wire CarryOUT, overflow;
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wire [7:0] Y;
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ALU uut (
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.A(A),
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.B(B),
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.CarryIN(CarryIN),
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.opCodeA(opCodeA),
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.CarryOUT(CarryOUT),
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.overflow(overflow),
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.Y(Y)
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);
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initial begin
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$dumpfile("ALU.vcd");
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$dumpvars;
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A = 4'b1111; B = 4'b0001; CarryIN = 1'b0; opCodeA = 3'b001; #5;
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$finish;
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end
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endmodule
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