30 lines
703 B
Verilog
30 lines
703 B
Verilog
module overflowDetect (
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input [1:0] opCode,
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input [3:0] A, B,
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input [3:0] Y,
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input CarryOUT,
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output overflowDetect
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);
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wire opC;
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wire sign1, sign2, sign3, sign4;
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wire addOverflow, subOverflow;
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wire detect1, detect2;
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or o1 (opC, opCode[0], opCode[1]); //check add or sub
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xnor xno1 (sign1, A[3], B[3]); // A B same sign
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xor xo2 (sign3, A[3], B[3]); // A and B opposite sign
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xor xo1 (sign2, Y[3], A[3]); // A and Sum opposite sign
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and a01 (addOverflow, sign1, opCode[0]); // A B same for add
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and a02 (subOverflow, sign3, opCode[1]); // A B diff for sub
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or o2 (detect1, addOverflow, subOverflow);
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and a03(detect2, detect1, sign2);
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and a04(overflowDetect, opC, detect2);
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endmodule
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