16 lines
203 B
Verilog
16 lines
203 B
Verilog
module test2Tb();
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reg [3:0] a;
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wire [6:0] b;
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test2 uut(a,b);
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initial begin
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$dumpfile("test2v.vcd");
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$dumpvars;
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$display("Success!");
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a = 4'd5; #10;
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$finish;
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end
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endmodule |