18 lines
200 B
Verilog
18 lines
200 B
Verilog
module hello_tb();
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reg A;
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reg B;
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wire C, D;
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initial begin
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$dumpfile("dmp.vcd");
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$dumpvars;
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A = 0; B = 0; #10;
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A = 0; B = 1; #10;
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A = 1; B = 0; #10;
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A = 1; B = 1; #10;
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$finish;
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end
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endmodule
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